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2018-08-02TEE-302: add support for i.MX 8MMSilvano di Ninno
reuse most of the i.mx 8mq supports. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02MLK-17909 RNG Instantation with basic Job RingCedric Neveux
- Add RNG Handles instantation using basic Job Ring - Increment TRNG entropy configuration in case of failure Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
2018-08-02MLK-17927 Remove OCOTP CSU protection.Clement Faure
The normal world and secure world have both R/W access to OCOTP now. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2018-08-02MLK-18036-2 Add dt_find_ocram_tz_addr() functionClement Faure
The OCRAM space allocated to optee is Trustzone protected. Only the begin address of the protection is specifiable. This function fetches the address of the node to protect in the dtb. Nodes to protect are specified by its compatible string in tz_ocram_match[] tab. This function defines the beginning the start address of the TZ ocram space. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2018-08-02MLK-18036-1 Add dt_overwrite_reg_node() functionClement Faure
dt_overwrite() overwrites specified properties in the device tree. Properties to overwrite and new properties are also specified in the device tree. The format is the following : overw_str = <&node_1 prop_1 ... prop_n>, <&node_2 prop_1 ... prop_n>, ... <&node_n prop_1 ... prop_n>; prop_n variables are 32bit integers. Signed-off-by: Clement Faure <clement.faure@nxp.com>
2018-08-02TEE-243-4 Add OCRAM as service initCedric Neveux
- Add a OCRAM initialization as a service init - Function is called automatically at boot and no need to call it at suspend time Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-08-02TEE-307 :Enable CAAM clock for imx7ulpFranck LENORMAND
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2018-08-02MLK-18005 core: arm: a9: set SMP for i.MX6SLLPeng Fan
The SMP bit needs to be make ldrex/strex instruction work properly. Fixes: 21aeeaa2301f6bc ("MLK-17962-2 core: arm: imx: a9: tune ACTLR") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02MLK-17797: [i.MX6SX-ARD]OPTEE: kernel panic with sdcard image and nfs ↵Silvano di Ninno
bootup.100% Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02core: arm: imx: 6sx: correct PL310_AUX_CTRL_INITPeng Fan
The PL310_AUX_CTRL_INIT should have - 16kb way size (bit19:17=3b001) - 16-way associciativity (bit16=1) Fixes: e934a0507ee496 ("MLK-17962-3 core: arm: imx: tune PL310 configuration") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02MLK-17962-4 core: arm: imx: handle errata 845369Peng Fan
Under very rare timing circumstances, a data corruption might occur on a dirty cache line that is evicted from the L1 Data Cache due to another cache line being entirely written. Configurations affected: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. This register is encoded as CP15 c15 0 c0 1. The bit can be written in Secure state only, with the following Read/Modify/Write code sequence: MRC p15,0,rt,c15,c0,1 ORR rt,rt,#0x00400000 MCR p15,0,rt,c15,c0,1 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02MLK-17962-3 core: arm: imx: tune PL310 configurationPeng Fan
The current tag/data ram, prefetch value is not the best value. With this, the performance is not good. So retune the value to match i.MX design to have good performance. Also there is PL310 errata that we need to disable Double linefill for version below r3p2 pl310. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02MLK-17962-2 core: arm: imx: a9: tune ACTLRPeng Fan
Tune ACTLR. To SLL, the value is 0xE at runtime. To others, the value should be 0x4F at runtime. Bit3 will be enabled when enable L2. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02MLK-17962-1 core: arm: imx: a7: set L1 Data prefetchPeng Fan
The default value of L1PCTL field in ACTLR is 0x3, which is "3 outstanding pre-fetches permitted", the value should not be override with 0 to decrease the performance. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02MLK-17791: [i.MX6SL-EVK]OPTEE:Kernel panic with sdcard image and nfs bootup.Silvano di Ninno
i.MX 6SL EVK board has 1GB DDR adjust the configuration to match this. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02MMIOT-4-3: SDP memory mapped without cache enabled to prevent MMU predictive ↵Olivier Masse
read When RDC is used to protect SDP instead of TZASC, the CPU do not have read access to the memory region. Then when the MMU tries to fill the cache with predictive read, cache line get zeros instead of correct value. Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2018-08-02MLK-17519 : Fix TZASC secure region configuration for optee-os on imx7dClement Faure
- The memory is divided in 4 TZASC regions: Region 0 : Maps all the available memory. Secure and Non-Secure, RW Region 1 : Maps all the DDR. Non-secure, RW Region 2 : Maps the TZ RAM. Secure, RW Region 3 : Maps the Shared Memory. Secure and Non-Secure, RW - The priority of a region increases with the region number. - A region is enabled as soon as the region is configured. - Region Start and Size: Region 0 : 0x00000000 (4G) Region 1 : 0x80000000 (2G) Region 2 : 0xbe000000 (32M) Region 3 : 0xbfe00000 (2M) Signed-off-by: Clement Faure <clement.faure@nxp.com>
2018-08-02[MLK-17816]-2 : Fix CSU configuration for OCRAM TZ protectionClement Faure
Signed-off-by: Clement Faure <clement.faure@nxp.com>
2018-08-02[MLK-17816]-1 : Remove duplicated code for OCRAM TZ configurationClement Faure
Signed-off-by: Clement Faure <clement.faure@nxp.com>
2018-08-02basic pm frameworkSilvano di Ninno
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02soc definition updateSilvano di Ninno
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02core: arm: imx: Add imx8mq evk board supportPeng Fan
Add support for i.MX 8mscale (AARCH64) Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02core: arm: imx: Add imx7ulp evk board supportPeng Fan
Add support for i.MX 7ulp SoC TODO some cleanup on the header files Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02driver: imx_wdog: update wdog support for i.MX 7ulp SoCPeng Fan
update watchdog support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02drivers: imx_lpuart: add i.MX lpuart driverPeng Fan
add new lpuart driver This driver is used by the i.MX 7ulp SoC Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02MLK-17082-02 core: arm: imx: Add imx6sll evk board supportBai Ping
Add i.MX6SLL EVK board support. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-02MLK-17082-01 core: arm: imx: Add imx6sl evk board supportBai Ping
Add i.MX6SL EVK board support. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-02TEE-244 drivers: caam: CAAM InitializationCedric Neveux
- Add CAAM controller to initialize the JR Owner Allow Non-secure world access to Job Rings - Add RNG entropy configuration CAAM control Block 0 registers are not accessible by the CPU running in Non-Secure world and so can not configure the RNG entropy. However, the default register settings is not suitable on every SoC. This is the case for i.MX 6SX and because the RNG entropy is not configured correctly, the NS SW can not do the RNG instantiation Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-08-02TEE-244: core: arm: imx: add clock definitionSilvano di Ninno
Add clock module registers definition for i.MX6 and i.MX7 Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02core: arm: imx: add tzasc configurationPeng Fan
Add tzasc configuration for imx platforms. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02TEE-247 core: arm: imx: add some default configurationSilvano di Ninno
- Add default configuration to all the imx platform to avoid passing them to the command line - Add some more board definition that are edrived from already available SoC support Please note the Change in configuration for the 6Q/D/DL from CFG_BOOT_SYNC_CPU = y to n Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02TEE-247 core: arm: imx: move gpc file to plat-imxSilvano di Ninno
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02core: arm: imx: merged imx6ul/6/7 into single fileSilvano di Ninno
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02TEE-243 core: arm: imx: Add SCU moduleCedric Neveux
Add a SCU module Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-08-02TEE-243 core: arm: imx: Add CSU moduleCedric Neveux
Centralize CSU settings in one file Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-08-02TEE-242 core: arm: imx: add imx6 soc definitionSilvano di Ninno
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2018-08-02TEE-243 core: arm: imx Rework registersCedric Neveux
- Move registers to subdirectory - Rename registers to be almost common Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-08-02core: arm: imx: create standalone config file for different SoCsPeng Fan
Create standalone config file for different SoCs Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-08-02drivers: imx_wdog driver cleanupSilvano di Ninno
use WDT_WCR defined in watchdog specific imx_wdog.h instead of WCR_OFF defined in the platform imx-regs.h Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2018-06-28core: make stack trace robustJens Wiklander
Makes stack trace robust by checking addresses before copying data. Kernel stack traces are a bit more relaxed as we have crashed already. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 AArch32, Aarch64) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno, QEMU) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-06-28core: fix offset in assign_mobj_to_param_mem()Jens Wiklander
Prior to this patch assign_mobj_to_param_mem() stored the offset supplied with a non-contiguous buffer in mem->offs. Since that offset already is stored inside the resulting MOBJ that offset is added twice. This patch fixes this by initializing mem->offs to 0 instead. Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-06-27core: arm64: update max pa after discovered nsec ddrJens Wiklander
Once non-secure DDR is discovered either via FDT or via register_ddr() maximum output address is updated. Note that is only has an effect in AArch64. Fixes: https://github.com/OP-TEE/optee_os/issues/2402 Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Suggested-by: Jean-Paul Etienne <jean-paul.etienne@arm.com> Reported-by: Rouven Czerwinski <rouven@czerwinskis.de> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno, FVP) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-06-27core: arm64.h: add TCR_EL1_IPS_MASKJens Wiklander
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-06-27plat-stm: fix MIN/MAX macro issue in platform_config.hEtienne Carriere
Use MIN_UNSAFE/MAX_UNSAFE macros as MAX/MIN macros fail to build from in current platform_config.h imaplement with the error trace below: In file included from core/arch/arm/include/arm.h:8:0, from core/arch/arm/include/kernel/thread.h:11, from core/arch/arm/kernel/asm-defines.c:7: lib/libutils/ext/include/util.h:24:16: error: missing binary operator before token "(" (__extension__({ __typeof__(a) _a = (a); \ ^ core/arch/arm/plat-stm/./platform_config.h:190:25: note: in expansion of macro ‘MAX’ #define STM_SECDDR_END MAX(TZSRAM_BASE + TZSRAM_SIZE, \ ^~~ core/arch/arm/plat-stm/./platform_config.h:204:6: note: in expansion of macro ‘STM_SECDDR_END’ #if (STM_SECDDR_END < 0x80000000ULL) ^~~~~~~~~~~~~~ make: *** [out/core/include/generated/.asm-defines.s] Error 1 Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-06-26drivers: tzc380: fix tzc_configure_region apiSilvano di Ninno
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2018-06-20benchmark: change the way of timestamp buffer allocation.Igor Opaniuk
In case if timestamp buffer is allocated in userspace and new register user memory API is used for its registering in OP-TEE (introduced in optee_client commit 27888d73d156 ("tee_client_api: register user memory")), there is no possibility to keep this mapping permanent among different TEEC_InvokeCommand invocations, as all SHM are automatically unmapped from OP-TEE VA space after TEEC_InvokeCommand is handled by OP-TEE. Timestamp buffer is now allocated with thread_rpc_alloc_global_payload(). Fixes: https://github.com/OP-TEE/optee_os/issues/1979 Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
2018-06-19core: support for global shared buffersIgor Opaniuk
Add support of allocating SHM shared with non-secure kernel and exported to a non-secure userspace application. Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
2018-06-19core: tee: update objectSize/keySize for ECDSA/ECDH ObjectsSahil Malhotra
objectSize/keySize was not getting updated when an ECDSA/ECDH object was imported. Updating the ObjectSize/keySize based on the EC Curve. Fixes: https://github.com/OP-TEE/optee_os/issues/2386 Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-06-19plat-stm32mp1: reformat OP-TEE images to stm32 formatEtienne Carriere
OP-TEE core images are reformatted into a STM32 compliant format expected by the platform flashing tools. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-06-19core: stm32_uart driverEtienne Carriere
Used by platform stm32mp1. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 09:27:41 +0000