core: arm: imx: merged imx6ul/6/7 into single file

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>

6 files changed, 47 insertions, 109 deletions

diff --git a/core/arch/arm/plat-imx/imx.h b/core/arch/arm/plat-imx/imx.h
index afcde28e..51550d06 100644
--- a/core/arch/arm/plat-imx/imx.h
+++ b/core/arch/arm/plat-imx/imx.h
@@ -42,4 +42,8 @@ TEE_Result csu_init(void);
 #ifdef CFG_SCU
 void scu_init(void);
 #endif
+
+#if defined(CFG_BOOT_SYNC_CPU)
+void psci_boot_allcpus(void);
+#endif
 #endif
diff --git a/core/arch/arm/plat-imx/imx6.c b/core/arch/arm/plat-imx/imx6.c
deleted file mode 100644
index e8885587..00000000
--- a/core/arch/arm/plat-imx/imx6.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: BSD-2-Clause
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- * Copyright (c) 2016, Wind River Systems.
- * All rights reserved.
- * Copyright 2018 NXP
- */
-#include <imx.h>
-#include <io.h>
-#include <kernel/tz_ssvce_pl310.h>
-#include <kernel/generic_boot.h>
-#include <kernel/misc.h>
-#include <mm/core_memprot.h>
-#include <mm/core_mmu.h>
-#include <platform_config.h>
-
-register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE);
-
-void plat_cpu_reset_late(void)
-{
-	uint32_t pa __maybe_unused;
-
-	if (!get_core_pos()) {
-		/* primary core */
-#if defined(CFG_BOOT_SYNC_CPU)
-		pa = virt_to_phys((void *)TEE_TEXT_VA_START);
-		/* set secondary entry address and release core */
-		write32(pa, SRC_BASE + SRC_GPR1 + 8);
-		write32(pa, SRC_BASE + SRC_GPR1 + 16);
-		write32(pa, SRC_BASE + SRC_GPR1 + 24);
-
-		write32(BM_SRC_SCR_CPU_ENABLE_ALL, SRC_BASE + SRC_SCR);
-#endif
-
-#ifdef CFG_SCU
-		scu_init();
-#endif
-
-#ifdef CFG_CSU
-		/* configure imx6 CSU */
-		csu_init();
-#endif
-	}
-}
diff --git a/core/arch/arm/plat-imx/imx6ul.c b/core/arch/arm/plat-imx/imx6ul.c
deleted file mode 100644
index 0a2c207e..00000000
--- a/core/arch/arm/plat-imx/imx6ul.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: BSD-2-Clause
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
- * Peng Fan <peng.fan@nxp.com>
- */
-
-#include <imx.h>
-#include <kernel/generic_boot.h>
-#include <platform_config.h>
-
-
-/* MMU not enabled now */
-void plat_cpu_reset_late(void)
-{
-#ifdef CFG_CSU
-	csu_init();
-#endif
-}
diff --git a/core/arch/arm/plat-imx/imx7.c b/core/arch/arm/plat-imx/imx7.c
deleted file mode 100644
index 6f6f0c10..00000000
--- a/core/arch/arm/plat-imx/imx7.c
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: BSD-2-Clause
-/*
- * Copyright 2017-2018 NXP
- *
- * Peng Fan <peng.fan@nxp.com>
- */
-#include <imx.h>
-#include <kernel/generic_boot.h>
-#include <kernel/misc.h>
-#include <platform_config.h>
-
-void plat_cpu_reset_late(void)
-{
-	if (get_core_pos() != 0)
-		return;
-
-#ifdef CFG_CSU
-	csu_init();
-#endif
-}
diff --git a/core/arch/arm/plat-imx/main.c b/core/arch/arm/plat-imx/main.c
index 9dd757cd..34332d34 100644
--- a/core/arch/arm/plat-imx/main.c
+++ b/core/arch/arm/plat-imx/main.c
@@ -3,35 +3,15 @@
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  * Copyright (c) 2016, Wind River Systems.
  * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Copyright 2018 NXP
  */
 
-#include <arm32.h>
+#include <arm.h>
 #include <console.h>
 #include <drivers/gic.h>
 #include <drivers/imx_uart.h>
 #include <io.h>
+#include <imx.h>
 #include <kernel/generic_boot.h>
 #include <kernel/misc.h>
 #include <kernel/panic.h>
@@ -142,3 +122,41 @@ void main_secondary_init_gic(void)
 	gic_cpu_init(&gic_data);
 }
 #endif
+
+#if defined(CFG_BOOT_SYNC_CPU)
+void psci_boot_allcpus(void)
+{
+	vaddr_t src_base = core_mmu_get_va(SRC_BASE, MEM_AREA_TEE_COHERENT);
+	uint32_t pa = virt_to_phys((void *)TEE_TEXT_VA_START);
+
+	/* set secondary entry address and release core */
+	write32(pa, src_base + SRC_GPR1 + 8);
+	write32(pa, src_base + SRC_GPR1 + 16);
+	write32(pa, src_base + SRC_GPR1 + 24);
+
+	write32(BM_SRC_SCR_CPU_ENABLE_ALL, src_base + SRC_SCR);
+}
+#endif
+
+/*
+ * Platform CPU reset late function executed with MMU
+ * OFF. The CSU must be initialized here to allow
+ * access to Non-Secure Memory from Secure code without
+ * aborting
+ */
+void plat_cpu_reset_late(void)
+{
+	if (get_core_pos() == 0) {
+#if defined(CFG_BOOT_SYNC_CPU)
+		psci_boot_allcpus();
+#endif
+
+#ifdef CFG_SCU
+		scu_init();
+#endif
+
+#ifdef CFG_CSU
+		csu_init();
+#endif
+	}
+}
diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk
index 3094644a..fd355e38 100644
--- a/core/arch/arm/plat-imx/sub.mk
+++ b/core/arch/arm/plat-imx/sub.mk
@@ -12,16 +12,15 @@ endif
 
 ifneq (,$(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
        $(CFG_MX6SX)))
-srcs-y += a9_plat_init.S imx6.c
+srcs-y += a9_plat_init.S
 srcs-$(CFG_SM_PLATFORM_HANDLER) += sm_platform_handler.c
 endif
 
 ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL)))
 srcs-y += a7_plat_init.S
-srcs-y += imx6ul.c
 endif
 
-srcs-$(CFG_MX7) += imx7.c a7_plat_init.S
+srcs-$(CFG_MX7) += a7_plat_init.S
 
 subdirs-$(CFG_PSCI_ARM32) += pm
 srcs-$(CFG_CSU) += imx_csu.c