MLK-17082-02 core: arm: imx: Add imx6sll evk board support

Add i.MX6SLL EVK board support.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

6 files changed, 154 insertions, 10 deletions

diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index 11b8a424..7bb0e190 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -7,7 +7,7 @@ mx6q-flavorlist = mx6qsabrelite mx6qsabresd mx6qsabreauto
 mx6qp-flavorlist = mx6qpsabresd mx6qpsabreauto
 mx6s-flavorlist =
 mx6sl-flavorlist = mx6slevk
-mx6sll-flavorlist =
+mx6sll-flavorlist = mx6sllevk
 mx6sx-flavorlist = mx6sxsabresd mx6sxsabreauto
 mx6ul-flavorlist = mx6ulevk mx6ul9x9evk
 mx6ull-flavorlist = mx6ullevk
@@ -50,6 +50,10 @@ else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
 $(call force,CFG_MX6,y)
 $(call force,CFG_MX6SL,y)
 $(call force,CFG_TEE_CORE_NB_CORE,1)
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
+$(call force,CFG_MX6,y)
+$(call force,CFG_MX6SLL,y)
+$(call force,CFG_TEE_CORE_NB_CORE,1)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
 $(call force,CFG_MX7,y)
 $(call force,CFG_TEE_CORE_NB_CORE,2)
@@ -82,9 +86,9 @@ $(call force,CFG_BOOT_SYNC_CPU,n)
 $(call force,CFG_BOOT_SECONDARY_REQUEST,n)
 endif
 
-# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
+# i.MX6 Solo/SL/SLL/SoloX/DualLite/Dual/Quad specific config
 ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) \
-      $(CFG_MX6S) $(CFG_MX6SX) $(CFG_MX6SL)), y)
+      $(CFG_MX6S) $(CFG_MX6SX) $(CFG_MX6SL) $(CFG_MX6SLL)), y)
 include core/arch/arm/cpu/cortex-a9.mk
 $(call force,CFG_MX6,y)
 $(call force,CFG_PL310,y)
@@ -256,6 +260,16 @@ CFG_BOOT_SYNC_CPU = n
 CFG_BOOT_SECONDARY_REQUEST = n
 endif
 
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
+CFG_DT ?= y
+CFG_NS_ENTRY_ADDR ?= 0x80800000
+CFG_DT_ADDR ?= 0x83000000
+CFG_DDR_SIZE ?= 0x80000000
+CFG_PSCI_ARM32 ?= y
+CFG_BOOT_SYNC_CPU = n
+CFG_BOOT_SECONDARY_REQUEST = n
+endif
+
 ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
 CFG_DT ?= y
 CFG_NS_ENTRY_ADDR ?= 0x80800000
diff --git a/core/arch/arm/plat-imx/config/imx6sll.h b/core/arch/arm/plat-imx/config/imx6sll.h
new file mode 100644
index 00000000..27415369
--- /dev/null
+++ b/core/arch/arm/plat-imx/config/imx6sll.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#ifndef _CONFIG_IMX6SLL_H
+#define _CONFIG_IMX6SLL_H
+
+#ifndef CFG_UART_BASE
+#define CFG_UART_BASE	(UART1_BASE)
+#endif
+
+#define DRAM0_BASE		0x80000000
+#define DRAM0_SIZE		CFG_DDR_SIZE
+
+#define CONSOLE_UART_BASE	(CFG_UART_BASE)
+
+/*
+ * PL310 TAG RAM Control Register
+ *
+ * bit[10:8]:1 - 2 cycle of write accesses latency
+ * bit[6:4]:1 - 2 cycle of read accesses latency
+ * bit[2:0]:1 - 2 cycle of setup latency
+ */
+#ifndef PL310_TAG_RAM_CTRL_INIT
+#define PL310_TAG_RAM_CTRL_INIT		0x00000111
+#endif
+
+/*
+ * PL310 DATA RAM Control Register
+ *
+ * bit[10:8]:2 - 3 cycle of write accesses latency
+ * bit[6:4]:2 - 3 cycle of read accesses latency
+ * bit[2:0]:2 - 3 cycle of setup latency
+ */
+#ifndef PL310_DATA_RAM_CTRL_INIT
+#define PL310_DATA_RAM_CTRL_INIT	0x00000222
+#endif
+
+/*
+ * PL310 Auxiliary Control Register
+ *
+ * I/Dcache prefetch enabled (bit29:28=2b11)
+ * NS can access interrupts (bit27=1)
+ * NS can lockown cache lines (bit26=1)
+ * Pseudo-random replacement policy (bit25=0)
+ * Force write allocated (default)
+ * Shared attribute internally ignored (bit22=1, bit13=0)
+ * Parity disabled (bit21=0)
+ * Event monitor disabled (bit20=0)
+ * Platform fmavor specific way config (dual / quad):
+ * - 64kb way size (bit19:17=3b011)
+ * - 16-way associciativity (bit16=1)
+ * Platform fmavor specific way config (dual lite / solo):
+ * - 32kb way size (bit19:17=3b010)
+ * - no 16-way associciativity (bit16=0)
+ * Store buffer device limitation enabled (bit11=1)
+ * Cacheable accesses have high prio (bit10=0)
+ * Full Line Zero (FLZ) disabled (bit0=0)
+ */
+#ifndef PL310_AUX_CTRL_INIT
+#define PL310_AUX_CTRL_INIT		0x3C430800
+#endif
+
+/*
+ * PL310 Prefetch Control Register
+ *
+ * Double linefill disabled (bit30=0)
+ * I/D prefetch enabled (bit29:28=2b11)
+ * Prefetch drop enabled (bit24=1)
+ * Incr double linefill disable (bit23=0)
+ * Prefetch offset = 7 (bit4:0)
+ */
+#define PL310_PREFETCH_CTRL_INIT	0x31000007
+
+/*
+ * PL310 Power Register
+ *
+ * Dynamic clock gating enabled
+ * Standby mode enabled
+ */
+#define PL310_POWER_CTRL_INIT		0x00000003
+
+/*
+ * SCU Invalidate Register
+ *
+ * Invalidate all registers
+ */
+#define	SCU_INV_CTRL_INIT		0xFFFFFFFF
+
+/*
+ * SCU Access Register
+ * - both secure CPU access SCU
+ */
+#define SCU_SAC_CTRL_INIT		0x0000000F
+
+/*
+ * SCU NonSecure Access Register
+ * - both nonsec cpu access SCU, private and global timer
+ */
+#define SCU_NSAC_CTRL_INIT		0x00000FFF
+
+#endif
diff --git a/core/arch/arm/plat-imx/imx_csu.c b/core/arch/arm/plat-imx/imx_csu.c
index 5f8205c6..e0e398c8 100644
--- a/core/arch/arm/plat-imx/imx_csu.c
+++ b/core/arch/arm/plat-imx/imx_csu.c
@@ -63,7 +63,7 @@ TEE_Result csu_init(void)
 		csu_setting = csu_setting_imx6sx;
 	} else if (soc_is_imx6ul() || soc_is_imx6ull()) {
 		csu_setting = csu_setting_imx6ul;
-	} else if (soc_is_imx6sl()) {
+	} else if (soc_is_imx6sll() || soc_is_imx6sl()) {
 		csu_setting = csu_setting_imx6sl;
 	} else if (soc_is_imx6()) {
 		csu_setting = csu_setting_imx6;
diff --git a/core/arch/arm/plat-imx/platform_config.h b/core/arch/arm/plat-imx/platform_config.h
index 0f1c3cdf..c00e65f1 100644
--- a/core/arch/arm/plat-imx/platform_config.h
+++ b/core/arch/arm/plat-imx/platform_config.h
@@ -42,11 +42,6 @@
 #if defined(CFG_MX7)
 /* For i.MX7D/S platforms */
 #include <config/imx7.h>
-#elif defined(CFG_MX6SX)
-#include <config/imx6sx.h>
-#elif defined(CFG_MX6UL) || defined(CFG_MX6ULL)
-/* For i.MX 6UltraLite and 6ULL EVK board */
-#include <config/imx6ul.h>
 #elif defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D) || \
 	defined(CFG_MX6DL) || defined(CFG_MX6S)
 /* For i.MX6 Quad SABRE Lite and Smart Device board */
@@ -54,6 +49,14 @@
 /* For i.MX 6SL */
 #elif defined(CFG_MX6SL)
 #include <config/imx6sl.h>
+/* For i.MX 6SLL */
+#elif defined(CFG_MX6SLL)
+#include <config/imx6sll.h>
+#elif defined(CFG_MX6SX)
+#include <config/imx6sx.h>
+#elif defined(CFG_MX6UL) || defined(CFG_MX6ULL)
+/* For i.MX 6UltraLite and 6ULL EVK board */
+#include <config/imx6ul.h>
 #else
 #error "Unknown platform flavor"
 #endif
diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk
index cff570cb..a86754da 100644
--- a/core/arch/arm/plat-imx/sub.mk
+++ b/core/arch/arm/plat-imx/sub.mk
@@ -12,7 +12,7 @@ asm-defines-y += imx_pm_asm_defines.c
 endif
 
 ifneq (,$(filter y, $(CFG_MX6Q) $(CFG_MX6QP) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
- 	$(CFG_MX6SL) $(CFG_MX6SX)))
+	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)))
 srcs-y += a9_plat_init.S
 srcs-$(CFG_SM_PLATFORM_HANDLER) += sm_platform_handler.c
 endif
diff --git a/core/arch/arm/plat-imx/tzasc.c b/core/arch/arm/plat-imx/tzasc.c
index bb199495..fa2171b8 100644
--- a/core/arch/arm/plat-imx/tzasc.c
+++ b/core/arch/arm/plat-imx/tzasc.c
@@ -226,6 +226,29 @@ static int board_imx_tzasc_configure(vaddr_t addr)
 
 	return 0;
 }
+
+#elif defined(PLATFORM_FLAVOR_mx6sllevk)
+static int board_imx_tzasc_configure(vaddr_t addr)
+{
+	tzc_init(addr);
+
+	tzc_configure_region(0, 0x00000000,
+		TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
+		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
+	tzc_configure_region(1, 0x80000000,
+		TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_2G) |
+		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_NS_RW);
+	tzc_configure_region(2, 0xfe000000,
+		TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) |
+		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW);
+	tzc_configure_region(3, 0xffe00000,
+		TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_2M) |
+		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
+
+	tzc_dump_state();
+
+	return 0;
+}
 #elif defined(PLATFORM_FLAVOR_mx7dsabresd)
 static int board_imx_tzasc_configure(vaddr_t addr)
 {