core: arm: imx: create standalone config file for different SoCs

Create standalone config file for different SoCs

Signed-off-by: Peng Fan <peng.fan@nxp.com>

6 files changed, 272 insertions, 208 deletions

diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index e046da06..aa63fe77 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -1,60 +1,55 @@
 PLATFORM_FLAVOR ?= mx6ulevk
 
 # Get SoC associated with the PLATFORM_FLAVOR
-mx6ul-flavorlist = mx6ulevk
-mx6ull-flavorlist = mx6ullevk
-mx6q-flavorlist = mx6qsabrelite mx6qsabresd
-mx6sx-flavorlist = mx6sxsabreauto
 mx6d-flavorlist =
 mx6dl-flavorlist = mx6dlsabresd
+mx6q-flavorlist = mx6qsabrelite mx6qsabresd
 mx6s-flavorlist =
-mx7-flavorlist = mx7dsabresd mx7swarp7
+mx6sx-flavorlist = mx6sxsabreauto
+mx6ul-flavorlist = mx6ulevk
+mx6ull-flavorlist = mx6ullevk
+mx7d-flavorlist = mx7dsabresd
+mx7s-flavorlist = mx7swarp7
 
 ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
 $(call force,CFG_MX6UL,y)
+$(call force,CFG_TEE_CORE_NB_CORE,1)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
 $(call force,CFG_MX6ULL,y)
+$(call force,CFG_TEE_CORE_NB_CORE,1)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
 $(call force,CFG_MX6Q,y)
+$(call force,CFG_TEE_CORE_NB_CORE,4)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
 $(call force,CFG_MX6D,y)
+$(call force,CFG_TEE_CORE_NB_CORE,2)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
 $(call force,CFG_MX6DL,y)
+$(call force,CFG_TEE_CORE_NB_CORE,2)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
 $(call force,CFG_MX6S,y)
+$(call force,CFG_TEE_CORE_NB_CORE,1)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
 $(call force,CFG_MX6,y)
 $(call force,CFG_MX6SX,y)
-$(call force,CFG_IMX_UART,y)
-else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7-flavorlist)))
+$(call force,CFG_TEE_CORE_NB_CORE,1)
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
 $(call force,CFG_MX7,y)
-else
-$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
-endif
-
-ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
-CFG_DDR_SIZE ?= 0x40000000
-CFG_DT ?= y
-CFG_NS_ENTRY_ADDR ?= 0x80800000
-CFG_PSCI_ARM32 ?= y
 $(call force,CFG_TEE_CORE_NB_CORE,2)
-endif
-
-ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
-CFG_DDR_SIZE ?= 0x20000000
-CFG_DT ?= y
-CFG_NS_ENTRY_ADDR ?= 0x80800000
-CFG_PSCI_ARM32 ?= y
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
+$(call force,CFG_MX7,y)
 $(call force,CFG_TEE_CORE_NB_CORE,1)
+else
+$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
 endif
 
-# Common i.MX6 config
+# Generic IMX functionality
 $(call force,CFG_GENERIC_BOOT,y)
 $(call force,CFG_GIC,y)
 $(call force,CFG_IMX_UART,y)
 $(call force,CFG_PM_STUBS,y)
 $(call force,CFG_WITH_SOFTWARE_PRNG,y)
-
+$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
 CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
 CFG_WITH_STACK_CANARIES ?= y
 
@@ -62,18 +57,9 @@ CFG_WITH_STACK_CANARIES ?= y
 # i.MX6UL/ULL specific config
 ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL)))
 include core/arch/arm/cpu/cortex-a7.mk
-
 $(call force,CFG_MX6,y)
-$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
-
-CFG_DDR_TEETZ_RESERVED_START ?= 0x9E000000
-CFG_TZDRAM_START ?= $(CFG_DDR_TEETZ_RESERVED_START)
-CFG_TZDRAM_SIZE ?= 0x01E00000
-CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
-CFG_SHMEM_SIZE ?= 0x00200000
 endif
 
-
 # i.MX6 Solo/SoloX/DualLite/Dual/Quad specific config
 ifeq ($(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
       $(CFG_MX6SX)), y)
@@ -81,7 +67,6 @@ include core/arch/arm/cpu/cortex-a9.mk
 
 $(call force,CFG_MX6,y)
 $(call force,CFG_PL310,y)
-$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
 
 CFG_PL310_LOCKED ?= y
 CFG_BOOT_SYNC_CPU ?= y
@@ -89,44 +74,74 @@ CFG_BOOT_SECONDARY_REQUEST ?= y
 CFG_ENABLE_SCTLR_RR ?= y
 endif
 
-# i.MX6 Solo/DualLite/Dual/Quad specific config
-ifeq ($(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
-CFG_TZDRAM_START ?= 0x4E000000
-CFG_TZDRAM_SIZE ?= 0x01F00000
-CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
-CFG_SHMEM_SIZE ?= 0x00100000
-endif
-
-# i.MX6 SoloX specific config
-ifeq ($(filter y, $(CFG_MX6SX)), y)
-CFG_TZDRAM_START ?= (0x80000000 + $(CFG_DDR_SIZE) - 0x02000000)
-CFG_TZDRAM_SIZE ?= 0x01e00000
-CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
-CFG_SHMEM_SIZE ?= 0x00200000
-endif
-
+# i.MX7 specific config
 ifeq ($(filter y, $(CFG_MX7)), y)
 include core/arch/arm/cpu/cortex-a7.mk
 
-$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
 CFG_BOOT_SECONDARY_REQUEST ?= y
 CFG_INIT_CNTVOFF ?= y
+endif
+
+CFG_MMAP_REGIONS ?= 24
 
-CFG_TZDRAM_START ?= (0x80000000 + $(CFG_DDR_SIZE) - 0x02000000)
-CFG_TZDRAM_SIZE ?= 0x01e00000
-CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
+ta-targets = ta_arm32
+
+# Default Board configuration
+
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk))
+CFG_NS_ENTRY_ADDR ?= 0x80800000
+CFG_DT_ADDR ?= 0x83000000
+CFG_DDR_SIZE ?= 0x20000000
 CFG_SHMEM_SIZE ?= 0x00200000
 endif
 
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ullevk))
+CFG_NS_ENTRY_ADDR ?= 0x80800000
+CFG_DT_ADDR ?= 0x83000000
+CFG_DDR_SIZE ?= 0x20000000
+CFG_SHMEM_SIZE ?= 0x00200000
+endif
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite))
+CFG_NS_ENTRY_ADDR ?= 0x12000000
+CFG_DT_ADDR ?= 0x18000000
+CFG_DDR_SIZE ?= 0x40000000
+CFG_SHMEM_SIZE ?= 0x00100000
+endif
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabresd))
+CFG_NS_ENTRY_ADDR ?= 0x12000000
+CFG_DT_ADDR ?= 0x18000000
+CFG_DDR_SIZE ?= 0x40000000
+CFG_SHMEM_SIZE ?= 0x00100000
+endif
 ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
-CFG_PAGEABLE_ADDR ?= 0
+CFG_NS_ENTRY_ADDR ?= 0x80800000
+CFG_DT_ADDR ?= 0x83000000
 CFG_DDR_SIZE ?= 0x80000000
+CFG_SHMEM_SIZE ?= 0x00200000
 CFG_DT ?= y
-CFG_NS_ENTRY_ADDR ?= 0x80800000
 CFG_PSCI_ARM32 ?= y
 CFG_BOOT_SYNC_CPU = n
 CFG_BOOT_SECONDARY_REQUEST = n
-$(call force,CFG_TEE_CORE_NB_CORE,1)
+endif
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx6dlsabresd))
+CFG_NS_ENTRY_ADDR ?= 0x12000000
+CFG_DT_ADDR ?= 0x18000000
+CFG_DDR_SIZE ?= 0x40000000
+CFG_SHMEM_SIZE ?= 0x00100000
+endif
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
+CFG_NS_ENTRY_ADDR ?= 0x80800000
+CFG_DDR_SIZE ?= 0x40000000
+CFG_SHMEM_SIZE ?= 0x00200000
+CFG_DT ?= y
+CFG_PSCI_ARM32 ?= y
+endif
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
+CFG_NS_ENTRY_ADDR ?= 0x80800000
+CFG_DDR_SIZE ?= 0x20000000
+CFG_SHMEM_SIZE ?= 0x00200000
+CFG_DT ?= y
+CFG_PSCI_ARM32 ?= y
 endif
 
 ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
@@ -134,6 +149,3 @@ CFG_HWSUPP_MEM_PERM_WXN = n
 CFG_IMX_WDOG ?= y
 endif
 
-CFG_MMAP_REGIONS ?= 24
-
-ta-targets = ta_arm32
diff --git a/core/arch/arm/plat-imx/config/imx6qdlsolo.h b/core/arch/arm/plat-imx/config/imx6qdlsolo.h
new file mode 100644
index 00000000..3caf60f3
--- /dev/null
+++ b/core/arch/arm/plat-imx/config/imx6qdlsolo.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (c) 2016, Wind River Systems.
+ * All rights reserved.
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CONFIG_IMX6QDLSOLO_H
+#define CONFIG_IMX6QDLSOLO_H
+
+#ifndef CFG_UART_BASE
+/* Board specific console UART */
+#if defined(PLATFORM_FLAVOR_mx6qsabrelite)
+#define CFG_UART_BASE		UART2_BASE
+#endif
+#if defined(PLATFORM_FLAVOR_mx6qsabresd)
+#define CFG_UART_BASE		UART1_BASE
+#endif
+#if defined(PLATFORM_FLAVOR_mx6dlsabresd)
+#define CFG_UART_BASE		UART1_BASE
+#endif
+#endif
+
+#define DRAM0_BASE		0x10000000
+#define DRAM0_SIZE		CFG_DDR_SIZE
+
+#define CONSOLE_UART_BASE	(CFG_UART_BASE)
+
+/*
+ * PL310 TAG RAM Control Register
+ *
+ * bit[10:8]:1 - 2 cycle of write accesses latency
+ * bit[6:4]:1 - 2 cycle of read accesses latency
+ * bit[2:0]:1 - 2 cycle of setup latency
+ */
+#ifndef PL310_TAG_RAM_CTRL_INIT
+#define PL310_TAG_RAM_CTRL_INIT		0x00000111
+#endif
+
+/*
+ * PL310 DATA RAM Control Register
+ *
+ * bit[10:8]:2 - 3 cycle of write accesses latency
+ * bit[6:4]:2 - 3 cycle of read accesses latency
+ * bit[2:0]:2 - 3 cycle of setup latency
+ */
+#ifndef PL310_DATA_RAM_CTRL_INIT
+#define PL310_DATA_RAM_CTRL_INIT	0x00000222
+#endif
+
+/*
+ * PL310 Auxiliary Control Register
+ *
+ * I/Dcache prefetch enabled (bit29:28=2b11)
+ * NS can access interrupts (bit27=1)
+ * NS can lockown cache lines (bit26=1)
+ * Pseudo-random replacement policy (bit25=0)
+ * Force write allocated (default)
+ * Shared attribute internally ignored (bit22=1, bit13=0)
+ * Parity disabled (bit21=0)
+ * Event monitor disabled (bit20=0)
+ * Platform flavor specific way config (dual / quad):
+ * - 64kb way size (bit19:17=3b011)
+ * - 16-way associativity (bit16=1)
+ * Platform flavor specific way config (dual lite / solo):
+ * - 32kb way size (bit19:17=3b010)
+ * - no 16-way associativity (bit16=0)
+ * Store buffer device limitation enabled (bit11=1)
+ * Cacheable accesses have high prio (bit10=0)
+ * Full Line Zero (FLZ) disabled (bit0=0)
+ */
+#ifndef PL310_AUX_CTRL_INIT
+#if defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D)
+#define PL310_AUX_CTRL_INIT		0x3C470800
+#else
+#define PL310_AUX_CTRL_INIT		0x3C440800
+#endif
+#endif
+
+/*
+ * PL310 Prefetch Control Register
+ *
+ * Double linefill disabled (bit30=0)
+ * I/D prefetch enabled (bit29:28=2b11)
+ * Prefetch drop enabled (bit24=1)
+ * Incr double linefill disable (bit23=0)
+ * Prefetch offset = 7 (bit4:0)
+ */
+#define PL310_PREFETCH_CTRL_INIT	0x31000007
+
+/*
+ * PL310 Power Register
+ *
+ * Dynamic clock gating enabled
+ * Standby mode enabled
+ */
+#define PL310_POWER_CTRL_INIT		0x00000003
+
+/*
+ * SCU Invalidate Register
+ *
+ * Invalidate all registers
+ */
+#define SCU_INV_CTRL_INIT		0xFFFFFFFF
+
+/*
+ * SCU Access Register
+ * - both secure CPU access SCU
+ */
+#define SCU_SAC_CTRL_INIT		0x0000000F
+
+/*
+ * SCU NonSecure Access Register
+ * - both nonsec cpu access SCU, private and global timer
+ */
+#define SCU_NSAC_CTRL_INIT		0x00000FFF
+
+#endif
diff --git a/core/arch/arm/plat-imx/config/config_imx6sx.h b/core/arch/arm/plat-imx/config/imx6sx.h
index 5d0b8717..5089799f 100644
--- a/core/arch/arm/plat-imx/config/config_imx6sx.h
+++ b/core/arch/arm/plat-imx/config/imx6sx.h
@@ -53,9 +53,9 @@
  * Shared attribute internally ignored (bit22=1, bit13=0)
  * Parity disabled (bit21=0)
  * Event monitor disabled (bit20=0)
- * Platform fmavor specific way config (dual / quad):
+ * Platform flavor specific way config:
  * - 16kb way size (bit19:17=3b001)
- * - 16-way associciativity (bit16=1)
+ * - 16-way associativity (bit16=1)
  * Store buffer device limitation enabled (bit11=1)
  * Cacheable accesses have high prio (bit10=0)
  * Full Line Zero (FLZ) disabled (bit0=0)
diff --git a/core/arch/arm/plat-imx/config/imx6ul.h b/core/arch/arm/plat-imx/config/imx6ul.h
new file mode 100644
index 00000000..e2e40034
--- /dev/null
+++ b/core/arch/arm/plat-imx/config/imx6ul.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef CONFIG_IMX6UL_H
+#define ONFIG_IMX6UL_H
+
+#ifdef CFG_WITH_PAGER
+#error "Pager not supported for platform mx6ulevk"
+#endif
+#ifdef CFG_WITH_LPAE
+#error "i.MX 6UL/6ULL does not support LPAE"
+#endif
+
+#ifndef CFG_UART_BASE
+#define CFG_UART_BASE	(UART1_BASE)
+#endif
+
+#define DRAM0_BASE		0x80000000
+#define DRAM0_SIZE		CFG_DDR_SIZE
+
+#define CONSOLE_UART_BASE	(CFG_UART_BASE)
+#endif
diff --git a/core/arch/arm/plat-imx/config/config_imx7.h b/core/arch/arm/plat-imx/config/imx7.h
index 474cdee4..32d56613 100644
--- a/core/arch/arm/plat-imx/config/config_imx7.h
+++ b/core/arch/arm/plat-imx/config/imx7.h
@@ -1,19 +1,19 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * Peng Fan <peng.fan@nxp.com>
  */
+#ifndef __CONFIG_IMX7_H
+#define __CONFIG_IMX7_H
 
 #ifndef CFG_UART_BASE
 #define CFG_UART_BASE	(UART1_BASE)
 #endif
 
-#ifndef CFG_DDR_SIZE
-#error "CFG_DDR_SIZE not defined"
-#endif
-
 #define DRAM0_BASE		0x80000000
 #define DRAM0_SIZE		CFG_DDR_SIZE
 
 #define CONSOLE_UART_BASE	(CFG_UART_BASE)
+
+#endif
diff --git a/core/arch/arm/plat-imx/platform_config.h b/core/arch/arm/plat-imx/platform_config.h
index a028af43..91760409 100644
--- a/core/arch/arm/plat-imx/platform_config.h
+++ b/core/arch/arm/plat-imx/platform_config.h
@@ -3,6 +3,7 @@
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  * Copyright (c) 2016, Wind River Systems.
  * All rights reserved.
+ * Copyright 2018 NXP
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -30,165 +31,51 @@
 #ifndef PLATFORM_CONFIG_H
 #define PLATFORM_CONFIG_H
 
-#include <mm/generic_ram_layout.h>
 #include <imx-regs.h>
 
 #define STACK_ALIGNMENT			64
 
-/* For i.MX7D/S platforms */
-#if defined(CFG_MX7)
-#include <config/config_imx7.h>
+#ifndef CFG_DDR_SIZE
+#error "CFG_DDR_SIZE not defined"
+#endif
 
+#if defined(CFG_MX7)
+/* For i.MX7D/S platforms */
+#include <config/imx7.h>
 #elif defined(CFG_MX6SX)
-#include <config/config_imx6sx.h>
-
-/* For i.MX 6UltraLite and 6ULL EVK board */
+#include <config/imx6sx.h>
 #elif defined(CFG_MX6UL) || defined(CFG_MX6ULL)
-
-#ifdef CFG_WITH_PAGER
-#error "Pager not supported for platform mx6ulevk"
-#endif
-#ifdef CFG_WITH_LPAE
-#error "LPAE not supported for now"
-#endif
-
-#define CFG_TEE_CORE_NB_CORE		1
-
-#define CONSOLE_UART_BASE	(UART1_BASE)
-
+/* For i.MX 6UltraLite and 6ULL EVK board */
+#include <config/imx6ul.h>
+#elif defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D) || \
+	defined(CFG_MX6DL) || defined(CFG_MX6S)
 /* For i.MX6 Quad SABRE Lite and Smart Device board */
-
-#elif defined(CFG_MX6Q) || defined(CFG_MX6D) || defined(CFG_MX6DL) || \
-	defined(CFG_MX6S)
-
-
-/* Board specific console UART */
-#if defined(PLATFORM_FLAVOR_mx6qsabrelite)
-#define CONSOLE_UART_BASE		UART2_BASE
-#endif
-#if defined(PLATFORM_FLAVOR_mx6qsabresd)
-#define CONSOLE_UART_BASE		UART1_BASE
-#endif
-#if defined(PLATFORM_FLAVOR_mx6dlsabresd)
-#define CONSOLE_UART_BASE		UART1_BASE
+#include <config/imx6qdlsolo.h>
+#else
+#error "Unknown platform flavor"
 #endif
 
-/* Board specific RAM size */
-#if defined(PLATFORM_FLAVOR_mx6qsabrelite) || \
-	defined(PLATFORM_FLAVOR_mx6qsabresd) || \
-	defined(PLATFORM_FLAVOR_mx6dlsabresd)
-#define DRAM0_SIZE			0x40000000
-#endif
 
-/* Core number depends of SoC version. */
-#if defined(CFG_MX6Q)
-#define CFG_TEE_CORE_NB_CORE		4
+#ifndef CFG_TEE_RESERVED_SIZE
+#define CFG_TEE_RESERVED_SIZE 0x02000000
 #endif
-#if defined(CFG_MX6D) || defined(CFG_MX6DL)
-#define CFG_TEE_CORE_NB_CORE		2
-#endif
-#if defined(CFG_MX6S)
-#define CFG_TEE_CORE_NB_CORE		1
-#endif
-
-/* Common RAM and cache controller configuration */
-#define DDR_PHYS_START			DRAM0_BASE
-#define DDR_SIZE			DRAM0_SIZE
-
-#define CFG_DDR_START			DDR_PHYS_START
-#define CFG_DDR_SIZE			DDR_SIZE
 
-/*
- * PL310 TAG RAM Control Register
- *
- * bit[10:8]:1 - 2 cycle of write accesses latency
- * bit[6:4]:1 - 2 cycle of read accesses latency
- * bit[2:0]:1 - 2 cycle of setup latency
- */
-#ifndef PL310_TAG_RAM_CTRL_INIT
-#define PL310_TAG_RAM_CTRL_INIT		0x00000111
+#ifndef CFG_TZDRAM_START
+#define  CFG_TZDRAM_START (DRAM0_BASE + CFG_DDR_SIZE - CFG_TEE_RESERVED_SIZE)
 #endif
 
-/*
- * PL310 DATA RAM Control Register
- *
- * bit[10:8]:2 - 3 cycle of write accesses latency
- * bit[6:4]:2 - 3 cycle of read accesses latency
- * bit[2:0]:2 - 3 cycle of setup latency
- */
-#ifndef PL310_DATA_RAM_CTRL_INIT
-#define PL310_DATA_RAM_CTRL_INIT	0x00000222
+#ifndef CFG_SHMEM_SIZE
+#define  CFG_SHMEM_SIZE 0x100000
 #endif
 
-/*
- * PL310 Auxiliary Control Register
- *
- * I/Dcache prefetch enabled (bit29:28=2b11)
- * NS can access interrupts (bit27=1)
- * NS can lockown cache lines (bit26=1)
- * Pseudo-random replacement policy (bit25=0)
- * Force write allocated (default)
- * Shared attribute internally ignored (bit22=1, bit13=0)
- * Parity disabled (bit21=0)
- * Event monitor disabled (bit20=0)
- * Platform fmavor specific way config (dual / quad):
- * - 64kb way size (bit19:17=3b011)
- * - 16-way associciativity (bit16=1)
- * Platform fmavor specific way config (dual lite / solo):
- * - 32kb way size (bit19:17=3b010)
- * - no 16-way associciativity (bit16=0)
- * Store buffer device limitation enabled (bit11=1)
- * Cacheable accesses have high prio (bit10=0)
- * Full Line Zero (FLZ) disabled (bit0=0)
- */
-#ifndef PL310_AUX_CTRL_INIT
-#if defined(CFG_MX6Q) || defined(CFG_MX6D)
-#define PL310_AUX_CTRL_INIT		0x3C470800
-#else
-#define PL310_AUX_CTRL_INIT		0x3C440800
-#endif
+#ifndef CFG_TZDRAM_SIZE
+#define  CFG_TZDRAM_SIZE  (CFG_TEE_RESERVED_SIZE - CFG_SHMEM_SIZE)
 #endif
 
-/*
- * PL310 Prefetch Control Register
- *
- * Double linefill disabled (bit30=0)
- * I/D prefetch enabled (bit29:28=2b11)
- * Prefetch drop enabled (bit24=1)
- * Incr double linefill disable (bit23=0)
- * Prefetch offset = 7 (bit4:0)
- */
-#define PL310_PREFETCH_CTRL_INIT	0x31000007
-
-/*
- * PL310 Power Register
- *
- * Dynamic clock gating enabled
- * Standby mode enabled
- */
-#define PL310_POWER_CTRL_INIT		0x00000003
-
-/*
- * SCU Invalidate Register
- *
- * Invalidate all registers
- */
-#define	SCU_INV_CTRL_INIT		0xFFFFFFFF
-
-/*
- * SCU Access Register
- * - both secure CPU access SCU
- */
-#define SCU_SAC_CTRL_INIT		0x0000000F
-
-/*
- * SCU NonSecure Access Register
- * - both nonsec cpu access SCU, private and global timer
- */
-#define SCU_NSAC_CTRL_INIT		0x00000FFF
-
-#else
-#error "Unknown platform flavor"
+#ifndef CFG_SHMEM_START
+#define  CFG_SHMEM_START (CFG_TZDRAM_START + CFG_TZDRAM_SIZE)
 #endif
 
+#include <mm/generic_ram_layout.h>
+
 #endif /*PLATFORM_CONFIG_H*/