diff options
| author | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-07-20 19:31:06 +0200 |
|---|---|---|
| committer | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-08-02 15:37:22 +0200 |
| commit | 257731364691ffc57c1856b13e902eac29064c01 (patch) | |
| tree | 2e9ae412c95fd7a03e103f1d96d00e0090ebb68a /core | |
| parent | 523126884b9bcc0430854aaf1e447b56fe2f4801 (diff) | |
soc definition update
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/arch/arm/plat-imx/imx-common.c | 63 | ||||
| -rw-r--r-- | core/arch/arm/plat-imx/imx.h | 2 |
2 files changed, 46 insertions, 19 deletions
diff --git a/core/arch/arm/plat-imx/imx-common.c b/core/arch/arm/plat-imx/imx-common.c index 2f67247a..6ea7ebbb 100644 --- a/core/arch/arm/plat-imx/imx-common.c +++ b/core/arch/arm/plat-imx/imx-common.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-2-Clause /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * * Peng Fan <peng.fan@nxp.com> */ @@ -13,35 +13,53 @@ #include <mm/core_memprot.h> #include <platform_config.h> -static uint32_t imx_digproc(void) -{ - static uint32_t reg; - vaddr_t anatop_addr; +static int imx_cpu_type = (-1); +static int imx_soc_revision = (-1); - if (!reg) { - anatop_addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC); +static void imx_digproc(void) +{ + uint32_t digprog; + vaddr_t anatop_addr __maybe_unused; +#ifdef CFG_MX7ULP +/* Temporary Hack to unify detection of SoC*/ + digprog = SOC_MX7ULP << 16; +#else + anatop_addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC); - /* TODO: Handle SL here */ -#if defined CFG_MX7 - reg = read32(anatop_addr + HW_ANADIG_DIGPROG_IMX7D); -#elif defined CFG_MX6SL - reg = read32(anatop_addr + HW_ANADIG_DIGPROG_IMX6SL); +#ifdef CFG_MX7 + digprog = read32(anatop_addr + HW_ANADIG_DIGPROG_IMX7D); +#elif defined(CFG_MX6SL) + digprog = read32(anatop_addr + HW_ANADIG_DIGPROG_IMX6SL); #else - reg = read32(anatop_addr + HW_ANADIG_DIGPROG); + digprog = read32(anatop_addr + HW_ANADIG_DIGPROG); #endif - } - return reg; +#endif + /* Set the CPU type */ + imx_cpu_type = ((digprog >> 16) & 0xFF); + + /* Set the SOC revision = (Major + 1).(Minor) */ + imx_soc_revision = (((digprog & 0xFF00) >> 4) + 0x10) | + (digprog & 0x0F); + } static uint32_t imx_soc_rev_major(void) { - return ((imx_digproc() & 0xff00) >> 8) + 1; + if (imx_soc_revision < 0) { + imx_digproc(); + } + + return (imx_soc_revision >> 4); } static uint32_t imx_soc_type(void) { - return (imx_digproc() >> 16) & 0xff; + if (imx_cpu_type < 0) { + imx_digproc(); + } + + return imx_cpu_type; } bool soc_is_imx6sll(void) @@ -76,12 +94,14 @@ bool soc_is_imx6sdl(void) bool soc_is_imx6dq(void) { - return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 1); + return (imx_soc_type() == SOC_MX6Q) && + (imx_soc_rev_major() == 1); } bool soc_is_imx6dqp(void) { - return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 2); + return (imx_soc_type() == SOC_MX6Q) && + (imx_soc_rev_major() == 2); } bool soc_is_imx6(void) @@ -100,6 +120,11 @@ bool soc_is_imx7ds(void) return imx_soc_type() == SOC_MX7D; } +bool soc_is_imx7ulp(void) +{ + return imx_soc_type() == SOC_MX7ULP; +} + uint32_t imx_get_src_gpr(int cpu) { vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC); diff --git a/core/arch/arm/plat-imx/imx.h b/core/arch/arm/plat-imx/imx.h index 60081363..5ec90115 100644 --- a/core/arch/arm/plat-imx/imx.h +++ b/core/arch/arm/plat-imx/imx.h @@ -20,6 +20,7 @@ #define SOC_MX6SLL 0x67 #define SOC_MX6D 0x6A #define SOC_MX7D 0x72 +#define SOC_MX7ULP 0xE1 /* Temporally hard code */ uint32_t imx_get_src_gpr(int cpu); void imx_set_src_gpr(int cpu, uint32_t val); @@ -34,6 +35,7 @@ bool soc_is_imx6sdl(void); bool soc_is_imx6dq(void); bool soc_is_imx6dqp(void); bool soc_is_imx7ds(void); +bool soc_is_imx7ulp(void); void imx_gpcv2_set_core1_pdn_by_software(void); void imx_gpcv2_set_core1_pup_by_software(void); #ifdef CFG_TZC380 |