core: arm: imx: Add imx8mq evk board support

Add support for i.MX 8mscale (AARCH64)

Signed-off-by: Peng Fan <peng.fan@nxp.com>

7 files changed, 141 insertions, 6 deletions

diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index 9a2613dd..6e029bd6 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -14,6 +14,7 @@ mx6ull-flavorlist = mx6ullevk
 mx7d-flavorlist = mx7dsabresd
 mx7s-flavorlist = mx7swarp7
 mx7ulp-flavorlist = mx7ulpevk
+mx8m-flavorlist = mx8mqevk
 
 ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
 $(call force,CFG_MX6,y)
@@ -71,18 +72,43 @@ $(call force,CFG_MX7ULP,y)
 $(call force,CFG_TEE_CORE_NB_CORE,1)
 $(call force,CFG_TZC380,n)
 $(call force,CFG_CSU,n)
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8m-flavorlist)))
+$(call force,CFG_MX8M,y)
+$(call force,CFG_ARM64_core,y)
+$(call force,CFG_TEE_CORE_NB_CORE,4)
 else
 $(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
 endif
 
 # Generic IMX functionality
 $(call force,CFG_GENERIC_BOOT,y)
-$(call force,CFG_GIC,y)
 $(call force,CFG_PM_STUBS,y)
+$(call force,CFG_GIC,y)
 $(call force,CFG_WITH_SOFTWARE_PRNG,y)
-$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
 CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
 CFG_WITH_STACK_CANARIES ?= y
+CFG_MMAP_REGIONS ?= 24
+
+ifeq ($(CFG_ARM64_core),y)
+# arm-v8 platforms
+include core/arch/arm/cpu/cortex-armv8-0.mk
+$(call force,CFG_WITH_LPAE,y)
+$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
+$(call force,CFG_ARM_GICV3,y)
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+ta-targets = ta_arm64
+CFG_CRYPTO_WITH_CE ?= y
+
+CFG_IMX_WDOG = n
+CFG_TZC380 ?= y
+CFG_IMX_UART ?= y
+else
+# arm-v7 platforms Common definition
+ta-targets = ta_arm32
+
+$(call force,CFG_SECURE_TIME_SOURCE_REE,y)
+CFG_TZC380 ?= y
+CFG_CSU ?= y
 
 # i.MX6UL/ULL specific config
 ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL)))
@@ -135,9 +161,8 @@ CFG_IMX_CAAM ?= y
 $(call force,CFG_IMX_UART,n)
 endif
 
-CFG_MMAP_REGIONS ?= 24
-
 ta-targets = ta_arm32
+endif
 
 # Default Board configuration
 ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk))
@@ -329,6 +354,10 @@ CFG_BOOT_SYNC_CPU = n
 CFG_BOOT_SECONDARY_REQUEST = n
 endif
 
+ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
+CFG_DDR_SIZE ?= 0xC0000000
+endif
+
 ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
 CFG_HWSUPP_MEM_PERM_WXN = n
 CFG_IMX_WDOG ?= y
diff --git a/core/arch/arm/plat-imx/config/imx8m.h b/core/arch/arm/plat-imx/config/imx8m.h
new file mode 100644
index 00000000..fa660620
--- /dev/null
+++ b/core/arch/arm/plat-imx/config/imx8m.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#ifndef CONFIG_IMX8M_H
+#define CONFIG_IMX8M_H
+
+#ifndef CFG_UART_BASE
+#define CFG_UART_BASE	(UART1_BASE)
+#endif
+
+#define DRAM0_BASE		0x40000000
+#define DRAM0_SIZE		CFG_DDR_SIZE
+
+#define CONSOLE_UART_BASE	(CFG_UART_BASE)
+#endif
diff --git a/core/arch/arm/plat-imx/main.c b/core/arch/arm/plat-imx/main.c
index 740bdb8d..cec9342e 100644
--- a/core/arch/arm/plat-imx/main.c
+++ b/core/arch/arm/plat-imx/main.c
@@ -36,12 +36,21 @@ static const struct thread_handlers handlers = {
 	.std_smc = tee_entry_std,
 	.fast_smc = tee_entry_fast,
 	.nintr = main_fiq,
+#if defined(CFG_WITH_ARM_TRUSTED_FW)
+	.cpu_on = cpu_on_handler,
+	.cpu_off = pm_do_nothing,
+	.cpu_suspend = pm_do_nothing,
+	.cpu_resume = pm_do_nothing,
+	.system_off = pm_do_nothing,
+	.system_reset = pm_do_nothing,
+#else
 	.cpu_on = pm_panic,
 	.cpu_off = pm_panic,
 	.cpu_suspend = pm_panic,
 	.cpu_resume = pm_panic,
 	.system_off = pm_panic,
 	.system_reset = pm_panic,
+#endif
 };
 
 #ifdef CFG_IMX_LPUART
@@ -62,6 +71,9 @@ register_phys_mem(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_DEVICE_SIZE);
 #ifdef GICD_BASE
 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, 0x10000);
 #endif
+#ifdef GICR_BASE
+register_phys_mem(MEM_AREA_IO_SEC, GICR_BASE, 0xC0000);
+#endif
 #ifdef AIPS0_BASE
 register_phys_mem(MEM_AREA_IO_SEC, AIPS0_BASE,
 		  ROUNDUP(AIPS0_SIZE, CORE_MMU_DEVICE_SIZE));
@@ -120,6 +132,18 @@ void console_init(void)
 
 void main_init_gic(void)
 {
+#ifdef CFG_ARM_GICV3
+	vaddr_t gicd_base;
+
+	gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC);
+
+	if (!gicd_base)
+		panic();
+
+	/* Initialize GIC */
+	gic_init(&gic_data, 0, gicd_base);
+	itr_init(&gic_data.chip);
+#else
 	vaddr_t gicc_base;
 	vaddr_t gicd_base;
 
@@ -132,10 +156,11 @@ void main_init_gic(void)
 	/* Initialize GIC */
 	gic_init(&gic_data, gicc_base, gicd_base);
 	itr_init(&gic_data.chip);
+#endif
 }
 
 #if defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D) || \
-	defined(CFG_MX6DL) || defined(CFG_MX7)
+	defined(CFG_MX6DL) || defined(CFG_MX7) || defined(CFG_MX8M)
 void main_secondary_init_gic(void)
 {
 	gic_cpu_init(&gic_data);
diff --git a/core/arch/arm/plat-imx/platform_config.h b/core/arch/arm/plat-imx/platform_config.h
index a14fedcb..b8890cf3 100644
--- a/core/arch/arm/plat-imx/platform_config.h
+++ b/core/arch/arm/plat-imx/platform_config.h
@@ -35,12 +35,16 @@
 
 #define STACK_ALIGNMENT			64
 
+
 #ifndef CFG_DDR_SIZE
 #error "CFG_DDR_SIZE not defined"
 #endif
 
-#if defined(CFG_MX7)
+/* For i.MX8M platforms */
+#if defined(CFG_MX8M)
+#include <config/imx8m.h>
 /* For i.MX7D/S platforms */
+#elif defined(CFG_MX7)
 #include <config/imx7.h>
 /* For i.MX7ULP platforms */
 #elif defined(CFG_MX7ULP)
diff --git a/core/arch/arm/plat-imx/registers/imx-regs.h b/core/arch/arm/plat-imx/registers/imx-regs.h
index 7755d746..c66a7f74 100644
--- a/core/arch/arm/plat-imx/registers/imx-regs.h
+++ b/core/arch/arm/plat-imx/registers/imx-regs.h
@@ -37,6 +37,8 @@
 #include <registers/imx7-regs.h>
 #elif defined(CFG_MX7ULP)
 #include <registers/imx7ulp-regs.h>
+#elif defined(CFG_MX8M)
+#include <registers/imx8m-regs.h>
 #else
 #error "PLATFORM not defined"
 #endif
diff --git a/core/arch/arm/plat-imx/registers/imx8m-regs.h b/core/arch/arm/plat-imx/registers/imx8m-regs.h
new file mode 100644
index 00000000..a62efacf
--- /dev/null
+++ b/core/arch/arm/plat-imx/registers/imx8m-regs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017 NXP
+ *
+ */
+
+#ifndef __IMX8_REGS_H__
+#define __IMX8_REGS_H__
+
+#define GICD_BASE	0x38800000
+#define GICR_BASE	0x38880000
+#define UART1_BASE	0x30860000
+#define UART2_BASE	0x30890000
+#define UART3_BASE	0x30880000
+#define UART4_BASE	0x30A60000
+#define TZASC_BASE	0x32F80000
+#define CAAM_BASE	0x30900000
+
+#endif /* __IMX8_REGS_H__ */
diff --git a/core/arch/arm/plat-imx/tzasc.c b/core/arch/arm/plat-imx/tzasc.c
index fa2171b8..fb176798 100644
--- a/core/arch/arm/plat-imx/tzasc.c
+++ b/core/arch/arm/plat-imx/tzasc.c
@@ -295,6 +295,31 @@ static int board_imx_tzasc_configure(vaddr_t addr)
 
 	return 0;
 }
+#elif defined(PLATFORM_FLAVOR_mx8mqevk)
+static int board_imx_tzasc_configure(vaddr_t addr)
+{
+	tzc_init(addr);
+
+	tzc_configure_region(0, 0x00000000,
+		TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
+		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
+	tzc_configure_region(1, 0xbe000000,
+		TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) |
+		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW);
+	tzc_configure_region(2, 0xbfe00000,
+		TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_2M) |
+		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
+
+	tzc_set_action(3);
+
+	tzc_region_enable(2);
+	tzc_region_enable(1);
+	tzc_region_enable(0);
+
+	tzc_dump_state();
+
+	return 0;
+}
 #else
 #error "No tzasc defined"
 #endif
@@ -423,6 +448,19 @@ TEE_Result tzasc_init(void)
 
 	return TEE_SUCCESS;
 }
+#elif defined(CFG_MX8M)
+register_phys_mem(MEM_AREA_IO_SEC, TZASC_BASE, CORE_MMU_DEVICE_SIZE);
+TEE_Result tzasc_init(void)
+{
+	vaddr_t addr;
+
+	addr = core_mmu_get_va(TZASC_BASE, MEM_AREA_IO_SEC);
+
+	board_imx_tzasc_configure(addr);
+
+	return TEE_SUCCESS;
+}
+driver_init(tzasc_init);
 #else
 #error "CFG_MX6/7 not defined"
 #endif