TEE-243 core: arm: imx: Add CSU module

Centralize CSU settings in one file

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

9 files changed, 111 insertions, 122 deletions

diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index aa63fe77..d1f81a63 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -30,7 +30,6 @@ else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
 $(call force,CFG_MX6S,y)
 $(call force,CFG_TEE_CORE_NB_CORE,1)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
-$(call force,CFG_MX6,y)
 $(call force,CFG_MX6SX,y)
 $(call force,CFG_TEE_CORE_NB_CORE,1)
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
@@ -50,6 +49,7 @@ $(call force,CFG_IMX_UART,y)
 $(call force,CFG_PM_STUBS,y)
 $(call force,CFG_WITH_SOFTWARE_PRNG,y)
 $(call force,CFG_SECURE_TIME_SOURCE_REE,y)
+CFG_CSU ?= y
 CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
 CFG_WITH_STACK_CANARIES ?= y
 
diff --git a/core/arch/arm/plat-imx/config/imx6sx.h b/core/arch/arm/plat-imx/config/imx6sx.h
index 5089799f..8d170e90 100644
--- a/core/arch/arm/plat-imx/config/imx6sx.h
+++ b/core/arch/arm/plat-imx/config/imx6sx.h
@@ -12,10 +12,7 @@
 #define CFG_UART_BASE	(UART1_BASE)
 #endif
 
-#ifndef CFG_DDR_SIZE
-#error "CFG_DDR_SIZE not defined"
-#endif
-
+#define DRAM0_BASE		0x80000000
 #define DRAM0_SIZE		CFG_DDR_SIZE
 
 #define CONSOLE_UART_BASE	(CFG_UART_BASE)
diff --git a/core/arch/arm/plat-imx/imx.h b/core/arch/arm/plat-imx/imx.h
index 466c76b8..4aacc246 100644
--- a/core/arch/arm/plat-imx/imx.h
+++ b/core/arch/arm/plat-imx/imx.h
@@ -9,6 +9,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include <tee_api_types.h>
 
 #define SOC_MX6SL	0x60
 #define SOC_MX6DL	0x61
@@ -35,4 +36,7 @@ bool soc_is_imx6dqp(void);
 bool soc_is_imx7ds(void);
 void imx_gpcv2_set_core1_pdn_by_software(void);
 void imx_gpcv2_set_core1_pup_by_software(void);
+#ifdef CFG_CSU
+TEE_Result csu_init(void);
+#endif
 #endif
diff --git a/core/arch/arm/plat-imx/imx6.c b/core/arch/arm/plat-imx/imx6.c
index dbec5635..962c1828 100644
--- a/core/arch/arm/plat-imx/imx6.c
+++ b/core/arch/arm/plat-imx/imx6.c
@@ -3,36 +3,13 @@
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  * Copyright (c) 2016, Wind River Systems.
  * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Copyright 2018 NXP
  */
-
-#include <compiler.h>
-#include <drivers/gic.h>
+#include <imx.h>
 #include <io.h>
+#include <kernel/tz_ssvce_pl310.h>
 #include <kernel/generic_boot.h>
 #include <kernel/misc.h>
-#include <kernel/tz_ssvce_pl310.h>
 #include <mm/core_memprot.h>
 #include <mm/core_mmu.h>
 #include <platform_config.h>
@@ -41,7 +18,6 @@ register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, CORE_MMU_DEVICE_SIZE);
 
 void plat_cpu_reset_late(void)
 {
-	uintptr_t addr;
 	uint32_t pa __maybe_unused;
 
 	if (!get_core_pos()) {
@@ -65,18 +41,9 @@ void plat_cpu_reset_late(void)
 		write32(read32(SCU_BASE + SCU_CTRL) | 0x1,
 			SCU_BASE + SCU_CTRL);
 
+#ifdef CFG_CSU
 		/* configure imx6 CSU */
-
-		/* first grant all peripherals */
-		for (addr = CSU_BASE + CSU_CSL_START;
-			 addr != CSU_BASE + CSU_CSL_END;
-			 addr += 4)
-			write32(CSU_ACCESS_ALL, addr);
-
-		/* lock the settings */
-		for (addr = CSU_BASE + CSU_CSL_START;
-			 addr != CSU_BASE + CSU_CSL_END;
-			 addr += 4)
-			write32(read32(addr) | CSU_SETTING_LOCK, addr);
+		csu_init();
+#endif
 	}
 }
diff --git a/core/arch/arm/plat-imx/imx6ul.c b/core/arch/arm/plat-imx/imx6ul.c
index 758f748c..0a2c207e 100644
--- a/core/arch/arm/plat-imx/imx6ul.c
+++ b/core/arch/arm/plat-imx/imx6ul.c
@@ -1,35 +1,19 @@
 // SPDX-License-Identifier: BSD-2-Clause
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
+ * Copyright 2018 NXP
  * Peng Fan <peng.fan@nxp.com>
  */
 
-#include <arm32.h>
-#include <io.h>
+#include <imx.h>
 #include <kernel/generic_boot.h>
 #include <platform_config.h>
-#include <stdint.h>
 
-static void init_csu(void)
-{
-	uintptr_t addr;
-
-	/* first grant all peripherals */
-	for (addr = CSU_BASE + CSU_CSL_START;
-	     addr != CSU_BASE + CSU_CSL_END;
-	     addr += 4)
-		write32(CSU_ACCESS_ALL, addr);
-
-	/* lock the settings */
-	for (addr = CSU_BASE + CSU_CSL_START;
-	     addr != CSU_BASE + CSU_CSL_END;
-	     addr += 4)
-		write32(read32(addr) | CSU_SETTING_LOCK, addr);
-}
 
 /* MMU not enabled now */
 void plat_cpu_reset_late(void)
 {
-	init_csu();
+#ifdef CFG_CSU
+	csu_init();
+#endif
 }
diff --git a/core/arch/arm/plat-imx/imx7.c b/core/arch/arm/plat-imx/imx7.c
index 2fcaea61..6f6f0c10 100644
--- a/core/arch/arm/plat-imx/imx7.c
+++ b/core/arch/arm/plat-imx/imx7.c
@@ -1,66 +1,20 @@
 // SPDX-License-Identifier: BSD-2-Clause
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * Peng Fan <peng.fan@nxp.com>
  */
-
-#include <arm32.h>
-#include <console.h>
-#include <drivers/imx_uart.h>
-#include <drivers/tzc380.h>
-#include <io.h>
+#include <imx.h>
 #include <kernel/generic_boot.h>
-#include <kernel/panic.h>
 #include <kernel/misc.h>
-#include <kernel/pm_stubs.h>
-#include <mm/core_mmu.h>
-#include <mm/core_memprot.h>
 #include <platform_config.h>
-#include <imx.h>
-#include <stdint.h>
-#include <sm/optee_smc.h>
-#include <sm/psci.h>
-#include <tee/entry_std.h>
-#include <tee/entry_fast.h>
-#include <util.h>
 
 void plat_cpu_reset_late(void)
 {
-	uintptr_t addr;
-	uint32_t val;
-
 	if (get_core_pos() != 0)
 		return;
 
-	/*
-	 * Configure imx7 CSU, first grant all peripherals
-	 * TODO: fine tune the permissions
-	 */
-	for (addr = CSU_CSL_START; addr != CSU_CSL_END; addr += 4)
-		write32(CSU_ACCESS_ALL, core_mmu_get_va(addr, MEM_AREA_IO_SEC));
-
-	dsb();
-	/* Protect OCRAM_S */
-	write32(0x003300FF, core_mmu_get_va(CSU_CSL_59, MEM_AREA_IO_SEC));
-	/* Proect TZASC */
-	write32(0x00FF0033, core_mmu_get_va(CSU_CSL_28, MEM_AREA_IO_SEC));
-	/*
-	 * Proect CSU
-	 * Note: Ater this settings, CSU seems still can be read,
-	 * in non-secure world but can not be written.
-	 */
-	write32(0x00FF0033, core_mmu_get_va(CSU_CSL_15, MEM_AREA_IO_SEC));
-	/*
-	 * Protect SRC
-	 * write32(0x003300FF, core_mmu_get_va(CSU_CSL_12, MEM_AREA_IO_SEC));
-	 */
-	dsb();
-
-	/* lock the settings */
-	for (addr = CSU_CSL_START; addr != CSU_CSL_END; addr += 4) {
-		val = read32(core_mmu_get_va(addr, MEM_AREA_IO_SEC));
-		write32(val | CSU_SETTING_LOCK,
-			core_mmu_get_va(addr, MEM_AREA_IO_SEC));
-	}
+#ifdef CFG_CSU
+	csu_init();
+#endif
 }
diff --git a/core/arch/arm/plat-imx/imx_csu.c b/core/arch/arm/plat-imx/imx_csu.c
new file mode 100644
index 00000000..963183e8
--- /dev/null
+++ b/core/arch/arm/plat-imx/imx_csu.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#include <mm/core_memprot.h>
+#include <io.h>
+
+#include <imx.h>
+
+struct csu_setting {
+	int      csu_index;
+	uint32_t value;
+};
+
+const struct csu_setting csu_setting_imx6[] = {
+	{13, 0xFF0033},		/* Protect ROMCP */
+	{14, 0x3F00FF},		/* Protect OCOTP */
+	{16, 0x330033},		/* Protect TZASC */
+	{26, 0xFF0033},		/* Protect OCRAM */
+	{(-1), 0},
+};
+
+const struct csu_setting csu_setting_imx6ul[] = {
+	{13, 0xFF0033},		/* Protect ROMCP */
+	{14, 0x3F00FF},		/* Protect OCOTP */
+	{16, 0x3300FF},		/* Protect TZASC */
+	{(-1), 0},
+};
+
+const struct csu_setting csu_setting_imx6sx[] = {
+	{13, 0xFF0033},		/* Protect ROMCP */
+	{14, 0x3F00FF},		/* Protect OCOTP */
+	{15, 0xFF0033},		/* Protect RDC   */
+	{16, 0x3300FF},		/* Protect TZASC */
+	{(-1), 0},
+};
+
+const struct csu_setting csu_setting_imx7ds[] = {
+	{14, 0x3300FF},		/* Protect RDC     */
+	{15, 0xFF0033},		/* Protect CSU     */
+	{28, 0xFF0033},		/* Protect TZASC   */
+	{59, 0xFF0033},		/* Protect OCRAM_S */
+	{(-1), 0},
+};
+
+TEE_Result csu_init(void)
+{
+	vaddr_t csu_base = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC);
+	vaddr_t offset;
+	const struct csu_setting *csu_setting = NULL;
+
+	if (soc_is_imx6sx()) {
+		csu_setting = csu_setting_imx6sx;
+	} else if (soc_is_imx6ul() || soc_is_imx6ull()) {
+		csu_setting = csu_setting_imx6ul;
+	} else if (soc_is_imx6()) {
+		csu_setting = csu_setting_imx6;
+	} else if (soc_is_imx7ds()) {
+		csu_setting = csu_setting_imx7ds;
+	} else {
+		return TEE_SUCCESS;
+	}
+
+	/* configure imx6 CSU */
+	/* first grant all peripherals */
+	for (offset = CSU_CSL_START; offset < CSU_CSL_END; offset += 4) {
+		write32(CSU_ACCESS_ALL, csu_base + offset);
+	}
+
+	while (csu_setting->csu_index > 0) {
+		write32(csu_setting->value,
+				csu_base + (csu_setting->csu_index * 4));
+
+		csu_setting++;
+	}
+
+	/* lock the settings */
+	for (offset = CSU_CSL_START; offset < CSU_CSL_END; offset += 4) {
+		write32(read32(csu_base + offset) | CSU_SETTING_LOCK,
+				csu_base + offset);
+	}
+
+	return TEE_SUCCESS;
+}
+
diff --git a/core/arch/arm/plat-imx/registers/imx7-regs.h b/core/arch/arm/plat-imx/registers/imx7-regs.h
index 7ed4a986..2a9e2031 100644
--- a/core/arch/arm/plat-imx/registers/imx7-regs.h
+++ b/core/arch/arm/plat-imx/registers/imx7-regs.h
@@ -38,12 +38,6 @@
 #define CSU_ACCESS_ALL		0x00FF00FF
 #define CSU_SETTING_LOCK	0x01000100
 
-
-#define CSU_CSL_59		(0x303E0000 + 59 * 4)
-#define CSU_CSL_28		(0x303E0000 + 28 * 4)
-#define CSU_CSL_15		(0x303E0000 + 15 * 4)
-#define CSU_CSL_12		(0x303E0000 + 12 * 4)
-
 #define TRUSTZONE_OCRAM_START	0x180000
 
 #endif /* __IMX7_REGS_H__ */
diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk
index 16818e7e..41b64563 100644
--- a/core/arch/arm/plat-imx/sub.mk
+++ b/core/arch/arm/plat-imx/sub.mk
@@ -24,3 +24,5 @@ endif
 srcs-$(CFG_MX7) += imx7.c a7_plat_init.S
 
 subdirs-$(CFG_PSCI_ARM32) += pm
+srcs-$(CFG_CSU) += imx_csu.c
+