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| author | Peng Fan <peng.fan@nxp.com> | 2018-04-02 09:59:00 +0800 |
|---|---|---|
| committer | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-08-02 15:37:23 +0200 |
| commit | 256cfaaba97a04eb2cd92774834eb73a43df5fb3 (patch) | |
| tree | 6aa2cac9cccc3c471f7b4369daa37cb347354b28 /core | |
| parent | b8fb9cdb76d5cb7c39f8fac51472758e4f7b5e76 (diff) | |
MLK-17962-2 core: arm: imx: a9: tune ACTLR
Tune ACTLR. To SLL, the value is 0xE at runtime.
To others, the value should be 0x4F at runtime.
Bit3 will be enabled when enable L2.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/arch/arm/plat-imx/a9_plat_init.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/core/arch/arm/plat-imx/a9_plat_init.S b/core/arch/arm/plat-imx/a9_plat_init.S index dee142f0..10dda17b 100644 --- a/core/arch/arm/plat-imx/a9_plat_init.S +++ b/core/arch/arm/plat-imx/a9_plat_init.S @@ -91,7 +91,11 @@ UNWIND( .fnstart) mov_imm r0, 0x00004000 write_sctlr r0 - mov_imm r0, 0x00000041 +#ifdef CFG_MX6SLL + mov_imm r0, 0x00000006 +#else + mov_imm r0, 0x00000047 +#endif write_actlr r0 mov_imm r0, 0x00020C00 |