diff options
| author | Franck LENORMAND <franck.lenormand@nxp.com> | 2018-04-17 18:33:59 +0200 |
|---|---|---|
| committer | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-08-02 15:37:23 +0200 |
| commit | b091867c9b658943e6ef74dd481706c9616987e7 (patch) | |
| tree | b9b042cb96bcc0ee5ded759e86ea71fb5fe16aa8 /core | |
| parent | f5e6ec7b02c44b3a2c4da02b8b9acf632f28eb5b (diff) | |
TEE-307 :Enable CAAM clock for imx7ulp
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/arch/arm/plat-imx/registers/imx7ulp-crm_regs.h | 17 | ||||
| -rw-r--r-- | core/arch/arm/plat-imx/registers/imx7ulp-regs.h | 2 | ||||
| -rw-r--r-- | core/drivers/caam/ctrl.c | 9 |
3 files changed, 28 insertions, 0 deletions
diff --git a/core/arch/arm/plat-imx/registers/imx7ulp-crm_regs.h b/core/arch/arm/plat-imx/registers/imx7ulp-crm_regs.h new file mode 100644 index 00000000..765fa629 --- /dev/null +++ b/core/arch/arm/plat-imx/registers/imx7ulp-crm_regs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright 2017 NXP + * + */ + +#ifndef __MX7ULP_CCM_REGS_H__ +#define __MX7ULP_CCM_REGS_H__ + +#define PCC_CGC_BIT_SHIFT 30 + +#define PCC_ENABLE_CLOCK (1 << PCC_CGC_BIT_SHIFT) +#define PCC_DISABLE_CLOCK (0 << PCC_CGC_BIT_SHIFT) + +#define PCC_CAAM 0x90 + +#endif diff --git a/core/arch/arm/plat-imx/registers/imx7ulp-regs.h b/core/arch/arm/plat-imx/registers/imx7ulp-regs.h index b4ab6a4a..339b81a0 100644 --- a/core/arch/arm/plat-imx/registers/imx7ulp-regs.h +++ b/core/arch/arm/plat-imx/registers/imx7ulp-regs.h @@ -7,6 +7,8 @@ #ifndef __IMX7ULP_REGS_H__ #define __IMX7ULP_REGS_H__ +#include <registers/imx7ulp-crm_regs.h> + #define GIC_BASE 0x40020000 #define GIC_SIZE 0x8000 #define GICC_OFFSET 0x2000 diff --git a/core/drivers/caam/ctrl.c b/core/drivers/caam/ctrl.c index 91555a92..e783d96b 100644 --- a/core/drivers/caam/ctrl.c +++ b/core/drivers/caam/ctrl.c @@ -35,7 +35,10 @@ static void caam_clock_enable(unsigned char enable __maybe_unused) { #if !defined(CFG_MX7ULP) vaddr_t ccm_base = (vaddr_t)phys_to_virt(CCM_BASE, MEM_AREA_IO_SEC); +#else + vaddr_t pcc2_base = (vaddr_t)phys_to_virt(PCC2_BASE, MEM_AREA_IO_SEC); #endif + #if defined(CFG_MX6) || defined(CFG_MX6UL) uint32_t reg; uint32_t mask; @@ -76,6 +79,12 @@ static void caam_clock_enable(unsigned char enable __maybe_unused) write32(CCM_CCGRx_ALWAYS_ON(0), ccm_base + CCM_CCGRx_CLR(CCM_CLOCK_DOMAIN_CAAM)); } +#elif defined(CFG_MX7ULP) + if (enable) { + write32(PCC_ENABLE_CLOCK, pcc2_base + PCC_CAAM); + } else { + write32(PCC_DISABLE_CLOCK, pcc2_base + PCC_CAAM); + } #endif } |