MLK-17962-3 core: arm: imx: tune PL310 configuration

The current tag/data ram, prefetch value is not the best value.
With this, the performance is not good. So retune the value
to match i.MX design to have good performance.

Also there is PL310 errata that we need to disable Double linefill
for version below r3p2 pl310.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

6 files changed, 106 insertions, 72 deletions

diff --git a/core/arch/arm/include/kernel/tz_ssvce_def.h b/core/arch/arm/include/kernel/tz_ssvce_def.h
index b11a8700..2cb73271 100644
--- a/core/arch/arm/include/kernel/tz_ssvce_def.h
+++ b/core/arch/arm/include/kernel/tz_ssvce_def.h
@@ -56,6 +56,7 @@
 #define PL310_LINE_SIZE		32
 #define PL310_8_WAYS		8
 
+#define PL310_CACHE_ID		0x0
 /* reg1 */
 #define PL310_CTRL		0x100
 #define PL310_AUX_CTRL		0x104
@@ -84,6 +85,11 @@
 #define PL310_CTRL_ENABLE_BIT	BIT32(0)
 #define PL310_AUX_16WAY_BIT	BIT32(16)
 
+#define PL310_CACHE_ID_PART_MASK	GENMASK_32(9, 6)
+#define PL310_CACHE_ID_PART_L310	(3 << 6)
+#define PL310_CACHE_ID_RTL_MASK		GENMASK_32(5, 0)
+#define PL310_CACHE_ID_RTL_R3P2		0x8
+
 /*
  * SCU iomem
  */
diff --git a/core/arch/arm/plat-imx/config/imx6qdlsolo.h b/core/arch/arm/plat-imx/config/imx6qdlsolo.h
index a2ec6c2c..7b2bfcf2 100644
--- a/core/arch/arm/plat-imx/config/imx6qdlsolo.h
+++ b/core/arch/arm/plat-imx/config/imx6qdlsolo.h
@@ -53,49 +53,63 @@
  * PL310 TAG RAM Control Register
  *
  * bit[10:8]:1 - 2 cycle of write accesses latency
- * bit[6:4]:1 - 2 cycle of read accesses latency
- * bit[2:0]:1 - 2 cycle of setup latency
+ * bit[6:4]:3 - 4 cycle of read accesses latency
+ * bit[2:0]:2 - 3 cycle of setup latency
  */
 #ifndef PL310_TAG_RAM_CTRL_INIT
-#define PL310_TAG_RAM_CTRL_INIT		0x00000111
+#define PL310_TAG_RAM_CTRL_INIT		0x00000132
 #endif
 
 /*
  * PL310 DATA RAM Control Register
  *
- * bit[10:8]:2 - 3 cycle of write accesses latency
- * bit[6:4]:2 - 3 cycle of read accesses latency
+ * bit[10:8]:1 - 2 cycle of write accesses latency
+ * bit[6:4]:3 - 4 cycle of read accesses latency
  * bit[2:0]:2 - 3 cycle of setup latency
  */
 #ifndef PL310_DATA_RAM_CTRL_INIT
-#define PL310_DATA_RAM_CTRL_INIT	0x00000222
+#define PL310_DATA_RAM_CTRL_INIT	0x00000132
 #endif
 
 /*
  * PL310 Auxiliary Control Register
- *
+ */
+#ifndef PL310_AUX_CTRL_INIT
+#if defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D)
+/*
+ * Early BRESP enabled (bit30=1)
+ * I/Dcache prefetch enabled (bit29:28=2b11)
+ * NS can access interrupts (bit27=1)
+ * NS can lockown cache lines (bit26=1)
+ * Pseudo-random replacement policy (bit25=1)
+ * Force write allocated (default) (bit24:23=00)
+ * Shared attribute internally ignored (bit22=1, bit13=0)
+ * Parity disabled (bit21=0)
+ * Event monitor disabled (bit20=0)
+ * 64kb way size (bit19:17=3b011)
+ * 16-way associativity (bit16=1)
+ * Store buffer device limitation disabled (bit11=0)
+ * Cacheable accesses have high prio (bit10=0)
+ * Full Line Zero (FLZ) enabled (bit0=1)
+ */
+#define PL310_AUX_CTRL_INIT		0x7E470001
+#else
+/*
+ * Early BRESP enabled (bit30=0)
  * I/Dcache prefetch enabled (bit29:28=2b11)
  * NS can access interrupts (bit27=1)
  * NS can lockown cache lines (bit26=1)
  * Pseudo-random replacement policy (bit25=0)
- * Force write allocated (default)
+ * Force write allocated (default) (bit24:23=00)
  * Shared attribute internally ignored (bit22=1, bit13=0)
  * Parity disabled (bit21=0)
  * Event monitor disabled (bit20=0)
- * Platform flavor specific way config (dual / quad):
- * - 64kb way size (bit19:17=3b011)
- * - 16-way associativity (bit16=1)
- * Platform flavor specific way config (dual lite / solo):
- * - 32kb way size (bit19:17=3b010)
- * - no 16-way associativity (bit16=0)
+ * 32kb way size (bit19:17=3b010)
+ * 8-way associativity (bit16=0)
  * Store buffer device limitation enabled (bit11=1)
  * Cacheable accesses have high prio (bit10=0)
  * Full Line Zero (FLZ) disabled (bit0=0)
  */
-#ifndef PL310_AUX_CTRL_INIT
-#if defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D)
-#define PL310_AUX_CTRL_INIT		0x3C470800
-#else
 #define PL310_AUX_CTRL_INIT		0x3C440800
 #endif
 #endif
@@ -103,13 +117,13 @@
 /*
  * PL310 Prefetch Control Register
  *
- * Double linefill disabled (bit30=0)
+ * Double linefill enabled (bit30=1)
  * I/D prefetch enabled (bit29:28=2b11)
- * Prefetch drop enabled (bit24=1)
+ * Prefetch drop disabled (bit24=0)
  * Incr double linefill disable (bit23=0)
- * Prefetch offset = 7 (bit4:0)
+ * Prefetch offset = 0xF (bit4:0)
  */
-#define PL310_PREFETCH_CTRL_INIT	0x31000007
+#define PL310_PREFETCH_CTRL_INIT	0x7000000F
 
 /*
  * PL310 Power Register
diff --git a/core/arch/arm/plat-imx/config/imx6sl.h b/core/arch/arm/plat-imx/config/imx6sl.h
index 6b7090bc..b3a6aaeb 100644
--- a/core/arch/arm/plat-imx/config/imx6sl.h
+++ b/core/arch/arm/plat-imx/config/imx6sl.h
@@ -20,59 +20,56 @@
  * PL310 TAG RAM Control Register
  *
  * bit[10:8]:1 - 2 cycle of write accesses latency
- * bit[6:4]:1 - 2 cycle of read accesses latency
- * bit[2:0]:1 - 2 cycle of setup latency
+ * bit[6:4]:3 - 4 cycle of read accesses latency
+ * bit[2:0]:2 - 3 cycle of setup latency
  */
 #ifndef PL310_TAG_RAM_CTRL_INIT
-#define PL310_TAG_RAM_CTRL_INIT		0x00000111
+#define PL310_TAG_RAM_CTRL_INIT		0x00000132
 #endif
 
 /*
  * PL310 DATA RAM Control Register
  *
- * bit[10:8]:2 - 3 cycle of write accesses latency
- * bit[6:4]:2 - 3 cycle of read accesses latency
+ * bit[10:8]:1 - 2 cycle of write accesses latency
+ * bit[6:4]:3 - 4 cycle of read accesses latency
  * bit[2:0]:2 - 3 cycle of setup latency
  */
 #ifndef PL310_DATA_RAM_CTRL_INIT
-#define PL310_DATA_RAM_CTRL_INIT	0x00000222
+#define PL310_DATA_RAM_CTRL_INIT	0x00000132
 #endif
 
 /*
  * PL310 Auxiliary Control Register
  *
+ * Early BRESP enabled (bit30=1)
  * I/Dcache prefetch enabled (bit29:28=2b11)
  * NS can access interrupts (bit27=1)
  * NS can lockown cache lines (bit26=1)
- * Pseudo-random replacement policy (bit25=0)
- * Force write allocated (default)
+ * Pseudo-random replacement policy (bit25=1)
+ * Force write allocated (default) (bit24:23=00)
  * Shared attribute internally ignored (bit22=1, bit13=0)
  * Parity disabled (bit21=0)
  * Event monitor disabled (bit20=0)
- * Platform fmavor specific way config (dual / quad):
- * - 64kb way size (bit19:17=3b011)
- * - 16-way associciativity (bit16=1)
- * Platform fmavor specific way config (dual lite / solo):
- * - 32kb way size (bit19:17=3b010)
- * - no 16-way associciativity (bit16=0)
- * Store buffer device limitation enabled (bit11=1)
+ * 16kb way size (bit19:17=3b001)
+ * 16-way associativity (bit16=1)
+ * Store buffer device limitation enabled (bit11=0)
  * Cacheable accesses have high prio (bit10=0)
- * Full Line Zero (FLZ) disabled (bit0=0)
+ * Full Line Zero (FLZ) enabled (bit0=1)
  */
 #ifndef PL310_AUX_CTRL_INIT
-#define PL310_AUX_CTRL_INIT		0x3C430800
+#define PL310_AUX_CTRL_INIT		0x7E430001
 #endif
 
 /*
  * PL310 Prefetch Control Register
  *
- * Double linefill disabled (bit30=0)
+ * Double linefill enabled (bit30=1)
  * I/D prefetch enabled (bit29:28=2b11)
- * Prefetch drop enabled (bit24=1)
+ * Prefetch drop disabled (bit24=0)
  * Incr double linefill disable (bit23=0)
- * Prefetch offset = 7 (bit4:0)
+ * Prefetch offset = 0xF (bit4:0)
  */
-#define PL310_PREFETCH_CTRL_INIT	0x31000007
+#define PL310_PREFETCH_CTRL_INIT	0x7000000F
 
 /*
  * PL310 Power Register
diff --git a/core/arch/arm/plat-imx/config/imx6sll.h b/core/arch/arm/plat-imx/config/imx6sll.h
index 27415369..433bf616 100644
--- a/core/arch/arm/plat-imx/config/imx6sll.h
+++ b/core/arch/arm/plat-imx/config/imx6sll.h
@@ -20,59 +20,56 @@
  * PL310 TAG RAM Control Register
  *
  * bit[10:8]:1 - 2 cycle of write accesses latency
- * bit[6:4]:1 - 2 cycle of read accesses latency
- * bit[2:0]:1 - 2 cycle of setup latency
+ * bit[6:4]:3 - 4 cycle of read accesses latency
+ * bit[2:0]:2 - 3 cycle of setup latency
  */
 #ifndef PL310_TAG_RAM_CTRL_INIT
-#define PL310_TAG_RAM_CTRL_INIT		0x00000111
+#define PL310_TAG_RAM_CTRL_INIT		0x00000132
 #endif
 
 /*
  * PL310 DATA RAM Control Register
  *
- * bit[10:8]:2 - 3 cycle of write accesses latency
- * bit[6:4]:2 - 3 cycle of read accesses latency
+ * bit[10:8]:1 - 2 cycle of write accesses latency
+ * bit[6:4]:3 - 4 cycle of read accesses latency
  * bit[2:0]:2 - 3 cycle of setup latency
  */
 #ifndef PL310_DATA_RAM_CTRL_INIT
-#define PL310_DATA_RAM_CTRL_INIT	0x00000222
+#define PL310_DATA_RAM_CTRL_INIT	0x00000132
 #endif
 
 /*
  * PL310 Auxiliary Control Register
  *
+ * Early BRESP enabled (bit30=1)
  * I/Dcache prefetch enabled (bit29:28=2b11)
  * NS can access interrupts (bit27=1)
  * NS can lockown cache lines (bit26=1)
- * Pseudo-random replacement policy (bit25=0)
- * Force write allocated (default)
+ * Pseudo-random replacement policy (bit25=1)
+ * Force write allocated (default) (bit24:23=00)
  * Shared attribute internally ignored (bit22=1, bit13=0)
  * Parity disabled (bit21=0)
  * Event monitor disabled (bit20=0)
- * Platform fmavor specific way config (dual / quad):
- * - 64kb way size (bit19:17=3b011)
- * - 16-way associciativity (bit16=1)
- * Platform fmavor specific way config (dual lite / solo):
- * - 32kb way size (bit19:17=3b010)
- * - no 16-way associciativity (bit16=0)
- * Store buffer device limitation enabled (bit11=1)
+ * 16kb way size (bit19:17=3b001)
+ * 16-way associativity (bit16=1)
+ * Store buffer device limitation enabled (bit11=0)
  * Cacheable accesses have high prio (bit10=0)
- * Full Line Zero (FLZ) disabled (bit0=0)
+ * Full Line Zero (FLZ) enabled (bit0=1)
  */
 #ifndef PL310_AUX_CTRL_INIT
-#define PL310_AUX_CTRL_INIT		0x3C430800
+#define PL310_AUX_CTRL_INIT		0x7E430001
 #endif
 
 /*
  * PL310 Prefetch Control Register
  *
- * Double linefill disabled (bit30=0)
+ * Double linefill enabled (bit30=1)
  * I/D prefetch enabled (bit29:28=2b11)
- * Prefetch drop enabled (bit24=1)
+ * Prefetch drop disabled (bit24=0)
  * Incr double linefill disable (bit23=0)
- * Prefetch offset = 7 (bit4:0)
+ * Prefetch offset = 0xF (bit4:0)
  */
-#define PL310_PREFETCH_CTRL_INIT	0x31000007
+#define PL310_PREFETCH_CTRL_INIT	0x7000000F
 
 /*
  * PL310 Power Register
diff --git a/core/arch/arm/plat-imx/config/imx6sx.h b/core/arch/arm/plat-imx/config/imx6sx.h
index 8d170e90..42526e6a 100644
--- a/core/arch/arm/plat-imx/config/imx6sx.h
+++ b/core/arch/arm/plat-imx/config/imx6sx.h
@@ -36,12 +36,13 @@
  * bit[2:0]:2 - 3 cycle of setup latency
  */
 #ifndef PL310_DATA_RAM_CTRL_INIT
-#define PL310_DATA_RAM_CTRL_INIT	0x00000232
+#define PL310_DATA_RAM_CTRL_INIT	0x00000132
 #endif
 
 /*
  * PL310 Auxiliary Control Register
  *
+ * Early BRESP enabled (bit31=1)
  * I/Dcache prefetch enabled (bit29:28=2b11)
  * NS can access interrupts (bit27=1)
  * NS can lockown cache lines (bit26=1)
@@ -55,20 +56,20 @@
  * - 16-way associativity (bit16=1)
  * Store buffer device limitation enabled (bit11=1)
  * Cacheable accesses have high prio (bit10=0)
- * Full Line Zero (FLZ) disabled (bit0=0)
+ * Full Line Zero (FLZ) enabled (bit0=1)
  */
-#define PL310_AUX_CTRL_INIT		0x3C430800
+#define PL310_AUX_CTRL_INIT		0x7E470001
 
 /*
  * PL310 Prefetch Control Register
  *
- * Double linefill disabled (bit30=0)
+ * Double linefill enabled (bit30=1)
  * I/D prefetch enabled (bit29:28=2b11)
- * Prefetch drop enabled (bit24=1)
+ * Prefetch drop disabled (bit24=0)
  * Incr double linefill disable (bit23=0)
- * Prefetch offset = 7 (bit4:0)
+ * Prefetch offset = 0xF (bit4:0)
  */
-#define PL310_PREFETCH_CTRL_INIT	0x31000007
+#define PL310_PREFETCH_CTRL_INIT	0x7000000F
 
 /*
  * PL310 Power Register
diff --git a/core/arch/arm/plat-imx/imx_pl310.c b/core/arch/arm/plat-imx/imx_pl310.c
index 3e872783..76569657 100644
--- a/core/arch/arm/plat-imx/imx_pl310.c
+++ b/core/arch/arm/plat-imx/imx_pl310.c
@@ -25,13 +25,32 @@ register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE);
 
 void arm_cl2_config(vaddr_t pl310_base)
 {
+	uint32_t val, cache_id;
+
 	/* Disable PL310 */
 	write32(0, pl310_base + PL310_CTRL);
 
 	write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL);
 	write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL);
 	write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL);
-	write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL);
+	/*
+	 * The L2 cache controller(PL310) version on the i.MX6D/Q
+	 * is r3p1-50rel0
+	 * The L2 cache controller(PL310) version on the
+	 * i.MX6DL/SOLO/SL/SX/DQP is r3p2.
+	 * But according to ARM PL310 errata: 752271
+	 * ID: 752271: Double linefill feature can cause data corruption
+	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+	 * Workaround: The only workaround to this erratum is to disable the
+	 * double linefill feature. This is the default behavior.
+	 */
+	val = PL310_PREFETCH_CTRL_INIT;
+	cache_id = read32(pl310_base + PL310_CACHE_ID);
+	if (((cache_id & PL310_CACHE_ID_PART_MASK) == PL310_CACHE_ID_PART_L310)
+	    && ((cache_id & PL310_CACHE_ID_RTL_MASK) < PL310_CACHE_ID_RTL_R3P2))
+		val &= ~(1 << 30);
+	write32(val, pl310_base + PL310_PREFETCH_CTRL);
+
 	write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL);
 
 	/* invalidate all cache ways */