TEE-244 drivers: caam: CAAM Initialization

- Add CAAM controller to initialize the JR Owner
	Allow Non-secure world access to Job Rings

- Add RNG entropy configuration

       CAAM control Block 0 registers are not accessible by the CPU
       running in Non-Secure world and so can not configure the RNG
entropy.
       However, the default register settings is not suitable on
       every SoC.
       This is the case for i.MX 6SX and because the RNG entropy is not
       configured correctly, the NS SW can not do the RNG instantiation

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

9 files changed, 932 insertions, 0 deletions

diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk
index f26cd3cf..78a4962a 100644
--- a/core/arch/arm/plat-imx/conf.mk
+++ b/core/arch/arm/plat-imx/conf.mk
@@ -73,6 +73,7 @@ ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL)))
 include core/arch/arm/cpu/cortex-a7.mk
 CFG_IMX_UART ?= y
 CFG_CSU ?= y
+CFG_IMX_CAAM ?= y
 $(call force,CFG_BOOT_SYNC_CPU,n)
 $(call force,CFG_BOOT_SECONDARY_REQUEST,n)
 endif
@@ -88,6 +89,7 @@ CFG_SCU ?= y
 CFG_BOOT_SYNC_CPU ?= y
 CFG_BOOT_SECONDARY_REQUEST ?= y
 CFG_ENABLE_SCTLR_RR ?= y
+CFG_IMX_CAAM ?= y
 endif
 
 # i.MX7 specific config
@@ -95,6 +97,7 @@ ifeq ($(filter y, $(CFG_MX7)), y)
 include core/arch/arm/cpu/cortex-a7.mk
 CFG_BOOT_SECONDARY_REQUEST ?= y
 CFG_INIT_CNTVOFF ?= y
+CFG_IMX_CAAM ?= y
 endif
 
 CFG_MMAP_REGIONS ?= 24
diff --git a/core/drivers/caam/caamrng.c b/core/drivers/caam/caamrng.c
new file mode 100644
index 00000000..d644618c
--- /dev/null
+++ b/core/drivers/caam/caamrng.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+#include <io.h>
+
+#include "intern.h"
+#include "rng_regs.h"
+
+void kick_trng(vaddr_t ctrl_base, uint32_t ent_delay)
+{
+	uint32_t val;
+
+	/* Put RNG in program mode */
+	io_mask32(ctrl_base + TRNG_MCTL, BM_TRNG_MCTL_PRGM, BM_TRNG_MCTL_PRGM);
+
+	/* Configure the RNG Entropy Delay
+	 * Performance-wise, it does not make sense to
+	 * set the delay to a value that is lower
+	 * than the last one that worked (i.e. the state handles
+	 * were instantiated properly. Thus, instead of wasting
+	 * time trying to set the values controlling the sample
+	 * frequency, the function simply returns.
+	 */
+	val = read32(ctrl_base + TRNG_SDCTL);
+	val &= BM_TRNG_SDCTL_ENT_DLY;
+	val >>= BS_TRNG_SDCTL_ENT_DLY;
+
+	if (ent_delay <= val) {
+		/* Put RNG4 into run mode */
+		io_mask32(ctrl_base + TRNG_MCTL,
+			~BM_TRNG_MCTL_PRGM, BM_TRNG_MCTL_PRGM);
+		return;
+	}
+
+	val = read32(ctrl_base + TRNG_SDCTL);
+	val &= ~BM_TRNG_SDCTL_ENT_DLY;
+	val |= ent_delay << BS_TRNG_SDCTL_ENT_DLY;
+	write32(val, ctrl_base + TRNG_SDCTL);
+
+	/* min. freq. count, equal to 1/4 of the entropy sample length */
+	write32(ent_delay >> 2, ctrl_base + TRNG_FRQMIN);
+
+	/* max. freq. count, equal to 16 times the entropy sample length */
+	write32(ent_delay << 4, ctrl_base + TRNG_FRQMAX);
+
+	val = read32(ctrl_base + TRNG_MCTL);
+	/*
+	 * Select raw sampling in both entropy shifter
+	 * and statistical checker
+	 */
+	val &= ~BM_TRNG_MCTL_SAMP_MODE;
+	val |= TRNG_MCTL_SAMP_MODE_RAW_ES_SC;
+	/* Put RNG4 into run mode */
+	val &= ~BM_TRNG_MCTL_PRGM;
+	write32(val, ctrl_base + TRNG_MCTL);
+}
+
+
diff --git a/core/drivers/caam/ctrl.c b/core/drivers/caam/ctrl.c
new file mode 100644
index 00000000..91555a92
--- /dev/null
+++ b/core/drivers/caam/ctrl.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#include <mm/core_memprot.h>
+#include <kernel/dt.h>
+#include <kernel/generic_boot.h>
+#include <initcall.h>
+#include <trace.h>
+#include <types_ext.h>
+#include <io.h>
+#include <libfdt.h>
+
+#include <imx.h>
+
+#include "intern.h"
+#include "ctrl_regs.h"
+#include "version_regs.h"
+#include "rng_regs.h"
+
+//#define DRV_DEBUG
+#ifdef DRV_DEBUG
+#define DRV_TRACE(...)	trace_printf(__func__, __LINE__, 0, false, __VA_ARGS__)
+#else
+#define DRV_TRACE(...)
+#endif
+
+static const char *dt_ctrl_match_table = {
+	"fsl,sec-v4.0-ctrl",
+};
+
+static void caam_clock_enable(unsigned char enable __maybe_unused)
+{
+#if !defined(CFG_MX7ULP)
+	vaddr_t  ccm_base = (vaddr_t)phys_to_virt(CCM_BASE, MEM_AREA_IO_SEC);
+#endif
+#if defined(CFG_MX6) || defined(CFG_MX6UL)
+	uint32_t reg;
+	uint32_t mask;
+
+	reg = read32(ccm_base + CCM_CCGR0);
+
+	mask = (BM_CCM_CCGR0_CAAM_WRAPPER_IPG  |
+			BM_CCM_CCGR0_CAAM_WRAPPER_ACLK |
+			BM_CCM_CCGR0_CAAM_SECURE_MEM);
+
+	if (enable) {
+		reg |= mask;
+	} else {
+		reg &= ~mask;
+	}
+
+	write32(reg, (ccm_base + CCM_CCGR0));
+
+	if (!soc_is_imx6ul()) {
+		/* EMI slow clk */
+		reg  = read32(ccm_base + CCM_CCGR6);
+		mask = BM_CCM_CCGR6_EMI_SLOW;
+
+		if (enable) {
+			reg |= mask;
+		} else {
+			reg &= ~mask;
+		}
+
+		write32(reg, (ccm_base + CCM_CCGR6));
+	}
+
+#elif defined(CFG_MX7)
+	if (enable) {
+		write32(CCM_CCGRx_ALWAYS_ON(0),
+			ccm_base + CCM_CCGRx_SET(CCM_CLOCK_DOMAIN_CAAM));
+	} else {
+		write32(CCM_CCGRx_ALWAYS_ON(0),
+			ccm_base + CCM_CCGRx_CLR(CCM_CLOCK_DOMAIN_CAAM));
+	}
+#endif
+}
+
+static TEE_Result caam_init(void)
+{
+	TEE_Result ret = TEE_SUCCESS;
+	size_t  size;
+	vaddr_t ctrl_base;
+	uint32_t jrnum, idx;
+
+	void *fdt;
+	int  node;
+
+	fdt = get_dt_blob();
+	if (!fdt) {
+		DRV_TRACE("No DTB\n");
+		return TEE_ERROR_NOT_SUPPORTED;
+	}
+
+	node = fdt_node_offset_by_compatible(fdt, 0, dt_ctrl_match_table);
+
+	if (node < 0) {
+		DRV_TRACE("Caam Node not found err = 0x%X\n", node);
+	}
+
+	/* Map the device in the system if not already present */
+	if (dt_map_dev(fdt, node, &ctrl_base, &size) < 0) {
+		DRV_TRACE("CAAM device not defined or not enabled\n");
+		ret = TEE_ERROR_GENERIC;
+		goto probe_exit;
+	}
+
+	/* Enable the CAAM clock - at this stage the OS is not loaded */
+	caam_clock_enable(1);
+
+	/*
+	 * Enable DECO watchdogs
+	 */
+	io_mask32(ctrl_base + MCFGR, BM_MCFGR_WDE, BM_MCFGR_WDE);
+
+	/*
+	 * ERRATA:  mx6 devices have an issue wherein AXI bus transactions
+	 * may not occur in the correct order. This isn't a problem running
+	 * single descriptors, but can be if running multiple concurrent
+	 * descriptors. Reworking the driver to throttle to single requests
+	 * is impractical, thus the workaround is to limit the AXI pipeline
+	 * to a depth of 1 (from it's default of 4) to preclude this situation
+	 * from occurring.
+	 *
+	 * mx7 devices, this bit has no effect.
+	 */
+	io_mask32(ctrl_base + MCFGR, (1 << BS_MCFGR_AXIPIPE), BM_MCFGR_AXIPIPE);
+
+	/*
+	 * Make all Job Rings available in the HW as accessible in Non-Secure.
+	 * Job Rings used by the TEE will be secured by the JR Driver Loaded
+	 * itself.
+	 * Don't Lock the configuration yet, will be done after loading all
+	 * Job Ring drivers
+	 */
+	jrnum = read32(ctrl_base + CHANUM_MS) & BM_CHANUM_MS_JRNUM;
+	jrnum >>= BS_CHANUM_MS_JRNUM;
+	DRV_TRACE("Number of Job Ring available = %d", jrnum);
+
+	if (jrnum == 0) {
+		EMSG("No HW Job Ring available");
+		ret = TEE_ERROR_GENERIC;
+		goto probe_exit;
+	}
+
+	for (idx = 0; idx < jrnum; idx++) {
+		write32(((MSTRID_NS_ARM << BS_JRxMIDR_LS_NONSEQ_MID) |
+				 (MSTRID_NS_ARM << BS_JRxMIDR_LS_SEQ_MID)),
+				ctrl_base + JRxMIDR_LS(idx));
+		write32((MSTRID_NS_ARM << BS_JRxMIDR_MS_JROWN_MID),
+				ctrl_base + JRxMIDR_MS(idx));
+	}
+
+	/* Lock all Job Ring access configuration */
+	for (idx = 0; idx < jrnum; idx++) {
+		DRV_TRACE("Lock JR[%d] Configuration", idx);
+		io_mask32(ctrl_base + JRxMIDR_MS(idx),
+			BM_JRxMIDR_MS_LMID, BM_JRxMIDR_MS_LMID);
+	}
+
+
+	/*
+	 * Configure the TRNG Entropy delay because some soc have no
+	 * access to the TRNG registers in Non-Secure (e.g. 6SX)
+	 */
+	kick_trng(ctrl_base, TRNG_SDCTL_ENT_DLY_MIN);
+
+probe_exit:
+	return ret;
+}
+
+
+driver_init(caam_init);
diff --git a/core/drivers/caam/include/ctrl_regs.h b/core/drivers/caam/include/ctrl_regs.h
new file mode 100644
index 00000000..8d3af887
--- /dev/null
+++ b/core/drivers/caam/include/ctrl_regs.h
@@ -0,0 +1,283 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+#ifndef __CTRL_REGS_H__
+#define __CTRL_REGS_H__
+
+/* Master Configuration */
+#define MCFGR				(0x0004)
+
+#define BS_MCFGR_SWRST			(31)
+#define BM_MCFGR_SWRST			(0x1 << BS_MCFGR_SWRST)
+#define BS_MCFGR_WDE			(30)
+#define BM_MCFGR_WDE			(0x1 << BS_MCFGR_WDE)
+#define BS_MCFGR_WDF			(29)
+#define BM_MCFGR_WDF			(0x1 << BS_MCFGR_WDF)
+#define BS_MCFGR_DMA_RST		(28)
+#define BM_MCFGR_DMA_RST		(0x1 << BS_MCFGR_DMA_RST)
+#define BS_MCFGR_WRHD			(27)
+#define BM_MCFGR_WRHD			(0x1 << BS_MCFGR_WRHD)
+#define BS_MCFGR_DWT			(19)
+#define BM_MCFGR_DWT			(0x1 << BS_MCFGR_DWT)
+#define BS_MCFGR_ARCACHE		(12)
+#define BM_MCFGR_ARCACHE		(0xF << BS_MCFGR_ARCACHE)
+#define BS_MCFGR_AWCACHE		(8)
+#define BM_MCFGR_AWCACHE		(0xF << BS_MCFGR_AWCACHE)
+#define BS_MCFGR_AXIPIPE		(4)
+#define BM_MCFGR_AXIPIPE		(0xF << BS_MCFGR_AXIPIPE)
+#define BS_MCFGR_LARGE_BURST	(2)
+#define BM_MCFGR_LARGE_BURST	(0x1 << BS_MCFGR_LARGE_BURST)
+
+/* Security Configuration */
+#define SCFGR				(0x000C)
+
+#define BS_SCFGR_MPCURVE	(28)
+#define BM_SCFGR_MPCURVE	(0xF << BS_SCFGR_MPCURVE)
+#define BS_SCFGR_MPPKRC		(27)
+#define BM_SCFGR_MPPKRC		(0x1 << BS_SCFGR_MPPKRC)
+#define BS_SCFGR_MPMRL		(26)
+#define BM_SCFGR_MPMRL		(0x1 << BS_SCFGR_MPMRL)
+#define BS_SCFGR_LCK_TRNG	(11)
+#define BM_SCFGR_LCK_TRNG	(0x1 << BS_SCFGR_LCK_TRNG)
+#define BS_SCFGR_RDB		(10)
+#define BM_SCFGR_RDB		(0x1 << BS_SCFGR_RDB)
+#define BS_SCFGR_RNGSH0		(9)
+#define BM_SCFGR_RNGSH0		(0x1 << BS_SCFGR_RNGSH0)
+#define BS_SCFGR_RANDDPAR	(8)
+#define BM_SCFGR_RANDDPAR	(0x1 << BS_SCFGR_RANDDPAR)
+#define BS_SCFGR_PRIBLOB	(0)
+#define BM_SCFGR_PRIBLOB	(0x3 << BS_SCFGR_PRIBLOB)
+
+#define SCFGR_PRIBLOB_PRIV_SECURE_BOOT	(0x0)
+#define SCFGR_PRIBLOB_PRIV_TYPE_1		(0x1)
+#define SCFGR_PRIBLOB_PRIV_TYPE_2		(0x2)
+#define SCFGR_PRIBLOB_NORMAL			(0x3)
+
+/* Job Ring x MID */
+#define JRxMIDR_SIZE			(0x8)
+#define JR0MIDR_MS			(0x0010)
+#define JR0MIDR_LS			(0x0014)
+#define JRxMIDR_MS(idx)			(JR0MIDR_MS + (idx * JRxMIDR_SIZE))
+#define JRxMIDR_LS(idx)			(JR0MIDR_LS + (idx * JRxMIDR_SIZE))
+
+#define BS_JRxMIDR_MS_LMID		(31)
+#define BM_JRxMIDR_MS_LMID		(1 << BS_JRxMIDR_MS_LMID)
+#define BS_JRxMIDR_MS_LAMTD		(17)
+#define BM_JRxMIDR_MS_LAMTD		(1 << BS_JRxMIDR_MS_LAMTD)
+#define BS_JRxMIDR_MS_AMTD		(16)
+#define BM_JRxMIDR_MS_AMTD		(1 << BS_JRxMIDR_MS_AMTD)
+#define BS_JRxMIDR_MS_TZ		(15)
+#define BM_JRxMIDR_MS_TZ		(1 << BS_JRxMIDR_MS_TZ)
+#if !defined(CFG_MX7ULP)
+#define BS_JRxMIDR_MS_SDID_MS		(4)
+#define BM_JRxMIDR_MS_SDID_MS		(0xFF << BS_JRxMIDR_MS_SDID_MS)
+#define BS_JRxMIDR_MS_JROWN_NS		(3)
+#define BM_JRxMIDR_MS_JROWN_NS		(0x1 << BS_JRxMIDR_MS_JROWN_NS)
+#define BS_JRxMIDR_MS_JROWN_MID		(0)
+#define BM_JRxMIDR_MS_JROWN_MID		(0x7 << BS_JRxMIDR_MS_JROWN_MID)
+
+#define BS_JRxMIDR_LS_NONSEQ_NS		(19)
+#define BM_JRxMIDR_LS_NONSEQ_NS		(0x1 << BS_JRxMIDR_LS_NONSEQ_NS)
+#define BS_JRxMIDR_LS_NONSEQ_MID	(16)
+#define BM_JRxMIDR_LS_NONSEQ_MID	(0x7 << BS_JRxMIDR_LS_NONSEQ_MID)
+#define BS_JRxMIDR_LS_SEQ_NS		(3)
+#define BM_JRxMIDR_LS_SEQ_NS		(0x1 << BS_JRxMIDR_LS_SEQ_NS)
+#define BS_JRxMIDR_LS_SEQ_MID		(0)
+#define BM_JRxMIDR_LS_SEQ_MID		(0x7 << BS_JRxMIDR_LS_SEQ_MID)
+
+#define MSTRID_DMA	0
+#define MSTRID_ARM	1
+#define MSTRID_CAAM	2
+#define MSTRID_SDMA	3
+
+#define MSTRID_S_DMA	(MSTRID_DMA)
+#define MSTRID_S_ARM	(MSTRID_ARM)
+#define MSTRID_S_CAAM	(MSTRID_CAAM)
+#define MSTRID_S_SDMA	(MSTRID_SDMA)
+#define MSTRID_NS_DMA	(MSTRID_DMA  | BM_JRxMIDR_MS_JROWN_NS)
+#define MSTRID_NS_ARM	(MSTRID_ARM  | BM_JRxMIDR_MS_JROWN_NS)
+#define MSTRID_NS_CAAM	(MSTRID_CAAM | BM_JRxMIDR_MS_JROWN_NS)
+#define MSTRID_NS_SDMA	(MSTRID_SDMA | BM_JRxMIDR_MS_JROWN_NS)
+
+#else
+
+#define BS_JRxMIDR_MS_SDID_MS		(5)
+#define BM_JRxMIDR_MS_SDID_MS		(0x7F << BS_JRxMIDR_MS_SDID_MS)
+#define BS_JRxMIDR_MS_JROWN_NS		(4)
+#define BM_JRxMIDR_MS_JROWN_NS		(0x1 << BS_JRxMIDR_MS_JROWN_NS)
+#define BS_JRxMIDR_MS_JROWN_MID		(0)
+#define BM_JRxMIDR_MS_JROWN_MID		(0xF << BS_JRxMIDR_MS_JROWN_MID)
+
+#define BS_JRxMIDR_LS_NONSEQ_NS		(20)
+#define BM_JRxMIDR_LS_NONSEQ_NS		(0x1 << BS_JRxMIDR_LS_NONSEQ_NS)
+#define BS_JRxMIDR_LS_NONSEQ_MID	(16)
+#define BM_JRxMIDR_LS_NONSEQ_MID	(0xF << BS_JRxMIDR_LS_NONSEQ_MID)
+#define BS_JRxMIDR_LS_SEQ_NS		(4)
+#define BM_JRxMIDR_LS_SEQ_NS		(0x1 << BS_JRxMIDR_LS_SEQ_NS)
+#define BS_JRxMIDR_LS_SEQ_MID		(0)
+#define BM_JRxMIDR_LS_SEQ_MID		(0xF << BS_JRxMIDR_LS_SEQ_MID)
+
+#define MSTRID_CM4	0x0
+#define MSTRID_CM4DAP	0x1
+#define MSTRID_DMA0	0x2
+#define MSTRID_ETR	0x3
+#define MSTRID_CA7	0x4
+#define MSTRID_DSI	0x5
+#define MSTRID_GPU3D	0x6
+#define MSTRID_GPU2D	0x7
+#define MSTRID_DMA1	0x8
+#define MSTRID_CAAM	0x9
+#define MSTRID_USB	0xA
+#define MSTRID_VIU	0xB
+#define MSTRID_uSDHC0	0xC
+#define MSTRID_uSDHC1	0xD
+#define MSTRID_RSV1	0xE
+#define MSTRID_RSV2	0xF
+
+
+#define MSTRID_S_ARM	(MSTRID_CA7)
+#define MSTRID_S_CAAM	(MSTRID_CAAM)
+
+#define MSTRID_NS_ARM	(MSTRID_CA7  | BM_JRxMIDR_MS_JROWN_NS)
+#define MSTRID_NS_CAAM	(MSTRID_CAAM | BM_JRxMIDR_MS_JROWN_NS)
+
+#endif
+
+/* Debug Control */
+#define DEBUGCTL			(0x0058)
+/* Job Ring Start */
+#define JRSTARTR			(0x005C)
+
+/* RTIC MID for Block x */
+#define RTICxMIDR_SIZE		(0x8)
+#define RTICAMIDR_MS		(0x0060)
+#define RTICAMIDR_LS		(0x0064)
+#define RTICxMIDR_MS(idx)	(RTICAMIDR_MS + (idx * RTICxMIDR_SIZE))
+#define RTICxMIDR_LS(idx)	(RTICAMIDR_LS + (idx * RTICxMIDR_SIZE))
+
+/* DECO */
+#define DECO_REQ_SRC		(0x0090)
+#define DECO_REQUEST		(0x009C)
+#define DECO0MIDR_MS		(0x00A0)
+#define DECO0MIDR_LS		(0x00A4)
+#define DECO_AVAILABLE		(0x0120)
+#define DECO_RESET			(0x0124)
+
+#define BS_DECO_REQ_SRC_VALID	(31)
+#define BM_DECO_REQ_SRC_VALID	(0x1 << BS_DECO_REQ_SRC_VALID)
+#define BS_DECO_REQ_SRC_JR0		(0)
+#define BM_DECO_REQ_SRC_JR0		(0x1 << BS_DECO_REQ_SRC_JR0)
+
+#define BS_DECO_REQUEST_DEN0	(16)
+#define BM_DECO_REQUEST_DEN0	(0x1 << BS_DECO_REQUEST_DEN0)
+#define BS_DECO_REQUEST_RQD0	(0)
+#define BM_DECO_REQUEST_RQD0	(0x1 << BS_DECO_REQUEST_RQD0)
+
+/* DMA Aliasing */
+#define	ALIAS_DMAC			(0x0204)
+#define ALIAS_DMA0AIML_MS	(0x0240)
+#define ALIAS_DMA0AIML_LS	(0x0244)
+#define ALIAS_DMA0AIMH_MS	(0x0248)
+#define ALIAS_DMA0AIMH_LS	(0x024C)
+#define ALIAS_DMA0AIE		(0x0254)
+#define ALIAS_DMA0ARTC		(0x0260)
+#define ALIAS_DMA0ARL		(0x026C)
+#define ALIAS_DMA0AWTC		(0x0270)
+#define ALIAS_DMA0AWL		(0x027C)
+
+/* Manufacturing Protection Private Key */
+#define MPPKR_x_SIZE		(0x0001)
+#define MPPKR_0				(0x0300)
+#define MPPKR_x(idx)		(MPPKR_0 + (idx * MPPKR_x_SIZE))
+/* Manufacturing Protection Message */
+#define MPMRx_SIZE			(0x0001)
+#define MPMR_0				(0x0380)
+#define MPMR_x(idx)			(MPMR_0 + (idx * MPMR_x_SIZE))
+/* Manufacturing Protection Test */
+#define MPTESTR_x_SIZE		(0x0001)
+#define MPTESTR_0			(0x03C0)
+#define MPTESTR_x(idx)		(MPTESTR_0 + (idx * MPTESTR_x_SIZE))
+
+/* Job Descriptor Key Encryption Key (JDKEK) */
+#define JDKEKR_x_SIZE		(0x0001)
+#define JDKEKR_0			(0x0400)
+#define JDKEKR_x(idx)		(JDKEKR_0 + (idx * JDKEKR_x_SIZE))
+/* Trusted Descriptor Key Encryption Key (TDKEK) */
+#define TDKEKR_x_SIZE		(0x0001)
+#define TDKEKR_0			(0x0420)
+#define TDKEKR_x(idx)		(TDKEKR_0 + (idx * TDKEKR_x_SIZE))
+/* Trusted Descriptor Signing Key (TDSK) */
+#define TDSKR_x_SIZE		(0x0001)
+#define TDSKR_0				(0x0440)
+#define TDSKR_x(idx)		(TDSKR_0 + (idx * TDSKR_x_SIZE))
+/* Secure Key Nonce (SKN)*/
+#define SKNR				(0x04E0)
+
+/* DMA Aliasing */
+#define DMA_STA_REG					(0x0500)
+#define DMA_CTL_REG					(0x0504)
+#define DMA0_AID_7_0_MAP_REG_MS		(0x0510)
+#define DMA0_AID_7_0_MAP_REG_LS		(0x0514)
+#define DMA0_AID_15_8_MAP_REG_MS	(0x0518)
+#define DMA0_AID_15_8_MAP_REG_LS	(0x051C)
+#define DMA0_AID_15_0_EN_REG		(0x0524)
+#define DMA0ARTC_CTL_REG			(0x0530)
+#define DMA0ARTC_LC_REG				(0x0534)
+#define DMA0ARTC_SC_REG				(0x0538)
+#define DMA0ARTC_LAT_REG			(0x053C)
+#define DMA0AWTC_CTL_REG			(0x0540)
+#define DMA0AWTC_LC_REG				(0x0544)
+#define DMA0AWTC_SC_REG				(0x0548)
+#define DMA0AWTC_LAT_REG			(0x054C)
+
+/* Recoverable Error Indication Status */
+#define REIS	(0x0B00)
+/* Recoverable Error Indication Halt */
+#define REIH	(0x0B0C)
+
+/*
+ * Debug Registers
+ */
+/* Holding Tank 0 */
+#define	HT0_JD_ADDR		(0x0C00)
+#define HT0_SD_ADDR		(0x0C08)
+#define HT0_JQ_CTRL_MS	(0x0C10)
+#define HT0_JQ_CTRL_LS	(0x0C14)
+#define HT0_STATUS		(0x0C1C)
+#define JQ_DEBUG_SEL	(0x0C24)
+#define JRJIDU_LS		(0x0DBC)
+#define JRJDJIFBC		(0x0DC0)
+#define JRJDJIF			(0x0DC4)
+#define JRJDS1			(0x0DE4)
+#define JRJDDA			(0x0E00)
+
+/*
+ * Secure Memory
+ */
+#define SMSTA		(0x0FB4)
+#define SMPO		(0x0FBC)
+
+#define BS_SMPO_PO			(2)
+#define BM_SMPO_PO			(0x3)
+
+#define BS_SMPO_POx(idx)		(idx * BS_SMPO_PO)
+#define BM_SMPO_POx(idx)		(BM_SMPO_PO << BS_SMPO_POx(idx))
+#define GET_SMPO_POx(val, idx)	((val >> BS_SMPO_POx(idx)) & BM_SMPO_PO)
+
+#define SMPO_POx_AVAILABLE		(0)
+#define SMPO_POx_NOEXIST		(1)
+#define SMPO_POx_UNAVAILABLE	(2)
+#define SMPO_POx_OURS			(3)
+
+/* Fault Address */
+#define FAR			(0x0FC0)
+#define FAMR		(0x0FC8)
+#define FADR		(0x0FCC)
+
+/* CAAM Status */
+#define CSTA		(0x0FD4)
+
+#endif /* __CTRL_REGS_H__ */
+
diff --git a/core/drivers/caam/include/rng_regs.h b/core/drivers/caam/include/rng_regs.h
new file mode 100644
index 00000000..94bb0fea
--- /dev/null
+++ b/core/drivers/caam/include/rng_regs.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+#ifndef __RNG_REGS_H__
+#define __RNG_REGS_H__
+
+/*
+ * RNG Test Registers
+ */
+/* Miscellaneous Control */
+#define TRNG_MCTL			(0x0600)
+
+#define BS_TRNG_MCTL_PRGM		(16)
+#define BM_TRNG_MCTL_PRGM		(0x1 << BS_TRNG_MCTL_PRGM)
+#define BS_TRNG_MCTL_TSTOP_OK		(13)
+#define BM_TRNG_MCTL_TSTOP_OK		(0x1 << BS_TRNG_MCTL_TSTOP_OK)
+#define BS_TRNG_MCTL_ERR		(12)
+#define BM_TRNG_MCTL_ERR		(0x1 << BS_TRNG_MCTL_ERR)
+#define BS_TRNG_MCTL_TEST_OUT		(11)
+#define BM_TRNG_MCTL_TEST_OUT		(0x1 << BS_TRNG_MCTL_TEST_OUT)
+#define BS_TRNG_MCTL_ENT_VAL		(10)
+#define BM_TRNG_MCTL_ENT_VAL		(0x1 << BS_TRNG_MCTL_ENT_VAL)
+#define BS_TRNG_MCTL_FCT_VAL		(9)
+#define BM_TRNG_MCTL_FCT_VAL		(0x1 << BS_TRNG_MCTL_FCT_VAL)
+#define BS_TRNG_MCTL_FCT_FAIL		(8)
+#define BM_TRNG_MCTL_FCT_FAIL		(0x1 << BS_TRNG_MCTL_FCT_FAIL)
+#define BS_TRNG_MCTL_FORCE_SYSCLK	(7)
+#define BM_TRNG_MCTL_FORCE_SYSCLK	(0x1 << BS_TRNG_MCTL_FORCE_SYSCLK)
+#define BS_TRNG_MCTL_RST_DEF		(6)
+#define BM_TRNG_MCTL_RST_DEF		(0x1 << BS_TRNG_MCTL_RST_DEF)
+#define BS_TRNG_MCTL_TRNG_ACC		(5)
+#define BM_TRNG_MCTL_TRNG_ACC		(0x1 << BS_TRNG_MCTL_TRNG_ACC)
+#define BS_TRNG_MCTL_CLK_OUT_EN		(4)
+#define BM_TRNG_MCTL_CLK_OUT_EN		(0x1 << BS_TRNG_MCTL_CLK_OUT_EN)
+#define BS_TRNG_MCTL_OSC_DIV		(2)
+#define BM_TRNG_MCTL_OSC_DIV		(0x3 << BS_TRNG_MCTL_OSC_DIV)
+#define BS_TRNG_MCTL_SAMP_MODE		(0)
+#define BM_TRNG_MCTL_SAMP_MODE		(0x3 << BS_TRNG_MCTL_SAMP_MODE)
+
+/* use von Neumann data in both entropy shifter and statistical checker */
+#define	TRNG_MCTL_SAMP_MODE_VON_NEUMANN_ES_SC		\
+				(0 << BS_TRNG_MCTL_SAMP_MODE)
+/* use raw data in both entropy shifter and statistical checker */
+#define TRNG_MCTL_SAMP_MODE_RAW_ES_SC			\
+				(1 << BS_TRNG_MCTL_SAMP_MODE)
+/* use von Neumann data in entropy shifter, raw data in statistical checker */
+#define TRNG_MCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC	\
+				(2 << BS_TRNG_MCTL_SAMP_MODE)
+/* invalid combination */
+#define TRNG_MCTL_SAMP_MODE_INVALID			\
+				(3 << BS_TRNG_MCTL_SAMP_MODE)
+
+/* Statistical Check Miscellaneous */
+#define TRNG_SCMISC			(0x0604)
+/* Poker Range */
+#define TRNG_PKRRNG			(0x0608)
+/* Poker Maximum Limit */
+#define TRNG_PKRMAX			(0x060C)
+/* Poker Square Calculation Result */
+#define TRNG_PKRSQ			(0x060C)
+/* Seed Control */
+#define TRNG_SDCTL			(0x0610)
+
+#define BS_TRNG_SDCTL_ENT_DLY	(16)
+#define BM_TRNG_SDCTL_ENT_DLY	(0xFFFF << BS_TRNG_SDCTL_ENT_DLY)
+#define TRNG_SDCTL_ENT_DLY_MIN	(3200)
+#define TRNG_SDCTL_ENT_DLY_MAX	(12800)
+
+#define BS_TRNG_SDCTL_SAMP_SIZE	(0)
+#define BM_TRNG_SDCTL_SAMP_SIZE	(0xFFFF << BS_TRNG_SDCTL_SAMP_SIZE)
+
+/* Total Samples */
+#define TRNG_TOTSAM		(0x0614)
+/* Sparse Bit Limit */
+#define TRNG_SBLIM		(0x0614)
+/* Frequency Count Minimum Limit */
+#define TRNG_FRQMIN		(0x0618)
+/* Frequency Count */
+#define TRNG_FRQCNT		(0x061C)
+/* Frequency Count Maximum Limit */
+#define TRNG_FRQMAX		(0x061C)
+/* Statistical Check Monobit Limit */
+#define TRNG_SCML		(0x0620)
+/* Statistical Check Monobit Count */
+#define TRNG_SCMC		(0x0620)
+
+/* Statistical Check Run Length x */
+#define TRNG_SCRx_SIZE		(0x4)
+#define TRNG_SCR1L		(0x0624)
+#define TRNG_SCR1C		(0x0624)
+#define TRNG_SCRxL(idx)		(TRNG_SCR1L + (idx * TRNG_SCRx_SIZE))
+#define TRNG_SCRxC(idx)		(TRNG_SCR1C + (idx * TRNG_SCRx_SIZE))
+
+/* Status */
+#define TRNG_STATUS		(0x063C)
+
+/* Entropy Read x */
+#define TRNG_ENTx_SIZE		(0x4)
+#define TRNG_ENT0		(0x0640)
+#define TRNG_ENTx(idx)		(TRNG_ENT0 + (idx * TRNG_ENTx_SIZE))
+
+/* Statistical Check Poker Count x and (x + 1) */
+#define TRNG_PKRCNTx_SIZE	(0x4)
+#define TRNG_PKRCNT10		(0x0680)
+#define TRNG_PKRCNTx(idx)	(TRNG_PKRCNT10 + (idx * TRNG_PKRCNTx_SIZE))
+
+/*
+ * RNG Registers
+ */
+/* Status */
+#define RNG_STA			(0x06C0)
+
+#define BS_RNG_STA_SKVT		(31)
+#define BM_RNG_STA_SKVT		(0x1 << BS_RNG_STA_SKVT)
+#define BS_RNG_STA_SKVN		(30)
+#define BM_RNG_STA_SKVN		(0x1 << BS_RNG_STA_SKVN)
+#define BS_RNG_STA_CE		(20)
+#define BM_RNG_STA_CE		(0x1 << BS_RNG_STA_CE)
+#define BS_RNG_STA_ERRCODE	(16)
+#define BM_RNG_STA_ERRCODE	(0xF << BS_RNG_STA_ERRCODE)
+#define BS_RNG_STA_TF1		(9)
+#define BM_RNG_STA_TF1		(0x1 << BS_RNG_STA_TF1)
+#define BS_RNG_STA_TF0		(8)
+#define BM_RNG_STA_TF0		(0x1 << BS_RNG_STA_TF0)
+#define BS_RNG_STA_PR1		(5)
+#define BM_RNG_STA_PR1		(0x1 << BS_RNG_STA_PR1)
+#define BS_RNG_STA_PR0		(4)
+#define BM_RNG_STA_PR0		(0x1 << BS_RNG_STA_PR0)
+#define BS_RNG_STA_IF1		(1)
+#define BM_RNG_STA_IF1		(0x1 << BS_RNG_STA_IF1)
+#define BS_RNG_STA_IF0		(0)
+#define BM_RNG_STA_IF0		(0x1 << BS_RNG_STA_IF0)
+
+/* State Handle 0 Reseed Interval */
+#define RNG_INT0		(0x06D0)
+/* State Handle 1 Reseed Interval */
+#define RNG_INT1		(0x06D4)
+/* Hash Control */
+#define RNG_HCNTL		(0x06E0)
+/* Hash Digest */
+#define RNG_HDIG		(0x06E4)
+/* Hash Buffer */
+#define RNG_HBUF		(0x06E8)
+
+#endif /* __RNG_REGS_H__ */
diff --git a/core/drivers/caam/include/version_regs.h b/core/drivers/caam/include/version_regs.h
new file mode 100644
index 00000000..f852bf2e
--- /dev/null
+++ b/core/drivers/caam/include/version_regs.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+#ifndef __VERSION_REGS_H__
+#define __VERSION_REGS_H__
+
+/*
+ * HW revision/version
+ */
+/* CHA Revision Number */
+#define CRNR_MS		(0x0FA0)
+#define CRNR_LS		(0x0FA4)
+
+#define BS_CRNR_MS_JRRN		(28)
+#define BM_CRNR_MS_JRRN		(0xF << BS_CRNR_MS_JRRN)
+#define BS_CRNR_MS_DECORN	(24)
+#define BM_CRNR_MS_DECORN	(0xF << BS_CRNR_MS_DECORN)
+
+#define BS_CRNR_LS_PKRN		(28)
+#define BM_CRNR_LS_PKRN		(0xF << BS_CRNR_LS_PKRN)
+#define BS_CRNR_LS_RNGRN	(16)
+#define BM_CRNR_LS_RNGRN	(0xF << BS_CRNR_LS_RNGRN)
+#define BS_CRNR_LS_MDRN		(12)
+#define BM_CRNR_LS_MDRN		(0xF << BS_CRNR_LS_MDRN)
+#define BS_CRNR_LS_ARC4RN	(8)
+#define BM_CRNR_LS_ARC4RN	(0xF << BS_CRNR_LS_ARC4RN)
+#define BS_CRNR_LS_DESRN	(4)
+#define BM_CRNR_LS_DESRN	(0xF << BS_CRNR_LS_DESRN)
+#define BS_CRNR_LS_AESRN	(0)
+#define BM_CRNR_LS_AESRN	(0xF << BS_CRNR_LS_AESRN)
+
+/* Compile Time Parameters */
+#define CTPR_MS		(0x0FA8)
+#define CTPR_LS		(0x0FAC)
+
+#define BS_CTPR_MS_AXI_PIPE_DEPTH	(28)
+#define BM_CTPR_MS_AXI_PIPE_DEPTH	(0xF << BS_CTPR_MS_AXI_PIPE_DEPTH)
+#define BS_CTPR_MS_AXI_MID		(27)
+#define BM_CTPR_MS_AXI_MID		(0x1 << BS_CTPR_MS_AXI_MID)
+#define BS_CTPR_MS_AXI_PRI		(26)
+#define BM_CTPR_MS_AXI_PRI		(0x1 << BS_CTPR_MS_PRI)
+#define BS_CTPR_MS_QI			(25)
+#define BM_CTPR_MS_QI			(0x1 << BS_CTPR_MS_QI)
+#define BS_CTPR_MS_ACC_CTL		(24)
+#define BM_CTPR_MS_ACC_CTL		(0x1 << BS_CTPR_MS_ACC_CTL)
+#define BS_CTPR_MS_C1C2			(23)
+#define BM_CTPR_MS_C1C2			(0x1 << BS_CTPR_MS_C1C2)
+#define BS_CTPR_MS_PC			(21)
+#define BM_CTPR_MS_PC			(0x1 << BS_CTPR_MS_PC)
+#define BS_CTPR_MS_DECO_WD		(20)
+#define BM_CTPR_MS_DECO_WD		(0x1 << BS_CTPR_MS_DECO_WD)
+#define BS_CTPR_MS_PM_EVT_BUS		(19)
+#define BM_CTPR_MS_PM_EVT_BUS		(0x1 << BS_CTPR_MS_PM_EVT_BUS)
+#define BS_CTPR_MS_SG8			(18)
+#define BM_CTPR_MS_SG8			(0x1 << BS_CTPR_MS_SG8)
+#define BS_CTPR_MS_MCFG_PS		(17)
+#define BM_CTPR_MS_MCFG_PS		(0x1 << BS_CTPR_MS_MCFG_PS)
+#define BS_CTPR_MS_MCFG_BURST		(16)
+#define BM_CTPR_MS_MCFG_BURST		(0x1 << BS_CTPR_MS_MCFG_BURST)
+#define BS_CTPR_MS_IP_CLK		(14)
+#define BM_CTPR_MS_IP_CLK		(0x1 << BS_CTPR_MS_IP_CLK)
+#define BS_CTPR_MS_DPAA2		(13)
+#define BM_CTPR_MS_DPAA2		(0x1 << BS_CTPR_MS_DPAA2)
+#define BS_CTPR_MS_AI_INCL		(11)
+#define BM_CTPR_MS_AI_INCL		(0x1 << BS_CTPR_MS_AI_INCL)
+#define BS_CTPR_MS_RNG_I		(8)
+#define BM_CTPR_MS_RNG_I		(0x7 << BS_CTPR_MS_RNG_I)
+#define BS_CTPR_MS_REG_PG_SIZE		(4)
+#define BM_CTPR_MS_REG_PG_SIZE		(0x1 << BS_CTPR_MS_REG_PG_SIZE)
+#define BS_CTPR_MS_VIRT_EN_POR_VALUE	(1)
+#define BM_CTPR_MS_VIRT_EN_POR_VALUE	(0x1 << BS_CTPR_MS_VIRT_EN_POR_VALUE)
+#define BS_CTPR_MS_VIRT_EN_INCL		(0)
+#define BM_CTPR_MS_VIRT_EN_INCL		(0x1 << BS_CTPR_MS_VIRT_EN_INCL)
+
+#define BS_CTPR_LS_SPLIT_KEY		(14)
+#define BM_CTPR_LS_SPLIT_KEY		(0x1 << BS_CTPR_LS_SPLIT_KEY)
+#define BS_CTPR_LS_MAN_PROT		(13)
+#define BM_CTPR_LS_MAN_PROT		(0x1 << BS_CTPR_LS_MAN_PROT)
+#define BS_CTPR_LS_DBL_CRC		(12)
+#define BM_CTPR_LS_DBL_CRC		(0x1 << BS_CTPR_LS_DBL_CRC)
+#define BS_CTPR_LS_P3G_LTE		(11)
+#define BM_CTPR_LS_P3G_LTE		(0x1 << BS_CTPR_LS_P3G_LTE)
+#define BS_CTPR_LS_RSA			(10)
+#define BM_CTPR_LS_RSA			(0x1 << BS_CTPR_LS_RSA)
+#define BS_CTPR_LS_MACSEC		(9)
+#define BM_CTPR_LS_MACSEC		(0x1 << BS_CTPR_LS_MACSEC)
+#define BS_CTPR_LS_TLS_PRF		(8)
+#define BM_CTPR_LS_TLS_PRF		(0x1 << BS_CTPR_LS_TLS_PRF)
+#define BS_CTPR_LS_SSL_TLS		(7)
+#define BM_CTPR_LS_SSL_TLS		(0x1 << BS_CTPR_LS_SSL_TLS)
+#define BS_CTPR_LS_IKE			(6)
+#define BM_CTPR_LS_IKE			(0x1 << BS_CTPR_LS_IKE)
+#define BS_CTPR_LS_IPSEC		(5)
+#define BM_CTPR_LS_IPSEC		(0x1 << BS_CTPR_LS_IPSEC)
+#define BS_CTPR_LS_SRTP			(4)
+#define BM_CTPR_LS_SRTP			(0x1 << BS_CTPR_LS_SRTP)
+#define BS_CTPR_LS_WIMAX		(3)
+#define BM_CTPR_LS_WIMAX		(0x1 << BS_CTPR_LS_WIMAX)
+#define BS_CTPR_LS_WIFI			(2)
+#define BM_CTPR_LS_WIFI			(0x1 << BS_CTPR_LS_WIFI)
+#define BS_CTPR_LS_BLOB			(1)
+#define BM_CTPR_LS_BLOB			(0x1 << BS_CTPR_LS_BLOB)
+#define BS_CTPR_LS_KG_DS		(0)
+#define BM_CTPR_LS_KG_DS		(0x1 << BS_CTPR_LS_KG_DS)
+
+/* Secure Memory Version ID */
+#define SMVID_MS	(0x0FD8)
+#define SMVID_LS	(0x0FDC)
+
+#define BS_SMVID_MS_MAX_NPAG	(16)
+#define BM_SMVID_MS_MAX_NPAG	(0x3FF << BS_SMVID_MS_MAX_NPAG)
+#define BS_SMVID_MS_NPRT	(12)
+#define BM_SMVID_MS_NPRT	(0xF << BS_SMVID_MS_NPRT)
+#define BS_SMVID_MS_NPAG	(0)
+#define BM_SMVID_MS_NPAG	(0x3FF << BS_SMVID_MS_NPAG)
+
+#define BS_SMVID_LS_PSIZ	(16)
+#define BM_SMVID_LS_PSIZ	(0x7 << BS_SMVID_LS_PSIZ)
+#define BS_SMVID_LS_SMJV	(8)
+#define BM_SMVID_LS_SMJV	(0xFF << BS_SMVID_LS_SMJV)
+#define BS_SMVID_LS_SMNV	(0)
+#define BM_SMVID_LS_SMNV	(0xFF << BS_SMVID_LS_SMNV)
+
+/* Minimum SM Version ID requiring v2 SM register mapping */
+#define SMVID_V2		(0x0105)
+
+/* RTIC Version ID */
+#define RVID			(0x0FE0)
+
+#define BS_RVID_MD		(27)
+#define BM_RVID_MD		(0x1 << BS_RVID_MD)
+#define BS_RVID_MC		(26)
+#define BM_RVID_MC		(0x1 << BS_RVID_MC)
+#define BS_RVID_MB		(25)
+#define BM_RVID_MB		(0x1 << BS_RVID_MB)
+#define BS_RVID_MA		(24)
+#define BM_RVID_MA		(0x1 << BS_RVID_MA)
+#define BS_RVID_MBL		(20)
+#define BM_RVID_MBL		(0x1 << BS_RVID_MBL)
+#define BS_RVID_SHA_512		(19)
+#define BM_RVID_SHA_512		(0x1 << BS_RVID_SHA_512)
+#define BS_RVID_SHA_256		(17)
+#define BM_RVID_SHA_256		(0x1 << BS_RVID_SHA_256)
+#define BS_RVID_RMJV		(8)
+#define BM_RVID_RMJV		(0xFF << BS_RVID_RMJV)
+#define BS_RVID_RMNV		(0)
+#define BM_RVID_RMNV		(0xFF << BS_RVID_RMNV)
+
+/* CHA Cluster Block Version ID */
+#define CCBVID		(0x0FE4)
+
+#define BS_CCBVID_CAAM_ERA	(24)
+#define BM_CCBVID_CAAM_ERA	(0xFF << BS_CCBVID_CAAM_ERA)
+#define BS_CCBVID_AMJV		(8)
+#define BM_CCBVID_AMJV		(0xFF << BS_CCBVID_AMJV)
+#define BS_CCBVID_AMNV		(0)
+#define BM_CCBVID_AMNV		(0xFF << BS_CCBVID_AMNV)
+
+/* CHA Version ID */
+#define CHAVID_MS	(0x0FE8)
+#define CHAVID_LS	(0x0FEC)
+
+#define BS_CHAVID_MS_JRVID	(28)
+#define BM_CHAVID_MS_JRVID	(0xF << BS_CHAVID_MS_JRVID)
+#define BS_CHAVID_MS_DECOVID	(24)
+#define BM_CHAVID_MS_DEOCVID	(0xF << BS_CHAVID_MS_DECOVID)
+
+#define BS_CHAVID_LS_PKVID	(28)
+#define BM_CHAVID_LS_PKVID	(0xF << BS_CHAVID_LS_PKVID)
+#define BS_CHAVID_LS_RNGVID	(16)
+#define BM_CHAVID_LS_RNGVID	(0xF << BS_CHAVID_LS_RNGVID)
+#define BS_CHAVID_LS_MDVID	(12)
+#define BM_CHAVID_LS_MDVID	(0xF << BS_CHAVID_LS_MDVID)
+#define BS_CHAVID_LS_ARC4VID	(8)
+#define BM_CHAVID_LS_ARC4VID	(0xF << BS_CHAVID_LS_ARC4VID)
+#define BS_CHAVID_LS_DESVID	(4)
+#define BM_CHAVID_LS_DESVID	(0xF << BS_CHAVID_LS_DESVID)
+#define BS_CHAVID_LS_AESVID	(0)
+#define BM_CHAVID_LS_AESVID	(0xF << BS_CHAVID_LS_AESVID)
+
+#define CHAVID_LS_MDVID_LP256	(0x0 << BS_CHAVID_LS_MDVID)
+#define CHAVID_LS_MDVID_LP512	(0x1 << BS_CHAVID_LS_MDVID)
+#define CHAVID_LS_MDVID_MD512	(0x2 << BS_CHAVID_LS_MDVID)
+#define CHAVID_LS_MDVID_HP512	(0x3 << BS_CHAVID_LS_MDVID)
+
+/* CHA Number */
+#define CHANUM_MS	(0x0FF0)
+#define CHANUM_LS	(0x0FF4)
+
+#define BS_CHANUM_MS_JRNUM	(28)
+#define BM_CHANUM_MS_JRNUM	(0xF << BS_CHANUM_MS_JRNUM)
+#define BS_CHANUM_MS_DECONUM	(24)
+#define BM_CHANUM_MS_DECONUM	(0xF << BS_CHANUM_MS_DECONUM)
+#define BS_CHANUM_MS_ZANUM	(12)
+#define BM_CHANUM_MS_ZANUM	(0xF << BS_CHANUM_MS_ZANUM)
+#define BS_CHANUM_MS_ZENUM	(8)
+#define BM_CHANUM_MS_ZENUM	(0xF << BS_CHANUM_MS_ZENUM)
+#define BS_CHANUM_MS_SNW9NUM	(4)
+#define BM_CHANUM_MS_SNW9NUM	(0xF << BS_CHANUM_MS_SNW9NUM)
+#define BS_CHANUM_MS_CRCNUM	(0)
+#define BM_CHANUM_MS_CRCNUM	(0xF << BS_CHANUM_MS_CRCNUM)
+
+#define BS_CHANUM_LS_PKNUM	(28)
+#define BM_CHANUM_LS_PKNUM	(0xF << BS_CHANUM_LS_PKNUM)
+#define BS_CHANUM_LS_KASNUM	(24)
+#define BM_CHANUM_LS_KASNUM	(0xF << BS_CHANUM_LS_KASNUM)
+#define BS_CHANUM_LS_SNW8NUM	(20)
+#define BM_CHANUM_LS_SNW8NUM	(0xF << BS_CHANUM_LS_SNW8NUM)
+#define BS_CHANUM_LS_RNGNUM	(16)
+#define BM_CHANUM_LS_RNGNUM	(0xF << BS_CHANUM_LS_RNGNUM)
+#define BS_CHANUM_LS_MDNUM	(12)
+#define BM_CHANUM_LS_MDNUM	(0xF << BS_CHANUM_LS_MDNUM)
+#define BS_CHANUM_LS_ARC4NUM	(8)
+#define BM_CHANUM_LS_ARC4NUM	(0xF << BS_CHANUM_LS_ARC4NUM)
+#define BS_CHANUM_LS_DESNUM	(4)
+#define BM_CHANUM_LS_DESNUM	(0xF << BS_CHANUM_LS_DESNUM)
+#define BS_CHANUM_LS_AESNUM	(0)
+#define BM_CHANUM_LS_AESNUM	(0xF << BS_CHANUM_LS_AESNUM)
+
+/* CAAM Version ID */
+#define CAAMVID_MS	(0x0FF8)
+#define CAAMVID_LS	(0x0FFC)
+
+#define BS_CAAMVID_MS_IP_ID	(16)
+#define BM_CAAMVID_MS_IP_ID	(0xFFFF << BS_CAAMVID_MS_IP_ID)
+#define BS_CAAMVID_MS_MAJ_REV	(8)
+#define BM_CAAMVID_MS_MAJ_REV	(0xFF << BS_CAAMVID_MS_MAJ_REV)
+#define BS_CAAMVID_MS_MIN_REV	(0)
+#define BM_CAAMVID_MS_MIN_REV	(0xFF << BS_CAAMVID_MS_MIN_REV)
+
+#define BS_CAAMVID_LS_COMPILE_OPT	(24)
+#define BM_CAAMVID_LS_COMPILE_OPT	(0xFF << BS_CAAMVID_LS_COMPILE_OPT)
+#define BS_CAAMVID_LS_INTG_OPT		(16)
+#define BM_CAAMVID_LS_INTG_OPT		(0xFF << BS_CAAMVID_LS_INTG_OPT)
+#define BS_CAAMVID_LS_ECO_REV		(8)
+#define BM_CAAMVID_LS_ECO_REV		(0xFF << BS_CAAMVID_LS_ECO_REV)
+#define BS_CAAMVID_LS_CONFIG_OPT	(0)
+#define BM_CAAMVID_LS_CONFIG_OPT	(0xFF << BS_CAAMVID_LS_CONFIG_OPT)
+
+#endif /* __VERSION_REGS_H__ */
+
diff --git a/core/drivers/caam/intern.h b/core/drivers/caam/intern.h
new file mode 100644
index 00000000..5ae3467a
--- /dev/null
+++ b/core/drivers/caam/intern.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#ifndef __INTERN_H__
+#define __INTERN_H__
+
+void kick_trng(vaddr_t ctrl_base, uint32_t ent_delay);
+
+#endif /* __INTERN_H__ */
+
diff --git a/core/drivers/caam/sub.mk b/core/drivers/caam/sub.mk
new file mode 100644
index 00000000..8a4b6cbd
--- /dev/null
+++ b/core/drivers/caam/sub.mk
@@ -0,0 +1,5 @@
+incdirs-y += include
+
+srcs-y += ctrl.c
+srcs-y += caamrng.c
+
diff --git a/core/drivers/sub.mk b/core/drivers/sub.mk
index b2bcf154..ac058155 100644
--- a/core/drivers/sub.mk
+++ b/core/drivers/sub.mk
@@ -1,3 +1,5 @@
+subdirs-$(CFG_IMX_CAAM) += caam
+
 srcs-$(CFG_CDNS_UART) += cdns_uart.c
 srcs-$(CFG_PL011) += pl011.c
 srcs-$(CFG_TZC400) += tzc400.c