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This adds name GUIDs to the Styx FDFs so that DevicePath references to
its contents (i.e., for the UiApp and Shell UEFI applications) are
emitted unambiguously rather than as MemoryMapped()/ device path nodes,
whose values may change between boots (e.g., if the amount of memory
changes, or if the firmware image is updated).
Having stable boot entries is preferable, given that the generic BDS code
autogenerates entries for the UI app and the shell, but does not clean up
any stale outdated ones that refer to FV files that no longer exist.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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sf command uses MARVELL_SPI_FLASH_PROTOCOL and MARVELL_SPI_MASTER_PROTOCOL.
It allows read/write/erase/update operations on SPI flash.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch add driver for managing Spi flash
It consumes MARVELL_SPI_FLASH_PROTOCOL and enables configuration
by PCD entries.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add MARVELL_SPI_FLASH_PROTOCOL and register containg folder in
Marvell/Marvell.dec in order to make it public.
This protocol contains functions used to manage SPI flash.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Spi master driver implements MARVELL_SPI_MASTER_PROTOCOL.
It configures and manages SPI controller.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add MARVELL_SPI_MASTER_PROTOCOL and register its GUID in Marvell.dec file
in order to make it public.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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'eeprom' command brings MvEeprom driver capabilities to UEFI shell.
It allows reading & writing from/to onboard EEPROM device.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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MvEeprom driver produces MARVELL_EEPROM_PROTOCOL, which can be used by
other drivers or applications. Working EFI_I2C_IO_PROTOCOL is required
by driver to operate.
EEPROM devices' addresses need to be fed via 'PcdEepromI2cAddresses'.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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MvI2cDxe driver was adapted to generic UEFI I2C stack. Connection with
following interfaces was required:
- EFI_I2C_MASTER_PROTOCOL
- EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
- EFI_I2C_ENUMERATE_PROTOCOL
Driver exports configuration options via PCDs. Configurable options
include:
- PcdI2cSlaveAddresses - should contain a list of valid I2C devices'
addresses on bus
- PcdI2cBaseAddresses - physical address of I2C controller registers
- PcdI2cClockFrequency - I2c clock frequency on platform
Drivers of devices on I2C bus should never use EFI_I2C_MASTER_PROTOCOL
directly. Instead, these ought to utilise EFI_I2C_IO_PROTOCOL produced
by generic UEFI stack.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bartosz Szczepanek <bsz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Since PCD tables are byte arrays, it is impossible to provide big values
(e.g. memory addresses) for multiple devices in simple PCD entry. In order
to overcome this, strings may be used.
ParsePcdLib allows parsing PCD string entry.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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- Create Mpp Library, which allows to set MPP on board.
- Create Platforms/Marvell/Marvell.dec file, which holds PCDs' declaration.
- Export configuration capabilities via PCDs.
- Prepare porting guide document
Because GetMppPcd has to be adjusted to possible 8 MPP registers,
although unused, additional PcdChip<X>MppSel are added in order to
satisfy preprocessor demands. For the same reason there are MPP
PCDs for all of 4 possible chips.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch add initial support for Armada70x0 platform. It includes
Armada.dsc.inc and uses Armada70x0.fdf files, which are created with
the aim of support for new boards.
Code currently supports:
- GICv2
- ARM architected timer
- ARM watchdog timer
- UART port
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch adds initial support for Armada70x0 SoC's initialization.
It implements empty mandatory hooks which are currently mostly empty
except for Memory mapping information.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Now that the page table manipulation code has been split off from ArmLib
into ArmMmuLib, we need a resolution for this new library class in all
platforms. For most platforms, this is simply a matter of adding a new
line
ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
to a common [LibraryClass] section.
For D02/D03, which were users of the special PEI_CORE/PEIM implementation
of ArmLib, we drop the reference to this special version from the
[LibraryClasses.PEI_CORE] section (since PEI core does use ArmLib but does
not use the MMU code), and replace the one in [LibraryClasses.PEIM] with
the new ArmMmuPeiLib.inf implementation, which is the new version that
takes care not to issue cache maintenance ops on NOR flash.
In two cases, existing out of tree users of ArmConfigureMmu() need to have
their .inf and #include section updated to add the ArmMmuLib reference.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This commit modifies the name of a structure that is entirely internal
to Platforms/ARM/Juno/AcpiTables/Gtdt.aslc
The name EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES is changed to
GENERIC_TIMER_DESCRIPTION_TABLE.
The name EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES was misleading in
that it appears to be from the standard headers, and caused a bug
where the very similar EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE was
accidentally used instead.
This is only a source name change with no functional modification.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Adjudicated-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This commit fixes a GTDT compilation error
"excess elements in array initializer [-Werror]"
in the EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT() macro
with options in ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h:
Number of Watchdog timers set to 0:
#define JUNO_WATCHDOG_COUNT 0
ACPI tables are based on ACPI 5.1 or later:
//#define ARM_JUNO_ACPI_5_0
This fix also prevents declaration of an ISO C90 non-compliant
zero-length array, causing the error:
"ISO C forbids zero-size array 'Watchdogs'"
when compiled with the "-pedantic" option.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Now that ARM Trusted Firmware has dropped support for the legacy VE memory
map (which means it can only support the FVP Foundation model in GICv3
mode), and runs the GICv3 in native mode by default on the secure side
(which prevents a GICv2 compatible GICv3 from being driven in v2 mode on
the non-secure side), there is little point in keeping the GICv2 legacy
ifdefs in the FVP dsc. So remove them.
Note that we will still be able to support FVP Base in GICv2 mode after
applying this patch, but running it will require a special build of ATF
with FVP_GICV2 defined.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Now that we switched to the .aslc alternatives, these files are no
longer used and can be removed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Switch to the new .aslc description of the ACPI tables. The old .asl
files will be removed in a subsequent patch.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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.asl files can end up being modified to later versions of spec when FADT
is tied to an earlier version. This can cause builds to break
unexpectedly on tools upgrades. Convert to aslc to fix the version of
ACPI in use for this platform to 6.1
Note that this version of the MADT table describes the GIC as a v3,
which is the only version we support for the Foundation model at the
moment (given that its GICv2 lives at a different address than its
FVP Base counterpart)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
[ardb: mention GICv3]
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Without this statement in fdf file ACPI tables defined in aslc files
do not automagically get included in the XSDT.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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The generic PL011 driver has been updated to allow for UARTs on a board
having different clock sources (as is the case on Juno).
See "ArmPlatformPkg: Add support to configure PL011 UART clock"
This change modifies the Juno code to use the new driver options.
By replacing Pl011UartInteger with Pl011UartClKInHz, the driver can be
used with different serial ports. This replaces an erroneous calculated
value with a TRM defined clock rate.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The wrong type name is used in the definition of the GTDT, causing the
header to have an incorrect size value.
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE is changed to
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES to rectify this.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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MADT will now compile with v6.1 fields so we need to bump the FADT to
indicate v6.1 compatability otherwise kernel will fail to parse MADT
correctly and issue the error "No valid GICC entries exist".
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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#if ARM_JUNO_ACPI_5_0
causes the GCC error listed below
k:\edk2\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\Fadt.aslc:76:22:
error: #if with no expression
when ARM_JUNO_ACPI_5_0 is defined in
edk2\ArmPlatformPkg\ArmJunoPkg\Include\ArmPlatform.h:
The problem occurs because the macro is defined but has no value.
The bug is corrected by replacing
#if ARM_JUNO_ACPI_5_0
with
#ifdef ARM_JUNO_ACPI_5_0
This usage is also consistent with that on line 20
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The original SPCR used explicit constants for hardware details.
That made it difficult to readilly adjust the use of serial ports.
This change modifies the explicit constants to use PCDs, so the serial
port usage can be adjusted at build. This can help avoid problems where
sharing ports (e.g. between UEFI trace and host debug) causes fails.
Because the SPCR baud rate selection does not map directly to the PCD
used, a compile time error has been added for baud rates not matching
the SPCR specification. This is beneficial as it is quite difficult
to diagnose an invalid baud rate otherwise.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Amend the Serial Port Console Redirection Table to aslc.
This patch replaces the Spcr.asl file which described the SPCR table
in TDL format with Spcr.aslc which introduces the option of using EDK2
build defined PCDs. Using PCDs will allow for future improvements.
No functional changes are made by this change, it is a preliminary step
towards introducing improvements to allow build time modifications for
bug fixes and improvements.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The DXE module NorFlashAuthenticatedDxe no longer exists upstream, now
that its functionality has been merged into the ordinary NorFlashDxe,
which now supports for non-secure boot and secure boot builds. So replace
all references to it with NorFlashDxe.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
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Enable FDT transfer via UEFI system configuration table; also add D03
specific FDT update library instance to update FDT per platform
information.
FDT support is controlled by FDT_ENABLE build flag and default is no.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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FDT support is controlled by FDT_ENABLE build flag and default is no.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The library will be used to update FDT per platform information gathered
by UEFI, like ethernet MAC address.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Enable Hisilicon D02 platform with features including:
SPI Flash driver
Address map library
Memory initialization PEIM
SEC setting up a simple EL3 exception vector
ARM Trusted Firmware
Early platform configuration PEIM
Other common drivers helping system to boot to UEFI shell
EBL binary
Ramdisk driver (created with 128MB ramdisk)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This adds support for the AMD Seattle based Overdrive and Husky platforms,
and the Lemaker Cello which is derived from it.
This code was tested with upstream EDK2 commit 758ea94651.
The binaries in this branch are based on SeattleFDK 1.0.0.2
(Linaro SeattleFDK commit 4b419f2ef2)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Move to the unicore PrePi implementation. This is possible, since we only
support executing under ATF anyway, so only the boot CPU enters UEFI in
EL2, and booting multiple cores using the ARM_MP_CORE protocol is only
supported when using the LinuxLoader.
The reason we need to make this change is because Juno implements this
protocol using 32-bit wide mailbox registers, which is awkward on an
otherwise 64-bit architecture, and this is holding back progress for
other platforms that need to implement the ACPI parking protocol.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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A PRIORI declarations are evil. They force a driver to be dispatched
before any other drivers, while completely ignoring normal precedence
rules or protocol dependencies.
In this particular case, the DXE version of Pcd.inf is loaded a priori to
work around the problem that the default PcdLib resolution introduces a
a protocol dependency on gPcdProtocolGuid, which provides dynamic PCD
handling for other drivers, and is implemented by Pcd.inf. Since Pcd.inf
depends on PcdLib as well, it can never be dispatched in the ordinary way
if it inherits the default PcdLib resolution (since that will make it depend
on itself), and so it must be made to depend on the Null implementation of
PcdLib explicitly.
So add this explicit override, and drop the A PRIORI declarations.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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Currently, the only supported way of running Tianocore on FVP is using
ARM Trusted Firmware at EL3, in which case only a single core will enter
the UEFI firmware at EL2. This means we can move to the UniCore flavor
of PrePi/PrePeiCore, which now have been made compatible with running
on an otherwise MpCore capable system. So replace the .inf references,
and drop or update the PCDs related to secondary boot as appropriate.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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The PCI Routing Table (_PRT) for Juno does not specify the Interrupt
trigger type and polarity. In the absence of this information, the
kernel uses PCI default interrupt type (level triggered, active low)
which is incompatible with GICv2 compliant interrupt controller such
as on Juno.
Absence of interrupt type leads to errors such as following in kernel
boot log -
[ 1.353696] genirq: Setting trigger mode 8 for irq 9 failed (gic_set_type+0x0/0x5c)
[ 1.478286] genirq: Setting trigger mode 8 for irq 17 failed (gic_set_type+0x0/0x5c)
[ 1.563723] genirq: Setting trigger mode 8 for irq 18 failed (gic_set_type+0x0/0x5c)
Fix this issue by providing the correct information (level triggered,
active high) to the kernel by using the PCI Link device.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The patch corrects Juno LAN9118 base address.
The previous version specified address 0x1a000000, but the TRM documents
it as being located at 0x18000000. Due to the magic of hardware aliasing,
the old version was functional, but let's use the documented value.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The built-in Linux loader is broken in several ways, one of which is that
it shields the UEFI environment from the OS. So remove it from the FVP build.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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