diff options
| author | Heyi Guo <heyi.guo@linaro.org> | 2016-05-30 16:25:46 +0800 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2016-06-17 09:45:56 +0100 |
| commit | b62277bbbea762d2c836fa51148f15ece1b3f417 (patch) | |
| tree | bd5b796a08a9af0a94ac041656f6c7bcee9e09f0 /Platforms | |
| parent | 10007702140441bc4d44186296f068e8ae56769b (diff) | |
Platforms/Hisilicon: add D03 platform
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platforms')
60 files changed, 2990 insertions, 0 deletions
diff --git a/Platforms/Hisilicon/Binary/D03/CustomData.Fv b/Platforms/Hisilicon/Binary/D03/CustomData.Fv Binary files differnew file mode 100644 index 0000000..466b1a8 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/CustomData.Fv diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi Binary files differnew file mode 100644 index 0000000..f125211 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf new file mode 100644 index 0000000..fb29319 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf @@ -0,0 +1,26 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = GetInfoFromBmc
+ FILE_GUID = 43B59C81-9C5F-4021-B0F2-947DB839B781
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = GetBmcInfoDriverEntry
+
+[Binaries]
+ PE32|GetInfoFromBmc.efi|*
+ DXE_DEPEX|GetInfoFromBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi Binary files differnew file mode 100644 index 0000000..cf62305 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf new file mode 100644 index 0000000..91ac33c --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf @@ -0,0 +1,32 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiInterfacePei
+ FILE_GUID = 269702AF-8004-4570-A08E-00762AE65D15
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = IpmiInterfacePeiEntry
+
+[Sources]
+
+[Binaries.AARCH64]
+ TE|IpmiInterfacePei.efi|*
+
+[Depex]
+ TRUE
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.depex b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi Binary files differnew file mode 100644 index 0000000..8352d01 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf new file mode 100644 index 0000000..49ef812 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf @@ -0,0 +1,28 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiInterfaceDxe
+ FILE_GUID = EF5483F8-68AD-4D71-9A23-674D2E9C013E
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+[Binaries.common]
+ PE32|IpmiInterfaceDxe.efi|*
+ DXE_DEPEX|IpmiInterfaceDxe.depex|*
+
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi Binary files differnew file mode 100644 index 0000000..29989b5 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOp.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf new file mode 100644 index 0000000..02618fc --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf @@ -0,0 +1,27 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiMiscOp
+ FILE_GUID = EC68451C-6D10-4ba2-9862-D27D4D6090DB
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = IpmiMiscOpEntry
+
+[Binaries]
+ PE32|IpmiMiscOp.efi|*
+ DXE_DEPEX|IpmiMiscOpDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi Binary files differnew file mode 100644 index 0000000..7528087 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf new file mode 100644 index 0000000..bda12e2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf @@ -0,0 +1,27 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiWatchdogDxe
+ FILE_GUID = 7C7ACA9F-DB25-43FB-A479-1B6E42F38792
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeWatchdogDxeEntry
+
+[Binaries]
+ PE32|IpmiWatchdogDxe.efi|*
+ DXE_DEPEX|IpmiWatchdogDxe.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi Binary files differnew file mode 100644 index 0000000..b898237 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf new file mode 100644 index 0000000..adb115b --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf @@ -0,0 +1,29 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SnpPV600Dxe
+ FILE_GUID = 92D37768-571C-48d9-BEF5-9744AE2FDAF4
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeSnpPV600Driver
+ UNLOAD_IMAGE = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac0.efi|*
+
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi Binary files differnew file mode 100644 index 0000000..c93b96e --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf new file mode 100644 index 0000000..4363d1e --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf @@ -0,0 +1,28 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SnpPV600Dxe
+ FILE_GUID = 3247F150-3612-4803-BD4E-4104D7EF944A
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeSnpPV600Driver
+ UNLOAD_IMAGE = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac1.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi Binary files differnew file mode 100644 index 0000000..de69e98 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf new file mode 100644 index 0000000..7fc67c1 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf @@ -0,0 +1,27 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SnpPV600Dxe
+ FILE_GUID = 3247F153-3612-4803-BD4E-4104D7EF944A
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeSnpPV600Driver
+ UNLOAD_IMAGE = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac4.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi Binary files differnew file mode 100644 index 0000000..007b61f --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf new file mode 100644 index 0000000..ab4120d --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf @@ -0,0 +1,27 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SnpPV600Dxe
+ FILE_GUID = 3246F154-3612-4803-BD4E-4104D7EF944A
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeSnpPV600Driver
+ UNLOAD_IMAGE = SnpPV600Unload
+
+[Binaries]
+ PE32|SnpPV600DxeMac5.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi Binary files differnew file mode 100644 index 0000000..ffe8cc0 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/NativeOhci.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf new file mode 100644 index 0000000..5053ece --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf @@ -0,0 +1,26 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = NativeOhci
+ FILE_GUID = 043D0B5E-DAC1-463a-85BA-2CEDC33A8C4F
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+[Binaries]
+ PE32|NativeOhci.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi Binary files differnew file mode 100644 index 0000000..a49c89f --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf new file mode 100644 index 0000000..52b219d --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf @@ -0,0 +1,25 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ReportPciePlugDidVidToBmc
+ FILE_GUID = 9BC4A5D1-5A46-4A6C-AF11-4875268179D3
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+[Binaries]
+ PE32|ReportPciePlugDidVidToBmc.efi|*
+ DXE_DEPEX|ReportPciePlugDidVidToBmc.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.depex b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi Binary files differnew file mode 100644 index 0000000..d33e7ce --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SFCDriver.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf new file mode 100644 index 0000000..e10275a --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf @@ -0,0 +1,29 @@ +#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SFCDriver
+ FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SFCInitialize
+
+
+
+[Binaries.common]
+ PE32|SFCDriver.efi|*
+ DXE_DEPEX|SFCDriver.depex|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi Binary files differnew file mode 100644 index 0000000..92f2534 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf new file mode 100644 index 0000000..0cb90f7 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf @@ -0,0 +1,28 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SasDriverDxe
+ FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe234567
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = SasDriverInitialize
+
+[Binaries]
+ PE32|SasDriverDxe.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi Binary files differnew file mode 100644 index 0000000..c2c2ef0 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/SmiGraphicsOutput.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf new file mode 100644 index 0000000..a261833 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf @@ -0,0 +1,32 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmiGraphicsOutput
+ FILE_GUID = BFB7B510-B09B-11DB-96E3-005056C00008
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+ PCI_VENDOR_ID = 0x126F
+ PCI_DEVICE_ID = 0x0750
+ PCI_CLASS_CODE = 0x030000
+ PCI_REVISION = 0xA1
+ COMPRESS = TRUE
+
+[Binaries]
+ PE32|SmiGraphicsOutput.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi Binary files differnew file mode 100644 index 0000000..6efc751 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.efi diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf new file mode 100644 index 0000000..f6b966d --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf @@ -0,0 +1,26 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TransSmbiosInfo
+ FILE_GUID = 13668C32-1977-436a-800C-F8644D11CB76
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = TransferSmbiosInfoToBMC
+
+[Binaries]
+ PE32|TransSmbiosInfo.efi|*
+ DXE_DEPEX|TransSmbiosInfo.depex|*
diff --git a/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi Binary files differnew file mode 100644 index 0000000..266d8ea --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.efi diff --git a/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf new file mode 100644 index 0000000..5bc73c2 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf @@ -0,0 +1,32 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Ebl
+ FILE_GUID = 3CEF354A-3B7A-4519-AD70-72A134698311
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 1.0
+ ENTRY_POINT = EdkBootLoaderEntry
+
+[Binaries.common]
+ PE32|Ebl.efi|*
+
diff --git a/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib Binary files differnew file mode 100644 index 0000000..77d8023 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2P.lib diff --git a/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf new file mode 100644 index 0000000..9de7cdf --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf @@ -0,0 +1,44 @@ +#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OemAddressMap2P
+ FILE_GUID = 32BC48E3-5428-4556-A383-25A23EA816A7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OemAddressMapLib
+
+[Sources.common]
+
+[Binaries.AARCH64]
+ LIB|OemAddressMap2P.lib|*
+
+[Sources.AARCH64.GCC]
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ CpldIoLib
+[BuildOptions]
+
+[FixedPcd]
+ gHisiTokenSpaceGuid.PcdNORFlashBase
+
diff --git a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi Binary files differnew file mode 100644 index 0000000..cf6bb92 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInit.efi diff --git a/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf new file mode 100644 index 0000000..c221de9 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf @@ -0,0 +1,33 @@ +#/** @file
+#
+# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Based on the files under ArmPlatformPkg/MemoryInitPei/
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MemoryInit
+ FILE_GUID = c61ef796-b50d-4f98-9f78-4f6f79d800d5
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeMemory
+
+[Sources]
+
+[Binaries.AARCH64]
+ TE|MemoryInit.efi|*
+
+[Depex]
+ TRUE
diff --git a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv Binary files differnew file mode 100644 index 0000000..1050b92 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv diff --git a/Platforms/Hisilicon/Binary/D03/bl1.bin b/Platforms/Hisilicon/Binary/D03/bl1.bin Binary files differnew file mode 100644 index 0000000..3d57440 --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/bl1.bin diff --git a/Platforms/Hisilicon/Binary/D03/fip.bin b/Platforms/Hisilicon/Binary/D03/fip.bin Binary files differnew file mode 100644 index 0000000..94b2c2e --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/fip.bin diff --git a/Platforms/Hisilicon/D03/D03.dec b/Platforms/Hisilicon/D03/D03.dec new file mode 100644 index 0000000..8b08a32 --- /dev/null +++ b/Platforms/Hisilicon/D03/D03.dec @@ -0,0 +1,44 @@ +#/** @file
+#
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#
+# D03 Package
+#
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = D03Pkg
+ PACKAGE_GUID = D42C5D53-63FA-4FBA-9FD4-E8EA684FD3BE
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+
+[Ppis]
+
+[Protocols]
+
+[Guids]
+
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild]
+
+[PcdsFeatureFlag]
+
+
diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc new file mode 100644 index 0000000..9598404 --- /dev/null +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -0,0 +1,540 @@ +#
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = D03
+ PLATFORM_GUID = e5003abd-8809-6194-ac3d-a6a99ff52478
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
+ DEFINE EDK2_SKIP_PEICORE=0
+ DEFINE INCLUDE_TFTP_COMMAND=1
+
+!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.dsc.inc
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
+
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+ NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+ LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+
+
+ I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+ IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
+
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+
+
+ CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+
+ SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.inf
+
+ EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
+ RealTimeClockLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+
+ OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
+ OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
+ PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+ PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ # USB Requirements
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
+ SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+ ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf
+
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
+ SerialPortLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf
+
+[BuildOptions]
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Include
+
+[BuildOptions.AARCH64.EDKII.UEFI_APPLICATION]
+ GCC:*_*_*_CC_FLAGS = -mcmodel=small -falign-functions=16
+ GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 --sort-section=alignment
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03"
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+
+ # Stacks for MPCores in Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x81000000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
+
+ # Stacks for MPCores in Monitor Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x8100FF00
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x81000000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
+
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+
+
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
+
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
+
+ gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
+
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+ #
+ # ARM PrimeCell
+ #
+
+
+ gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
+
+
+ gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x7 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3
+
+ ## SP805 Watchdog - Motherboard Watchdog
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
+
+ ## Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2F8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+ gHisiTokenSpaceGuid.PcdUartClkInHz|1846100
+
+ gHisiTokenSpaceGuid.PcdSerialPortSendDelay|10000000
+
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+
+ gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+ gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Estuary v2.2 D03 UEFI"
+
+ gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
+
+ gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
+
+ gHisiTokenSpaceGuid.PcdSystemProductName|L"D03"
+ gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
+ gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D03"
+ gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
+
+ gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1612"
+
+ #
+ # ARM PL390 General Interrupt Controller
+ #
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
+
+ #
+ # ARM OS Loader
+ #
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SATA"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"EFI\GRUB2\grubaa64.efi"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000
+
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+ gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
+ gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
+
+ gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
+
+ gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
+ gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
+
+
+ gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
+
+
+ gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
+
+
+ gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
+
+ gHisiTokenSpaceGuid.FdtFileAddress|0xA47C0000
+
+ gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
+
+ gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
+
+ gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
+
+ gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x2000000000
+
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
+
+ gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
+
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xB0000000
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x8000000
+
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xB0000000
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
+
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
+
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xAC000000
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x4000000
+
+ gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
+ gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
+ gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
+ gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xb2000000
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0x5feffff
+
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xb8000000
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0x5feffff
+
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xaa000000
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x5feffff
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xB2000000
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xB8000000
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xAA000000
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xb7ff0000
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xbdff0000
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xAfff0000
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
+
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
+
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
+
+ gHisiTokenSpaceGuid.Pcdsoctype|0x1610
+ ## SP804 DualTimer
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0xb0
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x40060000
+ ## TODO: need to confirm the base for Performance and Metronome base for PV660
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000
+
+ gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress|0xc6010040
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # SEC
+ #
+
+ #
+ # PEI Phase modules
+ #
+!if $(EDK2_SKIP_PEICORE) == 1
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+ ArmPlatformPkg/PrePi/PeiUniCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+!else
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+!endif
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf
+
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+ <LibraryClasses>
+ CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
+ }
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ # Simple TextIn/TextOut for UEFI Terminal
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+ ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+ #
+ #ACPI
+ #
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # Usb Support
+ #
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
+
+ #
+ #network
+ #
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+
+ OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf
+ MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+ #PCIe Support
+ OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+ OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <LibraryClasses>
+ NULL|OpenPlatformPkg/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf
+ }
+
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf
+
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+
+ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+ #
+ # Memory test
+ #
+ MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
+
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+!ifdef $(INCLUDE_DP)
+ NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf new file mode 100644 index 0000000..373b173 --- /dev/null +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -0,0 +1,349 @@ +#
+# Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
+# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[DEFINES]
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.D03]
+BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+
+Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00010000
+NumBlocks = 0x30
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv
+
+0x00040000|0x001C0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+0x00200000|0x00020000
+gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/bl1.bin
+0x00220000|0x00020000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/fip.bin
+
+0x002D0000|0x0000E000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x20000
+ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
+ 0xB8, 0xdF, 0x00, 0x00,
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002DE000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+ 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002E0000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+0x002F0000|0x00010000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ APRIORI DXE {
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ }
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/SFC/SfcDxeDriver.inf
+
+ INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ # Simple TextIn/TextOut for UEFI Terminal
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+
+ #
+ # Usb Support
+ #
+
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/OhciDxe/OhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+ #
+ #ACPI
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/AcpiTablesHi1610.inf
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ #Network
+ #
+
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+ #
+ # PCI Support
+ #
+ INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+ # VGA Driver
+ #
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf
+
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Ebl/Ebl.inf
+
+ #
+ # Build Shell from latest source code instead of prebuilt binary
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+!else
+ APRIORI PEI {
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ }
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF OpenPlatformPkg/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
+
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.fdf.inc
+
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h new file mode 100644 index 0000000..46c77d3 --- /dev/null +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h @@ -0,0 +1,40 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __OEM_NIC_CONFIG_H__
+#define __OEM_NIC_CONFIG_H__
+
+#define I2C_SLAVEADDR_EEPROM (0x52)
+
+#define I2C_OFFSET_EEPROM_ETH0 (0xc00)
+#define I2C_OFFSET_EEPROM_ETH1 (I2C_OFFSET_EEPROM_ETH0 + 6)
+#define I2C_OFFSET_EEPROM_ETH2 (I2C_OFFSET_EEPROM_ETH1 + 6)
+#define I2C_OFFSET_EEPROM_ETH3 (I2C_OFFSET_EEPROM_ETH2 + 6)
+#define I2C_OFFSET_EEPROM_ETH4 (I2C_OFFSET_EEPROM_ETH3 + 6)
+#define I2C_OFFSET_EEPROM_ETH5 (I2C_OFFSET_EEPROM_ETH4 + 6)
+#define I2C_OFFSET_EEPROM_ETH6 (I2C_OFFSET_EEPROM_ETH5 + 6)
+#define I2C_OFFSET_EEPROM_ETH7 (I2C_OFFSET_EEPROM_ETH6 + 6)
+
+#define MAC_ADDR_LEN 6
+
+#pragma pack(1)
+typedef struct {
+ UINT16 Crc16;
+ UINT16 MacLen;
+ UINT8 Mac[MAC_ADDR_LEN];
+} NIC_MAC_ADDRESS;
+#pragma pack()
+
+#endif
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c new file mode 100644 index 0000000..994ed6a --- /dev/null +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -0,0 +1,321 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/HisiBoardNicProtocol.h>
+#include <OemNicConfig.h>
+#include <Library/CpldIoLib.h>
+
+#include <Library/I2CLib.h>
+
+#define EEPROM_I2C_PORT 6
+
+EFI_STATUS
+EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS
+EFIAPI OemSetMac2P (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr);
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr);
+
+volatile unsigned char g_2pserveraddr[4][6] =
+{
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x00},
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x01},
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x02},
+ {0x00, 0x18, 0x16, 0x29, 0x11, 0x03}
+};
+
+UINT16 crc_tab[256] = {
+ 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
+ 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
+ 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
+ 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
+ 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
+ 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
+ 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
+ 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
+ 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
+ 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
+ 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
+ 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
+ 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
+ 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
+ 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
+ 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
+ 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
+ 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
+ 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+ 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
+ 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
+ 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+ 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
+ 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
+ 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
+ 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
+ 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
+ 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
+ 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
+ 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
+ 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
+ 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0,
+};
+
+UINT16 make_crc_checksum(UINT8 *buf, UINT32 len)
+{
+ UINT16 StartCRC = 0;
+
+ if (len > (512 * 1024))
+ {
+ return 0;
+ }
+
+ if (NULL == buf)
+ {
+ return 0;
+ }
+
+ while (len)
+ {
+ StartCRC = crc_tab[((UINT8)((StartCRC >> 8) & 0xff)) ^ *(buf++)] ^ ((UINT16)(StartCRC << 8));
+ len--;
+ }
+
+ return StartCRC;
+}
+
+
+EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr)
+{
+ I2C_DEVICE stI2cDev = {0};
+ EFI_STATUS Status;
+ UINT16 I2cOffset;
+ UINT16 crc16;
+ NIC_MAC_ADDRESS stMacDesc = {0};
+
+ Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS));
+
+ stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+ stI2cDev.Port = EEPROM_I2C_PORT;
+ stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+ stI2cDev.Socket = 0;
+ Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + sizeof(stMacDesc.Mac));
+ if ((crc16 != stMacDesc.Crc16) || (0 == crc16))
+ {
+ return EFI_NOT_FOUND;
+ }
+
+ gBS->CopyMem((VOID *)(pucAddr), (VOID *)(stMacDesc.Mac), MAC_ADDR_LEN);
+
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr)
+{
+ I2C_DEVICE stI2cDev = {0};
+ EFI_STATUS Status;
+ UINT16 I2cOffset;
+ NIC_MAC_ADDRESS stMacDesc = {0};
+
+
+ stMacDesc.MacLen = MAC_ADDR_LEN;
+ gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN);
+
+ stMacDesc.Crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN);
+
+ Status = I2CInit(0, EEPROM_I2C_PORT, Normal);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS));
+
+ stI2cDev.DeviceType = DEVICE_TYPE_E2PROM;
+ stI2cDev.Port = EEPROM_I2C_PORT;
+ stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
+ stI2cDev.Socket = 0;
+ Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemGetMac2P (
+ IN OUT EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ )
+{
+ EFI_STATUS Status;
+
+ if (NULL == Mac)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = OemGetMacE2prom(Port, Mac->Addr);
+ if ((EFI_ERROR(Status)))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Get mac failed!\n", __FUNCTION__, __LINE__));
+
+ Mac->Addr[0] = 0x00;
+ Mac->Addr[1] = 0x18;
+ Mac->Addr[2] = 0x82;
+ Mac->Addr[3] = 0x2F;
+ Mac->Addr[4] = 0x02;
+ Mac->Addr[5] = Port;
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI OemSetMac2P (
+ IN EFI_MAC_ADDRESS *Mac,
+ IN UINTN Port
+ )
+{
+ EFI_STATUS Status;
+
+ if (NULL == Mac)
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = OemSetMacE2prom(Port, Mac->Addr);
+ if ((EFI_ERROR(Status)))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+HISI_BOARD_NIC_PROTOCOL mHisiBoardNicProtocol2P = {
+ .GetMac = OemGetMac2P,
+ .SetMac = OemSetMac2P,
+};
+
+VOID OemFeedbackXGeStatus(BOOLEAN IsLinkup, BOOLEAN IsActOK, UINT32 port)
+{
+ UINT8 CpldValue = 0;
+ UINTN RegOffset = 0x10 + (UINTN)port * 4;
+
+ if (port > 2)
+ {
+ return;
+ }
+
+ if (IsLinkup)
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue |= BIT2;
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+ else
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue &= ~((UINT8)BIT2);
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+
+ if (IsActOK)
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue |= BIT4;
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+ else
+ {
+ CpldValue = ReadCpldReg(RegOffset);
+ CpldValue &= ~((UINT8)BIT4);
+ WriteCpldReg(RegOffset, CpldValue);
+ }
+}
+
+HISI_BOARD_XGE_STATUS_PROTOCOL mHisiBoardXgeStatusProtocol2p = {
+ .FeedbackXgeStatus = OemFeedbackXGeStatus,
+};
+
+
+EFI_STATUS
+EFIAPI
+OemNicConfigEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->InstallProtocolInterface(
+ &ImageHandle,
+ &gHisiBoardNicProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mHisiBoardNicProtocol2P
+ );
+
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ Status = gBS->InstallProtocolInterface(
+ &ImageHandle,
+ &gHisiBoardXgeStatusProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mHisiBoardXgeStatusProtocol2p
+ );
+
+ if(EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf new file mode 100644 index 0000000..4327406 --- /dev/null +++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -0,0 +1,51 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OemNicConfigPangea
+ FILE_GUID = 3A23A929-1F38-4d04-8A01-38AD993EB2CE
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = OemNicConfigEntry
+
+[Sources.common]
+ OemNicConfig2P.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[Protocols]
+ gHisiBoardNicProtocolGuid ##Produce
+ gHisiBoardXgeStatusProtocolGuid
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ DebugLib
+ IoLib
+ TimerLib
+ I2CLib
+ PcdLib
+
+[FixedPcd]
+
+[Depex]
+ TRUE
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c new file mode 100644 index 0000000..8bfac2d --- /dev/null +++ b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c @@ -0,0 +1,437 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/PciPlatform.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/MemoryAllocationLib.h>
+
+//
+// Global variables for Option ROMs
+//
+#define NULL_ROM_FILE_GUID \
+ { \
+ 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} \
+ }
+
+#define SAS_OPTION_ROM_FILE_GUID \
+{ 0xb47533c7, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xdb}}
+
+#define SAS3108_OPTION_ROM_FILE_GUID \
+{ 0xb47533c8, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xd8}}
+
+#define INVALID 0xBD
+
+
+typedef struct {
+ EFI_HANDLE PciPlatformHandle;
+ EFI_PCI_PLATFORM_PROTOCOL PciPlatform;
+} PCI_PLATFORM_PRIVATE_DATA;
+
+
+#define MAX_ROM_NUMBER 2
+
+
+typedef struct {
+ EFI_GUID FileName;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+} PCI_OPTION_ROM_TABLE;
+
+typedef struct {
+ UINTN RomSize;
+ VOID *RomBase;
+} OPTION_ROM_INFO;
+
+PCI_PLATFORM_PRIVATE_DATA *mPciPrivateData = NULL;
+
+PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = {
+ {
+ SAS_OPTION_ROM_FILE_GUID,
+ 0,
+ 2,
+ 0,
+ 0,
+ 0x1000,
+ 0x0097
+ },
+ {
+ SAS3108_OPTION_ROM_FILE_GUID,
+ 0,
+ 1,
+ 0,
+ 0,
+ 0x1000,
+ 0x005D
+ },
+
+ //
+ // End of OptionROM Entries
+ //
+ {
+ NULL_ROM_FILE_GUID, // Guid
+ 0, // Segment
+ 0, // Bus Number
+ 0, // Device Number
+ 0, // Function Number
+ 0xffff, // Vendor ID
+ 0xffff // Device ID
+ }
+};
+
+EFI_STATUS
+EFIAPI
+GetPlatformPolicy (
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
+ )
+/*++
+
+Routine Description:
+
+ Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS.
+
+Arguments:
+
+ This - The pointer to the Protocol itself.
+ PciPolicy - the returned Policy.
+
+Returns:
+
+ EFI_UNSUPPORTED - Function not supported.
+ EFI_INVALID_PARAMETER - Invalid PciPolicy value.
+
+--*/
+{
+ if (PciPolicy == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+GetRawImage (
+ IN EFI_GUID *NameGuid,
+ IN OUT VOID **Buffer,
+ IN OUT UINTN *Size
+ )
+/*++
+
+Routine Description:
+
+ Get an indicated image in raw sections.
+
+Arguments:
+
+ NameGuid - NameGuid of the image to get.
+ Buffer - Buffer to store the image get.
+ Size - size of the image get.
+
+Returns:
+
+ EFI_NOT_FOUND - Could not find the image.
+ EFI_LOAD_ERROR - Error occurred during image loading.
+ EFI_SUCCESS - Image has been successfully loaded.
+
+--*/
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINT32 AuthenticationStatus;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status) || HandleCount == 0) {
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Find desired image in all Fvs
+ //
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **)&Fv
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_LOAD_ERROR;
+ }
+ //
+ // Try a raw file
+ //
+ *Buffer = NULL;
+ *Size = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ NameGuid,
+ EFI_SECTION_RAW,
+ 0,
+ Buffer,
+ Size,
+ &AuthenticationStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ break;
+ }
+ }
+
+ if (Index >= HandleCount) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+GetPciRom (
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE PciHandle,
+ OUT VOID **RomImage,
+ OUT UINTN *RomSize
+ )
+/*++
+
+Routine Description:
+
+ Return a PCI ROM image for the onboard device represented by PciHandle.
+
+Arguments:
+
+ This - Protocol instance pointer.
+ PciHandle - PCI device to return the ROM image for.
+ RomImage - PCI Rom Image for onboard device.
+ RomSize - Size of RomImage in bytes.
+
+Returns:
+
+ EFI_SUCCESS - RomImage is valid.
+ EFI_NOT_FOUND - No RomImage.
+
+--*/
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINTN TableIndex;
+ UINTN RomImageNumber;
+ OPTION_ROM_INFO OptionRominfo[MAX_ROM_NUMBER];
+
+ Status = gBS->HandleProtocol (
+ PciHandle,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, 1, &VendorId);
+ (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_DEVICE_ID_OFFSET, 1, &DeviceId);
+
+ //
+ // Loop through table of video option rom descriptions
+ //
+ RomImageNumber = 0;
+ for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) {
+ //
+ // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable
+ //
+ if ((VendorId != mPciOptionRomTable[TableIndex].VendorId)
+ || (DeviceId != mPciOptionRomTable[TableIndex].DeviceId)
+ )
+ {
+ continue;
+ }
+
+ Status = GetRawImage (
+ &mPciOptionRomTable[TableIndex].FileName,
+ &(OptionRominfo[RomImageNumber].RomBase),
+ &(OptionRominfo[RomImageNumber].RomSize)
+ );
+
+ if (EFI_ERROR (Status)) {
+ continue;
+ } else {
+ RomImageNumber++;
+ if (RomImageNumber == MAX_ROM_NUMBER) {
+ break;
+ }
+ }
+ }
+
+ if (RomImageNumber == 0) {
+
+ return EFI_NOT_FOUND;
+
+ } else {
+ *RomImage = OptionRominfo[RomImageNumber - 1].RomBase;
+ *RomSize = OptionRominfo[RomImageNumber - 1].RomSize;
+
+ if (RomImageNumber > 1) {
+ //
+ // More than one OPROM have been found!
+ //
+
+ }
+
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformPrepController (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_HANDLE RootBridge,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ The PlatformPrepController() function can be used to notify the platform driver so that
+ it can perform platform-specific actions. No specific actions are required.
+ Several notification points are defined at this time. More synchronization points may be
+ added as required in the future. The PCI bus driver calls the platform driver twice for
+ every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
+ is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
+ been notified.
+ This member function may not perform any error checking on the input parameters. It also
+ does not return any error codes. If this member function detects any error condition, it
+ needs to handle those errors on its own because there is no way to surface any errors to
+ the caller.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ RootBridge - The associated PCI root bridge handle.
+ PciAddress - The address of the PCI device on the PCI bus.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - The function completed successfully.
+ EFI_UNSUPPORTED - Not supported.
+
+--*/
+{
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PhaseNotify (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ Perform initialization by the phase indicated.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - Must return with success.
+
+--*/
+{
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciPlatformDriverEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+/*++
+
+Routine Description:
+ Main Entry point of the Pci Platform Driver.
+
+Arguments:
+
+ ImageHandle - Handle to the image.
+ SystemTable - Handle to System Table.
+
+Returns:
+
+ EFI_STATUS - Status of the function calling.
+
+--*/
+{
+ EFI_STATUS Status;
+ PCI_PLATFORM_PRIVATE_DATA *PciPrivateData;
+
+ PciPrivateData = AllocateZeroPool (sizeof (PCI_PLATFORM_PRIVATE_DATA));
+ mPciPrivateData = PciPrivateData;
+
+ mPciPrivateData->PciPlatform.PlatformNotify = PhaseNotify;
+ mPciPrivateData->PciPlatform.PlatformPrepController = PlatformPrepController;
+ mPciPrivateData->PciPlatform.GetPlatformPolicy = GetPlatformPolicy;
+ mPciPrivateData->PciPlatform.GetPciRom = GetPciRom;
+
+ //
+ // Install on a new handle
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mPciPrivateData->PciPlatformHandle,
+ &gEfiPciPlatformProtocolGuid,
+ &mPciPrivateData->PciPlatform,
+ NULL
+ );
+
+ return Status;
+}
diff --git a/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h new file mode 100644 index 0000000..a89f7c6 --- /dev/null +++ b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h @@ -0,0 +1,180 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PCI_PLATFORM_H_
+#define PCI_PLATFORM_H_
+
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/PciPlatform.h>
+
+
+//
+// Global variables for Option ROMs
+//
+#define NULL_ROM_FILE_GUID \
+ { \
+ 0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 \
+ }
+
+
+typedef struct {
+ EFI_GUID FileName;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+} PCI_OPTION_ROM_TABLE;
+
+#define INVALID 0xBD
+
+
+typedef struct {
+ EFI_HANDLE PciPlatformHandle;
+ EFI_PCI_PLATFORM_PROTOCOL PciPlatform;
+} PCI_PLATFORM_PRIVATE_DATA;
+
+
+
+extern PCI_PLATFORM_PRIVATE_DATA mPciPrivateData;
+
+EFI_STATUS
+EFIAPI
+PhaseNotify (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ Perform initialization by the phase indicated.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - Must return with success.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+PlatformPrepController (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_HANDLE RootBridge,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+/*++
+
+Routine Description:
+
+ The PlatformPrepController() function can be used to notify the platform driver so that
+ it can perform platform-specific actions. No specific actions are required.
+ Several notification points are defined at this time. More synchronization points may be
+ added as required in the future. The PCI bus driver calls the platform driver twice for
+ every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
+ is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
+ been notified.
+ This member function may not perform any error checking on the input parameters. It also
+ does not return any error codes. If this member function detects any error condition, it
+ needs to handle those errors on its own because there is no way to surface any errors to
+ the caller.
+
+Arguments:
+
+ This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ HostBridge - The associated PCI host bridge handle.
+ RootBridge - The associated PCI root bridge handle.
+ PciAddress - The address of the PCI device on the PCI bus.
+ Phase - The phase of the PCI controller enumeration.
+ ChipsetPhase - Defines the execution phase of the PCI chipset driver.
+
+Returns:
+
+ EFI_SUCCESS - The function completed successfully.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+GetPlatformPolicy (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
+ )
+/*++
+
+Routine Description:
+
+ Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS.
+
+Arguments:
+
+ This - The pointer to the Protocol itself.
+ PciPolicy - the returned Policy.
+
+Returns:
+
+ EFI_UNSUPPORTED - Function not supported.
+ EFI_INVALID_PARAMETER - Invalid PciPolicy value.
+
+--*/
+;
+
+EFI_STATUS
+EFIAPI
+GetPciRom (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE PciHandle,
+ OUT VOID **RomImage,
+ OUT UINTN *RomSize
+ )
+/*++
+
+Routine Description:
+
+ Return a PCI ROM image for the onboard device represented by PciHandle.
+
+Arguments:
+
+ This - Protocol instance pointer.
+ PciHandle - PCI device to return the ROM image for.
+ RomImage - PCI Rom Image for onboard device.
+ RomSize - Size of RomImage in bytes.
+
+Returns:
+
+ EFI_SUCCESS - RomImage is valid.
+ EFI_NOT_FOUND - No RomImage.
+
+--*/
+;
+
+#endif
diff --git a/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf new file mode 100644 index 0000000..6d1b085 --- /dev/null +++ b/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf @@ -0,0 +1,53 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PciPlatform
+ FILE_GUID = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciPlatformDriverEntry
+
+[sources.common]
+ PciPlatform.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiLib
+ BaseLib
+ DebugLib
+ ArmLib
+ IoLib
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiPciPlatformProtocolGuid
+ gEfiFirmwareVolume2ProtocolGuid
+ gEfiPciIoProtocolGuid
+
+[Pcd]
+
+[FixedPcd]
+
+[Depex]
+ TRUE
+
diff --git a/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c new file mode 100644 index 0000000..97cf6b8 --- /dev/null +++ b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c @@ -0,0 +1,180 @@ +/** @file
+*
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/CacheMaintenanceLib.h>
+
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+#include <Library/OemMiscLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/ArmLib.h>
+
+#define PERI_SUBCTRL_BASE (0x40000000)
+#define MDIO_SUBCTRL_BASE (0x60000000)
+#define PCIE2_SUBCTRL_BASE (0xA0000000)
+#define PCIE0_SUBCTRL_BASE (0xB0000000)
+#define ALG_BASE (0xD0000000)
+
+#define SC_BROADCAST_EN_REG (0x16220)
+#define SC_BROADCAST_SCL1_ADDR0_REG (0x16230)
+#define SC_BROADCAST_SCL1_ADDR1_REG (0x16234)
+#define SC_BROADCAST_SCL2_ADDR0_REG (0x16238)
+#define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C)
+#define SC_BROADCAST_SCL3_ADDR0_REG (0x16240)
+#define SC_BROADCAST_SCL3_ADDR1_REG (0x16244)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200)
+#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0)
+#define SC_TM_CLKEN0_REG (0x2050)
+
+#define SC_TM_CLKEN0_REG_VALUE (0x3)
+#define SC_BROADCAST_EN_REG_VALUE (0x7)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400)
+#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e)
+
+VOID PlatformTimerStart (VOID)
+{
+ // Timer0 clock enable
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE);
+}
+
+void QResetAp(VOID)
+{
+ MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
+ (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
+ ArmDataSynchronizationBarrier ();
+ ArmInstructionSynchronizationBarrier ();
+
+ //SCCL A
+ if (!PcdGet64 (PcdTrustedFirmwareEnable))
+ {
+ StartupAp();
+ }
+}
+
+
+EFI_STATUS
+EFIAPI
+EarlyConfigEntry (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
+ (VOID)SmmuConfigForOS();
+ DEBUG((EFI_D_INFO,"Done\n"));
+
+
+ DEBUG((EFI_D_INFO,"AP CONFIG........."));
+ (VOID)QResetAp();
+ DEBUG((EFI_D_INFO,"Done\n"));
+
+ DEBUG((EFI_D_INFO,"MN CONFIG........."));
+ (VOID)MN_CONFIG();
+ DEBUG((EFI_D_INFO,"Done\n"));
+
+ if(OemIsMpBoot())
+ {
+ DEBUG((EFI_D_INFO,"Event Broadcast CONFIG........."));
+ //EVENT broadcast
+ MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+ MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+ MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+ MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+ MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+ MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+ MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+ MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+
+ MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+ MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+ MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+ MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+ MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+ MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+ MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+
+ MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
+ MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+ MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+ MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
+ MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
+ MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
+ MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
+
+ DEBUG((EFI_D_INFO,"Done\n"));
+ }
+
+ DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG........."));
+
+ if(OemIsMpBoot())
+ {
+ MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0);
+ MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
+ MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1);
+ MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0);
+ MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1);
+ }
+
+ else
+ {
+ MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0);
+ MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2);
+ MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0);
+ MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
+ MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0);
+ }
+
+ DEBUG((EFI_D_INFO,"Done\n"));
+
+ MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE);
+
+ DEBUG((EFI_D_INFO,"Timer CONFIG........."));
+ PlatformTimerStart ();
+ DEBUG((EFI_D_INFO,"Done\n"));
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf new file mode 100644 index 0000000..cd6b964 --- /dev/null +++ b/Platforms/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf @@ -0,0 +1,55 @@ +#/** @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = EarlyConfigPeimD03
+ FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = EarlyConfigEntry
+
+[Sources.common]
+ EarlyConfigPeimD03.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+ ArmPkg/ArmPkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PcdLib
+ DebugLib
+ IoLib
+ CacheMaintenanceLib
+
+ PlatformSysCtrlLib
+ ArmLib
+
+[Pcd]
+ gHisiTokenSpaceGuid.PcdMailBoxAddress
+ gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+ gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
+
+[Depex]
+## As we will clean mailbox in this module, need to wait memory init complete
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000..5ce7731 --- /dev/null +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,131 @@ +/** @file
+
+ Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+ /* Port 0 */
+ {
+ PCI_HB0RB0_ECAM_BASE, //ecam
+ 0, //BusBase
+ 31, //BusLimit
+ PCI_HB0RB0_PCIREGION_BASE, //Membase
+ PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
+ PCI_HB0RB0_IO_BASE, //IoBase
+ (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+ PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
+ PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
+ (PCI_HB0RB0_PCI_BASE) //RbPciBar
+ },
+ /* Port 1 */
+ {
+ PCI_HB0RB1_ECAM_BASE,//ecam
+ 224, //BusBase
+ 254, //BusLimit
+ PCI_HB0RB1_PCIREGION_BASE, //Membase
+ PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
+ (PCI_HB0RB1_IO_BASE), //IoBase
+ (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
+ PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
+ PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
+ (PCI_HB0RB1_PCI_BASE) //RbPciBar
+ },
+ /* Port 2 */
+ {
+ PCI_HB0RB2_ECAM_BASE,
+ 128, //BusBase
+ 159, //BusLimit
+ PCI_HB0RB2_PCIREGION_BASE ,//MemBase
+ PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
+ (PCI_HB0RB2_IO_BASE), //IOBase
+ (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
+ PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
+ PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
+ (PCI_HB0RB2_PCI_BASE) //RbPciBar
+ },
+
+ /* Port 3 */
+ {
+ PCI_HB0RB3_ECAM_BASE,
+ 96, //BusBase
+ 127, //BusLimit
+ (PCI_HB0RB3_ECAM_BASE), //MemBase
+ (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB0RB3_PCI_BASE) //RbPciBar
+ }
+ },
+{// HostBridge 1
+ /* Port 0 */
+ {
+ PCI_HB1RB0_ECAM_BASE,
+ 128, //BusBase
+ 159, //BusLimit
+ (PCI_HB1RB0_ECAM_BASE), //MemBase
+ (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB0_PCI_BASE) //RbPciBar
+ },
+ /* Port 1 */
+ {
+ PCI_HB1RB1_ECAM_BASE,
+ 160, //BusBase
+ 191, //BusLimit
+ (PCI_HB1RB1_ECAM_BASE), //MemBase
+ (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB1_PCI_BASE) //RbPciBar
+ },
+ /* Port 2 */
+ {
+ PCI_HB1RB2_ECAM_BASE,
+ 192, //BusBase
+ 223, //BusLimit
+ (PCI_HB1RB2_ECAM_BASE), //MemBase
+ (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB2_PCI_BASE) //RbPciBar
+ },
+
+ /* Port 3 */
+ {
+ PCI_HB1RB3_ECAM_BASE,
+ 224, //BusBase
+ 255, //BusLimit
+ (PCI_HB1RB3_ECAM_BASE), //MemBase
+ (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
+ (0), //IoBase
+ (0), //IoLimit
+ 0,
+ 0,
+ (PCI_HB1RB3_PCI_BASE) //RbPciBar
+ }
+ }
+};
+
diff --git a/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000..5040a04 --- /dev/null +++ b/Platforms/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,76 @@ +## @file
+#
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformPciLib
+ FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+
+[Sources]
+ PlatformPciLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ PcdLib
+
+[FixedPcd]
+ gHisiTokenSpaceGuid.PcdHb1BaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+ gHisiTokenSpaceGuid.PciHb0Rb0Base
+ gHisiTokenSpaceGuid.PciHb0Rb1Base
+ gHisiTokenSpaceGuid.PciHb0Rb2Base
+ gHisiTokenSpaceGuid.PciHb0Rb3Base
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+ gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+
+ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+ gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+
|