diff options
| author | Leo Duran <leo.duran@amd.com> | 2015-08-20 13:30:24 -0500 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2016-06-02 16:41:45 +0100 |
| commit | 803a43263a6cdf9632f418a3c20f31e753c0bec7 (patch) | |
| tree | 3ce3a8009017e515a89a597a16983b164a5107d0 /Platforms | |
| parent | fc7bacda24cd97ec11fc12c029c8a29fa15b77d7 (diff) | |
Platforms/AMD: add support for AMD Overdrive and Lemaker Cello
This adds support for the AMD Seattle based Overdrive and Husky platforms,
and the Lemaker Cello which is derived from it.
This code was tested with upstream EDK2 commit 758ea94651.
The binaries in this branch are based on SeattleFDK 1.0.0.2
(Linaro SeattleFDK commit 4b419f2ef2)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platforms')
109 files changed, 17988 insertions, 0 deletions
diff --git a/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf b/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf new file mode 100644 index 0000000..34a2c63 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf @@ -0,0 +1,29 @@ +#/** @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiAml
+ FILE_GUID = 2df2a2ee-5f34-4dea-b4b6-da724e455f33
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
diff --git a/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..72272aa --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf @@ -0,0 +1,88 @@ +#/** @file
+# Sample ACPI Platform Driver
+#
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+#
+# Derived from:
+# MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxAcpiLib
+ FILE_GUID = 74850e9e-371c-43af-b1fe-794d61505ad0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = AmdStyxAcpiLib
+
+[Sources]
+ Gtdt.c
+ Fadt.c
+ Dbg2.c
+ Spcr.c
+ Madt.c
+ Mcfg.c
+ Csrt.c
+ Dsdt.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ UefiBootServicesTableLib
+
+[Protocols]
+ gAmdMpCoreInfoProtocolGuid ## CONSUMED
+
+[Pcd]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+ gAmdStyxTokenSpaceGuid.PcdEthMacA
+ gAmdStyxTokenSpaceGuid.PcdEthMacB
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gAmdStyxTokenSpaceGuid.PcdGicVersion
+ gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase
+ gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase
+ gAmdStyxTokenSpaceGuid.PcdCntControlBase
+ gAmdStyxTokenSpaceGuid.PcdCntReadBase
+ gAmdStyxTokenSpaceGuid.PcdCntCTLBase
+ gAmdStyxTokenSpaceGuid.PcdCntBase0
+ gAmdStyxTokenSpaceGuid.PcdCntEL0Base0
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase
+ gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV
+ gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion
+
+[Depex]
+ gAmdMpCoreInfoProtocolGuid
diff --git a/Platforms/AMD/Styx/AcpiTables/Csrt.c b/Platforms/AMD/Styx/AcpiTables/Csrt.c new file mode 100644 index 0000000..f25f90d --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Csrt.c @@ -0,0 +1,107 @@ +/** @file
+
+ ACPI Memory mapped configuration space base address Description Table (MCFG).
+ Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials are licensed and
+ made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the
+ license may be found at http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+//
+// CSRT for ARM_CCN504 (L3 CACHE)
+//
+#define AMD_ACPI_ARM_CCN504_CSRT_REVISION 0
+#define AMD_ACPI_ARM_CCN504_VENDOR_ID SIGNATURE_32('A','R','M','H')
+#define AMD_ACPI_ARM_CCN504_DEVICE_ID 0x510
+#define AMD_ACPI_ARM_CCN504_RESOURCE_TYPE 0x04
+#define AMD_ACPI_ARM_CCN504_DESC_VERSION 1
+#define AMD_ACPI_ARM_CCN504_HNF_COUNT 8
+#define AMD_ACPI_ARM_CCN504_BASE_ADDR 0xE8000000ULL
+#define AMD_ACPI_ARM_CCN504_CACHE_SIZE 0x00800000ULL
+
+//
+// Ensure proper (byte-packed) structure formats
+//
+#pragma pack(push, 1)
+
+typedef struct {
+ UINT32 Version;
+ UINT8 HnfRegionCount;
+ UINT8 Reserved[3];
+ UINT64 BaseAddress;
+ UINT64 CacheSize;
+} AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR;
+
+typedef struct {
+ UINT32 Length;
+ UINT16 ResourceType;
+ UINT16 ResourceSubtype;
+ UINT32 UID;
+ AMD_ACPI_ARM_CCN504_CSRT_DEVICE_DESCRIPTOR Ccn504Desc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR;
+
+typedef struct {
+ UINT32 Length;
+ UINT32 VendorId;
+ UINT32 SubvendorId;
+ UINT16 DeviceId;
+ UINT16 SubdeviceId;
+ UINT16 Revision;
+ UINT8 Reserved[2];
+ UINT32 SharedInfoLength;
+ AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR RsrcDesc;
+} AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP RsrcGroup;
+} AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE;
+
+
+AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE AcpiCsrt = {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE,
+ AMD_ACPI_ARM_CCN504_CORE_SYSTEM_RESOURCE_TABLE,
+ AMD_ACPI_ARM_CCN504_CSRT_REVISION),
+ { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_GROUP), // UINT32 RsrcGroup.Length
+ AMD_ACPI_ARM_CCN504_VENDOR_ID, // UINT32 RsrcGroup.VendorId
+ 0, // UINT32 RsrcGroup.SubvendorId
+ AMD_ACPI_ARM_CCN504_DEVICE_ID, // UINT16 RsrcGroup.DeviceId
+ 0, // UINT16 RsrcGroup.SubdeviceId
+ 0, // UINT16 RsrcGroup.Revision
+ { 0 }, // UINT8 RsrcGroup.Reserved[]
+ 0, // UINT32 RsrcGroup.SharedInfoLength
+ { sizeof (AMD_ACPI_ARM_CCN504_CSRT_RESOURCE_DESCRIPTOR), // UINT32 RsrcDesc.Length
+ AMD_ACPI_ARM_CCN504_RESOURCE_TYPE, // UINT16 RsrcDesc.ResourceType
+ 0, // UINT16 RsrcDesc.ResourceSubtype
+ 0, // UINT32 RsrcDesc.UID
+ { AMD_ACPI_ARM_CCN504_DESC_VERSION, // UINT32 Ccn504Desc.Version
+ AMD_ACPI_ARM_CCN504_HNF_COUNT, // UINT8 Ccn504Desc.HnfRegionCount
+ { 0 }, // UINT8 Ccn504Desc.Reserved[]
+ AMD_ACPI_ARM_CCN504_BASE_ADDR, // UINT64 Ccn504Desc.BaseAddress
+ AMD_ACPI_ARM_CCN504_CACHE_SIZE, // UINT64 Ccn504Desc.CacheSize
+ },
+ },
+ },
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+CsrtHeader (
+ VOID
+ )
+{
+ return &AcpiCsrt.Header;
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Dbg2.c b/Platforms/AMD/Styx/AcpiTables/Dbg2.c new file mode 100644 index 0000000..5d6cf82 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Dbg2.c @@ -0,0 +1,114 @@ +/** @file
+
+ Microsoft Debug Port Table 2 (DBG2)
+ © 2012 Microsoft. All rights reserved.<BR>
+ http://go.microsoft.com/fwlink/p/?linkid=403551
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/DebugPort2Table.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_DBG2_REVISION 0
+#define DBG2_NUM_DEBUG_PORTS 1
+#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1
+#define DBG2_NAMESPACESTRING_FIELD_SIZE 8
+#define DBG2_OEM_DATA_FIELD_SIZE 0
+#define DBG2_OEM_DATA_FIELD_OFFSET 0
+
+#define DBG2_DEBUG_PORT_SUBTYPE_PL011 0x0003 // Sub type for Pl011
+#define DBG2_DEBUG_PORT_SUBTYPE_UEFI 0x0007 // Sub type for UEFI Debug Port
+#define PL011_UART_LENGTH 0x1000
+
+#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'}
+#define NAME_STR_UEFI {'U', 'E', 'F', 'I', '\0', '\0', '\0', '\0'}
+
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
+ UINT32 AddressSize;
+ UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE];
+} DBG2_DEBUG_DEVICE_INFORMATION;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS];
+} DBG2_TABLE;
+
+
+#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \
+ { \
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision; */ \
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length; */ \
+ NumReg, /* UINT8 NumberofGenericAddressRegisters; */ \
+ DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset; */ \
+ DBG2_OEM_DATA_FIELD_SIZE, /* UINT16 OemDataLength; */ \
+ DBG2_OEM_DATA_FIELD_OFFSET, /* UINT16 OemDataOffset; */ \
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type; */ \
+ SubType, /* UINT16 Port Subtype; */ \
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2]; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset; */ \
+ OFFSET_OF(DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset; */ \
+ }, \
+ AMD_GASN (UartBase), /* EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \
+ UartAddrLen, /* UINT32 AddressSize */ \
+ UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \
+ }
+
+
+STATIC DBG2_TABLE AcpiDbg2 = {
+ {
+ AMD_ACPI_HEADER (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE,
+ DBG2_TABLE,
+ EFI_ACPI_DBG2_REVISION),
+ OFFSET_OF(DBG2_TABLE, Dbg2DeviceInfo),
+ DBG2_NUM_DEBUG_PORTS // UINT32 NumberDbgDeviceInfo
+ },
+ {
+ /*
+ * Kernel Debug Port
+ */
+#if (DBG2_NUM_DEBUG_PORTS > 0)
+ DBG2_DEBUG_PORT_DDI(DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS,
+ DBG2_DEBUG_PORT_SUBTYPE_PL011,
+ FixedPcdGet64(PcdSerialDbgRegisterBase),
+ PL011_UART_LENGTH,
+ NAME_STR_UART1),
+#endif
+ /*
+ * UEFI Debug Port
+ */
+#if (DBG2_NUM_DEBUG_PORTS > 1)
+ DBG2_DEBUG_PORT_DDI(0,
+ DBG2_DEBUG_PORT_SUBTYPE_UEFI,
+ 0,
+ 0,
+ NAME_STR_UEFI),
+#endif
+ }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+Dbg2Header (
+ VOID
+ )
+{
+ return &AcpiDbg2.Description.Header;
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.asl b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..1f0a96f --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.asl @@ -0,0 +1,804 @@ +/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Dsdt.asl
+
+**/
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+#if (NUM_CORES > 1)
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 2)
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 3)
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 4)
+ Device (CPU4)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x200) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 5)
+ Device (CPU5)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x201) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 6)
+ Device (CPU6)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x300) // _UID: Unique ID
+ }
+#endif
+#if (NUM_CORES > 7)
+ Device (CPU7)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x301) // _UID: Unique ID
+ }
+#endif
+
+ Device (AHC0)
+ {
+ Name (_HID, "AMDI0600") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0300000, // Address Base (MMIO)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0000078, // Address Base (SGPIO)
+ 0x00000001, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000183, }
+ })
+ }
+
+ Device (AHC1)
+ {
+ Name (_HID, "AMDI0600") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0D00000, // Address Base (MMIO)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE000007C, // Address Base (SGPIO)
+ 0x00000001, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000189, }
+ })
+ }
+
+#if DO_XGBE
+ Device (ETH0)
+ {
+ Name (_HID, "AMDI8001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0700000, // Address Base (XGMAC)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0780000, // Address Base (XPCS)
+ 0x00080000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1240800, // Address Base (SERDES_RxTx)
+ 0x00000400, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1250000, // Address Base (SERDES_IR_1)
+ 0x00000060, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE12500F8, // Address Base (SERDES_IR_2)
+ 0x00000004, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000165, } // XGMAC
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017A, } // DMA0
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017B, } // DMA1
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017C, } // DMA2
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x0000017D, } // DMA3
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000163, } // XPCS
+ })
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"mac-address", Package (0x06) {0x02, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5}},
+ Package (0x02) {"phy-mode", "xgmii"},
+ Package (0x02) {"amd,speed-set", 0x00},
+ Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+ Package (0x02) {"amd,ptp-freq", 0x0EE6B280},
+ Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+ Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+ Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+ Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+ Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+ Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+ Package (0x02) {"amd,per-channel-interrupt", 0x01}
+ }
+ })
+ }
+
+ Device (ETH1)
+ {
+ Name (_HID, "AMDI8001") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0900000, // Address Base (XGMAC)
+ 0x00010000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE0980000, // Address Base (XPCS)
+ 0x00080000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1240C00, // Address Base (SERDES_RxTx)
+ 0x00000400, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE1250080, // Address Base (SERDES_IR_1)
+ 0x00000060, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xE12500FC, // Address Base (SERDES_IR_2)
+ 0x00000004, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000164, } // XGMAC
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000175, } // DMA0
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000176, } // DMA1
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000177, } // DMA2
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) {0x00000178, } // DMA3
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000162, } // XPCS
+ })
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"mac-address", Package (0x06) {0x02, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5}},
+ Package (0x02) {"phy-mode", "xgmii"},
+ Package (0x02) {"amd,speed-set", 0x00},
+ Package (0x02) {"amd,dma-freq", 0x0EE6B280},
+ Package (0x02) {"amd,ptp-freq", 0x0EE6B280},
+ Package (0x02) {"amd,serdes-blwc", Package (0x03) {1, 1, 0}},
+ Package (0x02) {"amd,serdes-cdr-rate", Package (0x03) {2, 2, 7}},
+ Package (0x02) {"amd,serdes-pq-skew", Package (0x03) {10, 10, 18}},
+ Package (0x02) {"amd,serdes-tx-amp", Package (0x03) {15, 15, 10}},
+ Package (0x02) {"amd,serdes-dfe-tap-config", Package (0x03) {3, 3, 1}},
+ Package (0x02) {"amd,serdes-dfe-tap-enable", Package (0x03) {0, 0, 127}},
+ Package (0x02) {"amd,per-channel-interrupt", 0x01}
+ }
+ })
+ }
+#endif // DO_XGBE
+
+ Device (SPI0)
+ {
+ Name (_HID, "AMDI0500") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1020000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000016A, }
+ })
+ }
+
+ Device (SPI1)
+ {
+ Name (_HID, "AMDI0500") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1030000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000169, }
+ })
+
+ Device(SDC0)
+ {
+ Name(_HID, "AMDI0501") // SD Card/MMC slot
+ Name(_CRS, ResourceTemplate()
+ {
+ SPISerialBus(1, // DeviceSelection
+ PolarityLow, // DeviceSelectionPolarity
+ FourWireMode, // WireMode
+ 8, // DataBitLength
+ ControllerInitiated, // SlaveMode
+ 20000000, // ConnectionSpeed
+ ClockPolarityLow, // ClockPolarity
+ ClockPhaseFirst, // ClockPhase
+ "\\SB.SPI1", // ResourceSource
+ 0, // ResourceSourceIndex
+ ResourceConsumer, // ResourceUsage
+ ) // SPISerialBus()
+
+ // SD Card “Detect†signal
+ GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, , "\\_SB.GIO1") {6}
+ }) // ResourceTemplate()
+
+ } // Device()
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "AMDI0511") // _HID: Hardware ID
+ Name (_CID, "ARMH0011") // _CID: Compatible ID
+ Name (_ADR, 0xE1010000) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1010000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000168, }
+ })
+ }
+
+ Device (GIO0)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0080000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000189, }
+ })
+ }
+
+ Device (GIO1)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1050000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000186, }
+ })
+ }
+
+ Device (GIO2)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0020000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018E, }
+ })
+ }
+
+ Device (GIO3)
+ {
+ Name (_HID, "AMDI0400") // _HID: Hardware ID
+ Name (_CID, "ARMH0061") // _CID: Compatible ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0030000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x0000018D, }
+ })
+ }
+
+ Device (I2C0)
+ {
+ Name (_HID, "AMDI0510") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE1000000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000185, }
+ })
+
+ Method (SSCN, 0, NotSerialized)
+ {
+ Name (PKG, Package (0x03)
+ {
+ 0x0430,
+ 0x04E1,
+ 0x00
+ })
+ Return (PKG)
+ }
+
+ Method (FMCN, 0, NotSerialized)
+ {
+ Name (PKG, Package (0x03)
+ {
+ 0x00DE,
+ 0x018F,
+ 0x00
+ })
+ Return (PKG)
+ }
+ }
+
+ Device (I2C1)
+ {
+ Name (_HID, "AMDI0510") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0050000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000174, }
+ })
+
+ Method (SSCN, 0, NotSerialized)
+ {
+ Name (PKG, Package (0x03)
+ {
+ 0x0430,
+ 0x04E1,
+ 0x00
+ })
+ Return (PKG)
+ }
+
+ Method (FMCN, 0, NotSerialized)
+ {
+ Name (PKG, Package (0x03)
+ {
+ 0x00DE,
+ 0x018F,
+ 0x00
+ })
+ Return (PKG)
+ }
+ }
+
+ Device (CCP0)
+ {
+ Name (_HID, "AMDI0C00") // _HID: Hardware ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xE0100000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x00000023, }
+ })
+
+ Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (0x02) {"amd,zlib-support", 1}
+ }
+ })
+ }
+
+#if DO_KCS
+ //
+ // IPMI/KCS
+ //
+ Device (KCS0)
+ {
+ Name (_HID, "AMDI0300")
+ Name (_CID, "IPI0001")
+ Name (_STR, Unicode("IPMI_KCS"))
+ Name (_UID, 0)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xE0010000, 0x1) // KCS Data In/Out
+ Memory32Fixed(ReadWrite, 0xE0010004, 0x1) // KCS Control/Status
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,) { 421 } // GSIV
+ })
+ Method (_IFT) { // Interface Type
+ Return ( 0x01) // IPMI KCS
+ }
+
+ Method (_SRV) { // Spec Revision
+ Return (0x200) // IPMI Spec v2.0
+ }
+ }
+#endif // DO_KCS
+
+ //
+ // PCIe Root Bus
+ //
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package (0x04) // _PRT: PCI Routing Table
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x00,
+ 0x00,
+ 0x0140
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x01,
+ 0x00,
+ 0x0141
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ 0x00,
+ 0x0142
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ 0x00,
+ 0x0143
+ }
+ }) // _PRT
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x000F, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0010, // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x40000000, // Range Minimum
+ 0x5FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x60000000, // Range Minimum
+ 0x7FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x80000000, // Range Minimum
+ 0x9FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xA0000000, // Range Minimum
+ 0xBFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x20000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000001FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000100000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x00000003FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000200000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000400000000, // Range Minimum
+ 0x00000007FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000400000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000800000000, // Range Minimum
+ 0x0000000FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000001000000000, // Range Minimum
+ 0x0000001FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000001000000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000002000000000, // Range Minimum
+ 0x0000003FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000002000000000 // Length
+ )
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000004000000000, // Range Minimum
+ 0x0000007FFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000004000000000 // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0xEFFF0000, // Range Minimum
+ 0xEFFFFFFF, // Range Maximum
+ 0xEFFF0000, // Translation Address
+ 0x00010000 // Length
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+ } // Method(_CRS)
+
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+
+ //
+ // Device-Specific Methods
+ //
+ Method(_DSM, 0x4, NotSerialized) {
+ If (LEqual(Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
+ switch (ToInteger(Arg2)) {
+ //
+ // Function 0: Return supported functions
+ //
+ case(0) {
+ Return (Buffer() {0xFF})
+ }
+
+ //
+ // Function 1: Return PCIe Slot Information
+ //
+ case(1) {
+ Return (Package(2) {
+ One, // Success
+ Package(3) {
+ 0x1, // x1 PCIe link
+ 0x1, // PCI express card slot
+ 0x1 // WAKE# signal supported
+ }
+ })
+ }
+
+ //
+ // Function 2: Return PCIe Slot Number.
+ //
+ case(2) {
+ Return (Package(1) {
+ Package(4) {
+ 2, // Source ID
+ 4, // Token ID: ID refers to a slot
+ 0, // Start bit of the field to use.
+ 7 // End bit of the field to use.
+ }
+ })
+ }
+
+ //
+ // Function 3: Return Vendor-specific Token ID Strings.
+ //
+ case(3) {
+ Return (Package(0) {})
+ }
+
+ //
+ // Function 4: Return PCI Bus Capabilities
+ //
+ case(4) {
+ Return (Package(2) {
+ One, // Success
+ Buffer() {
+ 1,0, // Version
+ 0,0, // Status, 0:Success
+ 24,0,0,0, // Length
+ 1,0, // PCI
+ 16,0, // Length
+ 0, // Attributes
+ 0x0D, // Current Speed/Mode
+ 0x3F,0, // Supported Speeds/Modes
+ 0, // Voltage
+ 0,0,0,0,0,0,0 // Reserved
+ }
+ })
+ }
+
+ //
+ // Function 5: Return Ignore PCI Boot Configuration
+ //
+ case(5) {
+ Return (Package(1) {1})
+ }
+
+ //
+ // Function 6: Return LTR Maximum Latency
+ //
+ case(6) {
+ Return (Package(4) {
+ Package(1){0}, // Maximum Snoop Latency Scale
+ Package(1){0}, // Maximum Snoop Latency Value
+ Package(1){0}, // Maximum No-Snoop Latency Scale
+ Package(1){0} // Maximum No-Snoop Latency Value
+ })
+ }
+
+ //
+ // Function 7: Return PCI Express Naming
+ //
+ case(7) {
+ Return (Package(2) {
+ Package(1) {0},
+ Package(1) {Unicode("PCI0")}
+ })
+ }
+
+ //
+ // Not supported
+ //
+ default {
+ }
+ }
+ }
+ Return (Buffer(){0})
+ } // Method(_DSM)
+
+ //
+ // Root-Complex 0
+ //
+ Device (RP0)
+ {
+ Name (_ADR, 0xF0000000) // _ADR: Bus 0, Dev 0, Func 0
+ }
+ }
+ }
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Dsdt.c b/Platforms/AMD/Styx/AcpiTables/Dsdt.c new file mode 100644 index 0000000..922d721 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Dsdt.c @@ -0,0 +1,197 @@ +/** @file
+
+ C language wrapper to build DSDT generated data.
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Dsdt.hex>
+#include <Dsdt.offset.h>
+
+
+UINTN
+ShiftLeftByteToUlong (
+ IN UINT8 Byte,
+ IN UINTN Shift
+ )
+{
+ UINTN Data;
+
+ Data = (UINTN)Byte;
+ Data <<= Shift;
+ return Data;
+}
+
+UINTN
+AmlGetPkgLength (
+ IN UINT8 *Buffer,
+ OUT UINTN *PkgLength
+ )
+{
+ UINTN Bytes, Length;
+
+ Bytes = (UINTN)((Buffer[0] >> 6) & 0x3) + 1;
+ switch (Bytes) {
+ case 1:
+ Length = (UINTN)Buffer[0];
+ break;
+
+ case 2:
+ Length = ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+
+ case 3:
+ Length = ShiftLeftByteToUlong(Buffer[2], 12) +
+ ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+
+ default: /* 4 bytes */
+ Length = ShiftLeftByteToUlong(Buffer[3], 20) +
+ ShiftLeftByteToUlong(Buffer[2], 12) +
+ ShiftLeftByteToUlong(Buffer[1], 4) +
+ (UINTN)(Buffer[0] & 0x0F);
+ break;
+ }
+
+ *PkgLength = Length;
+ return Bytes;
+}
+
+UINT8 *
+AmlSearchStringPackage (
+ IN UINT8 *Buffer,
+ IN UINTN Length,
+ IN CHAR8 *String
+ )
+{
+ UINTN StrLength;
+
+ StrLength = AsciiStrLen (String) + 1;
+ if (Length > StrLength ) {
+ Length -= StrLength;
+ while (AsciiStrCmp((CHAR8 *)Buffer, String) != 0 && Length) {
+ --Length;
+ ++Buffer;
+ }
+ if (Length) {
+ return &Buffer[StrLength];
+ }
+ }
+ return NULL;
+}
+
+VOID
+OverrideMacAddr (
+ IN UINT8 *DSD_Data,
+ IN UINT64 MacAddr
+ )
+{
+ UINT8 *MacAddrPkg;
+ UINTN Bytes, Length, Index = 0;
+
+ // AML encoding: PackageOp
+ if (DSD_Data[0] == 0x12) {
+ // AML encoding: PkgLength
+ Bytes = AmlGetPkgLength (&DSD_Data[1], &Length);
+
+ // Search for "mac-address" property
+ MacAddrPkg = AmlSearchStringPackage (&DSD_Data[Bytes + 1],
+ Length - Bytes,
+ "mac-address");
+ if (MacAddrPkg &&
+ MacAddrPkg[0] == 0x12 && // PackageOp
+ MacAddrPkg[1] == 0x0E && // PkgLength
+ MacAddrPkg[2] == 0x06) { // NumElements (element must have a BytePrefix)
+
+ MacAddrPkg += 3;
+ do {
+ MacAddrPkg[0] = 0x0A; // BytePrefix
+ MacAddrPkg[1] = (UINT8)(MacAddr & 0xFF);
+ MacAddrPkg += 2;
+ MacAddr >>= 8;
+ } while (++Index < 6);
+ }
+ }
+}
+
+VOID
+OverrideStatus (
+ IN UINT8 *DSD_Data,
+ IN BOOLEAN Enable
+ )
+{
+ if (Enable) {
+ // AML encoding: ReturnOp + BytePrefix
+ if (DSD_Data[1] == 0xA4 && DSD_Data[2] == 0x0A) {
+ DSD_Data[3] = 0x0F;
+ }
+ } else {
+ // AML encoding: ReturnOp
+ if (DSD_Data[1] == 0xA4) {
+ // AML encoding: BytePrefix?
+ if (DSD_Data[2] == 0x0A) {
+ DSD_Data[3] = 0x00;
+ } else {
+ DSD_Data[2] = 0x00;
+ }
+ }
+ }
+}
+
+EFI_ACPI_DESCRIPTION_HEADER *
+DsdtHeader (
+ VOID
+ )
+{
+ AML_OFFSET_TABLE_ENTRY *Table;
+ BOOLEAN EnableOnB1;
+ UINT32 CpuId = PcdGet32 (PcdSocCpuId);
+
+ // Enable features on Styx-B1 or later
+ EnableOnB1 = (CpuId & 0xFF0) && (CpuId & 0x00F);
+
+ Table = &DSDT_SEATTLE__OffsetTable[0];
+ while (Table->Pathname) {
+ if (AsciiStrCmp(Table->Pathname, "_SB_.ETH0._DSD") == 0) {
+ OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacA));
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.ETH1._DSD") == 0) {
+ OverrideMacAddr ((UINT8 *)&AmlCode[Table->Offset], PcdGet64 (PcdEthMacB));
+ }
+#if DO_SATA1
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+ }
+#else
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.AHC1._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], FALSE);
+ }
+#endif
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO2._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+ }
+ else if (AsciiStrCmp(Table->Pathname, "_SB_.GIO3._STA") == 0) {
+ OverrideStatus ((UINT8 *)&AmlCode[Table->Offset], EnableOnB1);
+ }
+
+ ++Table;
+ }
+
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AmlCode[0];
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Fadt.c b/Platforms/AMD/Styx/AcpiTables/Fadt.c new file mode 100644 index 0000000..bcbff37 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Fadt.c @@ -0,0 +1,104 @@ +/** @file
+
+ Fixed ACPI Description Table (FADT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Fadt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#define FADT_FLAGS ( EFI_ACPI_5_1_HW_REDUCED_ACPI | \
+ EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE | \
+ EFI_ACPI_5_1_HEADLESS )
+
+#pragma pack(push, 1)
+
+STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ FADT_FLAGS, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ 0, // UINT16 ArmBootArch
+ 1, // UINT8 MinorVersion
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+FadtTable (
+ VOID
+ )
+{
+ if (FixedPcdGetBool (PcdPsciOsSupport) && FixedPcdGetBool (PcdTrustedFWSupport)) {
+ AcpiFadt.ArmBootArch = EFI_ACPI_5_1_ARM_PSCI_COMPLIANT;
+ }
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiFadt;
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Gtdt.c b/Platforms/AMD/Styx/AcpiTables/Gtdt.c new file mode 100644 index 0000000..139c9ae --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Gtdt.c @@ -0,0 +1,189 @@ +/** @file
+
+ Generic Timer Description Table (GTDT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Gtdt.aslc
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+
+#pragma pack(push, 1)
+
+#define CNT_CONTROL_BASE_ADDRESS FixedPcdGet64(PcdCntControlBase)
+#define CNT_READ_BASE_ADDRESS FixedPcdGet64(PcdCntReadBase)
+#define CNT_CTL_BASE_ADDRESS FixedPcdGet64(PcdCntCTLBase)
+#define CNT_BASE0_ADDRESS FixedPcdGet64(PcdCntBase0)
+#define CNT_EL0_BASE0_ADDRESS FixedPcdGet64(PcdCntEL0Base0)
+#define SBSA_WATCHDOG_REFRESH_BASE FixedPcdGet64(PcdSbsaWatchDogRefreshBase)
+#define SBSA_WATCHDOG_CONTROL_BASE FixedPcdGet64(PcdSbsaWatchDogControlBase)
+#define SBSA_WAKEUP_GSIV FixedPcdGet64(PcdSbsaWakeUpGSIV)
+#define SBSA_WATCHDOG_GSIV FixedPcdGet64(PcdSbsaWatchDogGSIV)
+
+
+/*
+ * Section 8.2.3 of Cortex-A15 r2p1 TRM
+ */
+#define CP15_TIMER_SEC_INTR 29
+#define CP15_TIMER_NS_INTR 30
+#define CP15_TIMER_VIRT_INTR 27
+#define CP15_TIMER_NSHYP_INTR 26
+
+/* SBSA Timers */
+ #define PLATFORM_TIMER_COUNT 2
+ #define PLATFORM_TIMER_OFFSET sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE)
+
+/*
+// GTDT Table timer flags.
+
+Bit 0: Timer interrupt Mode
+ This bit indicates the mode of the timer interrupt
+ 1: Interrupt is Edge triggered
+ 0: Interrupt is Level triggered
+Timer Interrupt polarity
+ This bit indicates the polarity of the timer interrupt
+ 1: Interrupt is Active low
+ 0: Interrupt is Active high
+Reserved 2 30 Reserved, must be zero.
+
+From A15 TRM:
+ 9.2 Generic Timer functional description
+ ...
+ Each timer provides an active-LOW interrupt output that is an external pin to the SoC and is
+ sent to the GIC as a Private Peripheral Interrupt (PPI). See Interrupt sources on page 8-4 for
+ the ID and PPI allocation of the Timer interrupts.
+ PPI6 Virtual Maintenance Interrupt.
+ PPI5 Hypervisor timer event.
+ PPI4 Virtual timer event.
+ PPI3 nIRQ.
+ PPI2 Non-secure physical timer event.
+ PPI1 Secure physical timer event.
+ PPI0-5 Active-LOW level-sensitive.
+ PPI6 Active-HIGH level-sensitive.*/
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_TIMER_SECURE EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_NON_SECURE 0
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED 0
+#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH 0
+#define GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE 0
+#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT 0
+#define GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE)
+
+#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0
+#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH 0
+#define SBSA_WATCHDOG_SECURE EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE 0
+#define SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+
+#define AMD_SBSA_GTX { \
+ EFI_ACPI_5_1_GTDT_GT_BLOCK, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) + \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), /* UINT16 Length */ \
+ EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
+ CNT_CTL_BASE_ADDRESS, /* UINT64 CntCtlBase */ \
+ 1, /* UINT32 GTBlockTimerCount */ \
+ sizeof (EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE) /* UINT32 GTBlockTimerOffset */ \
+ }
+
+#define AMD_SBSA_GTX_TIMER { \
+ 0, /* UINT8 GTFrameNumber */ \
+ {0, 0, 0}, /* UINT8 Reserved[3] */ \
+ CNT_BASE0_ADDRESS, /* UINT64 CntBaseX */ \
+ CNT_EL0_BASE0_ADDRESS, /* UINT64 CntEL0BaseX */ \
+ SBSA_WAKEUP_GSIV, /* UINT32 GTxPhysicalTimerGSIV */ \
+ GTX_TIMER_FLAGS, /* UINT32 GTxPhysicalTimerFlags */ \
+ 0, /* UINT32 GTxVirtualTimerGSIV */ \
+ GTX_TIMER_FLAGS, /* UINT32 GTxVirtualTimerFlags */ \
+ GTX_COMMON_FLAGS /* UINT32 GTxCommonFlags */ \
+ }
+
+#define AMD_SBSA_WATCHDOG { \
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), /* UINT16 Length */ \
+ EFI_ACPI_RESERVED_BYTE, /* UINT8 Reserved */ \
+ SBSA_WATCHDOG_REFRESH_BASE, /* UINT64 RefreshFramePhysicalAddress */ \
+ SBSA_WATCHDOG_CONTROL_BASE, /* UINT64 WatchdogControlFramePhysicalAddress */ \
+ SBSA_WATCHDOG_GSIV, /* UINT32 WatchdogTimerGSIV */ \
+ SBSA_WATCHDOG_FLAGS /* UINT32 WatchdogTimerFlags */ \
+ }
+
+typedef struct {
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE GTxBlock;
+ EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE GTxTimer;
+ EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE WatchDog;
+} AMD_ACPI_5_1_ARM_GTDT_STRUCTURE;
+
+STATIC AMD_ACPI_5_1_ARM_GTDT_STRUCTURE AcpiGtdt = {
+ {
+ AMD_ACPI_HEADER(EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ AMD_ACPI_5_1_ARM_GTDT_STRUCTURE,
+ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
+ CNT_CONTROL_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ CP15_TIMER_SEC_INTR, // UINT32 SecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags
+ CP15_TIMER_NS_INTR, // UINT32 NonSecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags
+ CP15_TIMER_VIRT_INTR, // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ CP15_TIMER_NSHYP_INTR, // UINT32 NonSecureEL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags
+ CNT_READ_BASE_ADDRESS, // UINT64 CntReadBaseAddress
+ PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount
+ PLATFORM_TIMER_OFFSET // UINT32 PlatformTimerOffset
+ },
+ AMD_SBSA_GTX,
+ AMD_SBSA_GTX_TIMER,
+ AMD_SBSA_WATCHDOG,
+};
+
+#pragma pack(pop)
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+GtdtHeader (
+ VOID
+ )
+{
+ UINT32 CpuId = PcdGet32 (PcdSocCpuId);
+
+ // Check BaseModel and Stepping: Styx-B0 or prior?
+ if (((CpuId & 0xFF0) == 0) || ((CpuId & 0x00F) == 0)) {
+ AcpiGtdt.Gtdt.Header.Length = sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE);
+ AcpiGtdt.Gtdt.PlatformTimerCount = 0;
+ AcpiGtdt.Gtdt.PlatformTimerOffset = 0;
+ }
+
+ return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiGtdt.Gtdt.Header;
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Madt.c b/Platforms/AMD/Styx/AcpiTables/Madt.c new file mode 100644 index 0000000..96182e7 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Madt.c @@ -0,0 +1,336 @@ +/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+
+ Derived from:
+ ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
+
+**/
+
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <AmdStyxAcpiLib.h>
+#include <Protocol/AmdMpCoreInfo.h>
+
+AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL;
+
+
+// ARM PL390 General Interrupt Controller
+#define GIC_BASE (FixedPcdGet64 (PcdGicInterruptInterfaceBase))
+#define GICD_BASE (FixedPcdGet64 (PcdGicDistributorBase))
+#define GICV_BASE (FixedPcdGet64 (PcdGicVirtualInterruptInterfaceBase))
+#define GICH_BASE (FixedPcdGet64 (PcdGicHypervisorInterruptInterfaceBase))
+#define VGIC_MAINT_INT (FixedPcdGet32 (PcdGicVirtualMaintenanceInterrupt))
+#define GICVR_BASE (FixedPcdGet64 (PcdGicVirtualRegisterInterfaceBase))
+#define GIC_MSI_FRAME (FixedPcdGet64 (PcdGicMSIFrameBase))
+#define GIC_VERSION (FixedPcdGet8 (PcdGicVersion))
+
+#define GICD_ID ( 0 )
+#define GICD_VECTOR ( 0 )
+
+#define GICM_ID ( 0 )
+#define GICM_SPI_COUNT ( 0x100 )
+#define GICM_SPI_BASE ( 0x40 )
+#define GSIV_SPI_OFFSET ( 32 )
+
+#if STYX_A0
+ #define MSI_TYPER_FLAG ( 1 ) // Ignore TYPER register and use Count/Base fields
+#else
+ #define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields
+#endif
+
+#define PARKING_PROTOCOL_VERSION (FixedPcdGet32 (PcdParkingProtocolVersion))
+#define PARKED_OFFSET ( 4096 )
+
+#define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster))
+#define PARKED_ADDRESS(Base, ClusterId, CoreId) \
+ ((Base) + (CORES_PER_CLUSTER * ClusterId + CoreId) * PARKED_OFFSET)
+
+
+/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */
+#define AMD_GIC(CpuNum, ClusterId, CoreId, PerfInt) { \
+ EFI_ACPI_5_1_GIC, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GIC_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved */ \
+ CpuNum, /* UINT32 CPUInterfaceNumber */ \
+ (ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \
+ EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \
+ PARKING_PROTOCOL_VERSION, /* UINT32 ParkingProtocolVersion */ \
+ PerfInt, /* UINT32 PerformanceInterruptGsiv */ \
+ 0, /* UINT64 ParkedAddress */ \
+ GIC_BASE, /* UINT64 PhysicalBaseAddress */ \
+ GICV_BASE, /* UINT64 GICV */ \
+ GICH_BASE, /* UINT64 GICH */ \
+ VGIC_MAINT_INT, /* UINT32 VGICMaintenanceInterrupt */ \
+ GICVR_BASE, /* UINT64 GICRBaseAddress */ \
+ (ClusterId << 8) | CoreId /* UINT64 MPIDR */ \
+ }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE */
+#define AMD_GICD(Id, Vec) { \
+ EFI_ACPI_5_1_GICD, /* UINT8 Type */ \
+ sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \
+ Id, /* UINT32 GicId */ \
+ GICD_BASE, /* UINT64 PhysicalBaseAddress */ \
+ Vec, /* UINT32 SystemVectorBase */ \
+ EFI_ACPI_RESERVED_DWORD /* UINT32 Reserved2 */ \
+ }
+
+/* Macro to initialise EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE */
+#define AMD_GICM(Id, SpiCount, SpiBase) { \
+ EFI_ACPI_5_1_GIC_MSI_FRAME, /* UINT8 Type */ \
+ sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE), /* UINT8 Length */ \
+ EFI_ACPI_RESERVED_WORD, /* UINT16 Reserved1 */ \
+ Id, /* UINT32 GicMsiFrameId */ \
+ GIC_MSI_FRAME, /* UINT64 PhysicalBaseAddress */ \
+ MSI_TYPER_FLAG, /* UINT32 Flags */ \
+ SpiCount, /* UINT16 SPICount */ \
+ SpiBase /* UINT16 SPIBase */ \
+ }
+
+
+//
+// NOTE: NUM_CORES is a pre-processor macro passed in with -D option
+//
+#pragma pack(push, 1)
+typedef struct {
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_5_1_GIC_STRUCTURE GicC[NUM_CORES];
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicD;
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE GicM;
+} EFI_ACPI_5_1_ARM_MADT_STRUCTURE;
+#pragma pack(pop)
+
+
+STATIC EFI_ACPI_5_1_ARM_MADT_STRUCTURE AcpiMadt = {
+ {
+ AMD_ACPI_HEADER (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_5_1_ARM_MADT_STRUCTURE,
+ EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ GIC_BASE, // UINT32 LocalApicAddress
+ 0 // UINT32 Flags
+ },
+ {
+ /*
+ * GIC Interface for Cluster 0 CPU 0
+ */
+ AMD_GIC(0, 0, 0, 39), // EFI_ACPI_5_1_GIC_STRUCTURE
+#if (NUM_CORES > 1)
+ /*
+ * GIC Interface for Cluster 0 CPU 1
+ */
+ AMD_GIC(1, 0, 1, 40), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 2)
+ /*
+ * GIC Interface for Cluster 1 CPU 0
+ */
+ AMD_GIC(2, 1, 0, 41), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 3)
+ /*
+ * GIC Interface for Cluster 1 CPU 1
+ */
+ AMD_GIC(3, 1, 1, 42), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 4)
+ /*
+ * GIC Interface for Cluster 2 CPU 0
+ */
+ AMD_GIC(4, 2, 0, 43), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 5)
+ /*
+ * GIC Interface for Cluster 2 CPU 1
+ */
+ AMD_GIC(5, 2, 1, 44), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 6)
+ /*
+ * GIC Interface for Cluster 3 CPU 0
+ */
+ AMD_GIC(6, 3, 0, 45), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+#if (NUM_CORES > 7)
+ /*
+ * GIC Interface for Cluster 3 CPU 1
+ */
+ AMD_GIC(7, 3, 1, 46), // EFI_ACPI_5_1_GIC_STRUCTURE
+#endif
+ },
+ /*
+ * GIC Distributor
+ */
+ AMD_GICD(GICD_ID, GICD_VECTOR), // EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE
+ /*
+ * GIC MSI Frame
+ */
+ AMD_GICM(GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE),
+};
+
+
+STATIC
+EFI_STATUS
+BuildGicC (
+ EFI_ACPI_5_1_GIC_STRUCTURE *GicC,
+ UINT32 CpuNum,
+ UINT32 ClusterId,
+ UINT32 CoreId,
+ EFI_PHYSICAL_ADDRESS MpParkingBase
+ )
+{
+ UINT32 MpId, PmuSpi;
+ EFI_STATUS Status;
+
+ MpId = (UINT32) GET_MPID (ClusterId, CoreId);
+ Status = mAmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuSpi);
+ if (EFI_ERROR (Status))
+ return Status;
+
+ GicC->Type = EFI_ACPI_5_1_GIC;
+ GicC->Length = sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+ GicC->Reserved = EFI_ACPI_RESERVED_WORD;
+ GicC->CPUInterfaceNumber = CpuNum;
+ GicC->AcpiProcessorUid = MpId;
+ GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED;
+ GicC->ParkingProtocolVersion = PARKING_PROTOCOL_VERSION;
+ GicC->ParkedAddress = PARKED_ADDRESS(MpParkingBase, ClusterId, CoreId);
+ GicC->PhysicalBaseAddress = GIC_BASE;
+ GicC->GICV = GICV_BASE;
+ GicC->GICH = GICH_BASE;
+ GicC->VGICMaintenanceInterrupt = VGIC_MAINT_INT;
+ GicC->GICRBaseAddress = GICVR_BASE;
+ GicC->PerformanceInterruptGsiv = PmuSpi + GSIV_SPI_OFFSET;
+ GicC->MPIDR = MpId;
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+BuildGicD (
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD,
+ UINT32 GicId,
+ UINT32 SystemVectorBase
+ )
+{
+ GicD->Type = EFI_ACPI_5_1_GICD;
+ GicD->Length = sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+ GicD->Reserved1 = EFI_ACPI_RESERVED_WORD;
+ GicD->GicId = GicId;
+ GicD->PhysicalBaseAddress = GICD_BASE;
+ GicD->SystemVectorBase = SystemVectorBase;
+#if 0
+ GicD->Reserved2 = EFI_ACPI_RESERVED_DWORD;
+#else
+ GicD->GicVersion = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[0] = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[1] = EFI_ACPI_RESERVED_BYTE;
+ GicD->Reserved2[2] = EFI_ACPI_RESERVED_BYTE;
+#endif
+}
+
+
+STATIC
+VOID
+BuildGicM (
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM,
+ UINT32 MsiFrameId,
+ UINT16 SpiCount,
+ UINT16 SpiBase
+ )
+{
+ GicM->Type = EFI_ACPI_5_1_GIC_MSI_FRAME;
+ GicM->Length = sizeof(EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+ GicM->Reserved1 = EFI_ACPI_RESERVED_WORD;
+ GicM->GicMsiFrameId = MsiFrameId;
+ GicM->PhysicalBaseAddress = GIC_MSI_FRAME;
+ GicM->Flags = MSI_TYPER_FLAG;
+ GicM->SPICount = SpiCount;
+ GicM->SPIBase = SpiBase;
+}
+
+
+EFI_ACPI_DESCRIPTION_HEADER *
+MadtHeader (
+ VOID
+ )
+{
+ EFI_ACPI_5_1_GIC_STRUCTURE *GicC;
+ EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *GicD;
+ EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *GicM;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN CoreCount, CpuNum;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+
+ Status = gBS->LocateProtocol (
+ &gAmdMpCoreInfoProtocolGuid,
+ NULL,
+ (VOID **)&mAmdMpCoreInfoProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Get pointer to ARM core info table
+ ArmCoreInfoTable = mAmdMpCoreInfoProtocol->GetArmCoreInfoTable (&CoreCount);
+ ASSERT (ArmCoreInfoTable != NULL);
+
+ // Make sure SoC's core count does not exceed what we want to build
+ ASSERT (CoreCount <= NUM_CORES);
+ ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount));
+
+ MpParkingSize = 0;
+ MpParkingBase = mAmdMpCoreInfoProtocol->GetMpParkingBase(&MpParkingSize);
+ if (MpParkingBase && MpParkingSize < (CoreCount * SIZE_4KB)) {
+ DEBUG ((EFI_D_ERROR, "MADT: Parking Protocol not supported.\n"));
+ MpParkingBase = 0;
+ }
+
+ GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0];
+ AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
+
+ for (CpuNum = 0; CpuNum < CoreCount; ++CpuNum, ++GicC) {
+ DEBUG ((EFI_D_ERROR, "MADT: Core[%d]: ClusterId = %d CoreId = %d\n",
+ CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, ArmCoreInfoTable[CpuNum].CoreId));
+
+ Status = BuildGicC (GicC, CpuNum,
+ ArmCoreInfoTable[CpuNum].ClusterId,
+ ArmCoreInfoTable[CpuNum].CoreId,
+ MpParkingBase
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_STRUCTURE);
+ }
+
+ GicD = (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+ BuildGicD (GicD, GICD_ID, GICD_VECTOR);
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE);
+
+ GicM = (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE *)(UINT8 *)((UINTN)&AcpiMadt + (UINTN)AcpiMadt.Header.Header.Length);
+ BuildGicM (GicM, GICM_ID, GICM_SPI_COUNT, GICM_SPI_BASE);
+ AcpiMadt.Header.Header.Length += sizeof (EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE);
+
+ return &AcpiMadt.Header.Header;
+}
+
diff --git a/Platforms/AMD/Styx/AcpiTables/Mcfg.c b/Platforms/AMD/Styx/AcpiTables/Mcfg.c new file mode 100644 index 0000000..4fc18e8 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Mcfg.c @@ -0,0 +1,51 @@ +/** @file
+
+ ACPI Memory mapped configuration space base address Description Table (MCFG).
+ Implementation based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials are licensed and
+ made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the
+ license may be found at http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#if STYX_A0
+#define END_PCI_BUS_NUMBER 15
+#else
+#define END_PCI_BUS_NUMBER 255
+#endif
+
+#pragma pack(push, 1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure;
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE AcpiMcfg = {
+ { AMD_ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD },
+ { 0xF0000000ULL, 0, 0, END_PCI_BUS_NUMBER, EFI_ACPI_RESERVED_DWORD }
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+McfgHeader (
+ VOID
+ )
+{
+ return &AcpiMcfg.Header.Header;
+}
diff --git a/Platforms/AMD/Styx/AcpiTables/Spcr.c b/Platforms/AMD/Styx/AcpiTables/Spcr.c new file mode 100644 index 0000000..719c276 --- /dev/null +++ b/Platforms/AMD/Styx/AcpiTables/Spcr.c @@ -0,0 +1,124 @@ +/** @file
+
+ Serial Port Console Redirection Table
+ © 2000 - 2014 Microsoft Corporation. All rights reserved.
+ http://go.microsoft.com/fwlink/?linkid=403368
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+
+#pragma pack(push, 1)
+
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011 3
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE AcpiSpcr = {
+ //
+ // Header
+ //
+ AMD_ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ 2), /* New MS definition for PL011 support */
+ //
+ // InterfaceType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_PL011,
+ //
+ // Reserved[3]
+ //
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ //
+ // BaseAddress
+ //
+ AMD_GASN(FixedPcdGet64(PcdSerialRegisterBase)),
+ //
+ // InterruptType
+ //
+ 0,
+ //
+ // Irq
+ //
+ 0,
+ //
+ // GlobalSystemInterrupt
+ //
+ 0x148,
+ //
+ // BaudRate
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ //
+ // Parity
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ //
+ // StopBits
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ //
+ // FlowControl
+ //
+ 0,
+ //
+ // TerminalType
+ //
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ //
+ // Language
+ //
+ EFI_ACPI_RESERVED_BYTE,
+ //
+ // PciDeviceId
+ //
+ 0xFFFF,
+ //
+ // PciVendorId
+ //
+ 0xFFFF,
+ //
+ // PciBusNumber
+ //
+ 0x00,
+ //
+ // PciDeviceNumber
+ //
+ 0x00,
+ //
+ // PciFunctionNumber
+ //
+ 0x00,
+ //
+ // PciFlags
+ //
+ 0,
+ //
+ // PciSegment
+ //
+ 0,
+ //
+ // Reserved2
+ //
+ EFI_ACPI_RESERVED_DWORD
+};
+
+#pragma pack(pop)
+
+EFI_ACPI_DESCRIPTION_HEADER *
+SpcrHeader (
+ VOID
+ )
+{
+ return &AcpiSpcr.Header;
+}
+
diff --git a/Platforms/AMD/Styx/AmdStyx.dec b/Platforms/AMD/Styx/AmdStyx.dec new file mode 100644 index 0000000..3466d1e --- /dev/null +++ b/Platforms/AMD/Styx/AmdStyx.dec @@ -0,0 +1,113 @@ +#/** @file
+# AmdStyx package.
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may be
+# found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = AmdStyx
+ PACKAGE_GUID = 58353cd1-61fb-4f9e-93f7-c43961d39b01
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Common
+
+[LibraryClasses]
+
+[Ppis]
+ gAmdStyxPlatInitPpiGuid = { 0xcbff429c, 0xd3e3, 0x4c50, { 0xac, 0x1a, 0x1c, 0xd2, 0xfe, 0x15, 0x1a, 0xd7 } }
+
+[Protocols]
+ gAmdMpBootProtocolGuid = { 0xe21eac84, 0x9fbf, 0x4808, { 0x83, 0x93, 0xe1, 0x93, 0x97, 0x23, 0x48, 0xab } }
+ gAmdMpCoreInfoProtocolGuid = { 0x0dba25f8, 0x2da1, 0x4ec5, { 0x89, 0x5d, 0x32, 0x1e, 0xd6, 0x1e, 0x3f, 0x43 } }
+
+[Guids]
+ gAmdStyxTokenSpaceGuid = { 0x220d9653, 0x4a0e, 0x40bc, { 0xb3, 0x65, 0x2f, 0xbb, 0xa2, 0xd9, 0x03, 0x45 } }
+ gAmdStyxMpCoreInfoGuid = { 0x68efeabd, 0xcb77, 0x4aa5, { 0xbf, 0x0c, 0xa3, 0x31, 0xfc, 0xcf, 0x76, 0x66 } }
+
+[PcdsDynamic]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101
+
+ gAmdStyxTokenSpaceGuid.PcdEthMacA|0|UINT64|0x000d0001
+ gAmdStyxTokenSpaceGuid.PcdEthMacB|0|UINT64|0x000d0002
+
+[PcdsFixedAtBuild]
+ # CPUID Register
+ gAmdStyxTokenSpaceGuid.PcdCpuIdRegister|0xE0000010|UINT32|0x00000200
+
+ # FDT support
+ gAmdStyxTokenSpaceGuid.PcdStyxFdt|{ 0xe4, 0x08, 0x0d, 0x04, 0x9a, 0x47, 0x4b, 0x42, 0x8c, 0x42, 0x36, 0x64, 0xdf, 0x79, 0x3f, 0x4b }|VOID*|0x00010000
+
+ # Synopsys SATA Controller
+ gAmdStyxTokenSpaceGuid.PcdSataCtrlAxiSlvPort|0xE0300000|UINT32|0x00020000
+ gAmdStyxTokenSpaceGuid.PcdSataPortCount|8|UINT8|0x00020001
+ gAmdStyxTokenSpaceGuid.PcdSataPi|0xFF|UINT32|0x00020002
+ gAmdStyxTokenSpaceGuid.PcdSataPortMode|0|UINT16|0x00020003
+ gAmdStyxTokenSpaceGuid.PcdSataPortMpsp|TRUE|BOOLEAN|0x00020004
+ gAmdStyxTokenSpaceGuid.PcdSataSmpsSupport|FALSE|BOOLEAN|0x00020005
+ gAmdStyxTokenSpaceGuid.PcdSataSssSupport|TRUE|BOOLEAN|0x00020006
+ gAmdStyxTokenSpaceGuid.PcdSataPortCpd|TRUE|BOOLEAN|0x00020007
+ gAmdStyxTokenSpaceGuid.PcdSata1CtrlAxiSlvPort|0xE0D00000|UINT32|0x00020008
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount|8|UINT8|0x00020009
+
+ # UART
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0xE1010000|UINT64|0x00030000
+ gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200|UINT32|0x00030001
+
+ # GIC
+ gAmdStyxTokenSpaceGuid.PcdGicVersion|0x2|UINT8|0x00040000
+ gAmdStyxTokenSpaceGuid.PcdGicHypervisorInterruptInterfaceBase|0xE1140000|UINT64|0x00040001
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualInterruptInterfaceBase|0xE116F000|UINT64|0x00040002
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualMaintenanceInterrupt|25|UINT32|0x00040003
+ gAmdStyxTokenSpaceGuid.PcdGicVirtualRegisterInterfaceBase|0x00000000|UINT64|0x00040004
+ gAmdStyxTokenSpaceGuid.PcdGicMSIFrameBase|0xE1180000|UINT64|0x00040005
+
+ # Timers (GTDT)
+ gAmdStyxTokenSpaceGuid.PcdCntControlBase|0xFFFFFFFFFFFFFFFF|UINT64|0x00050000
+ gAmdStyxTokenSpaceGuid.PcdCntReadBase|0x00000000E0B90000|UINT64|0x00050001
+ gAmdStyxTokenSpaceGuid.PcdCntCTLBase|0x00000000E0BD0000|UINT64|0x00050002
+ gAmdStyxTokenSpaceGuid.PcdCntBase0|0x00000000E0BE0000|UINT64|0x00050003
+ gAmdStyxTokenSpaceGuid.PcdCntEL0Base0|0x00000000E0BF0000|UINT64|0x00050004
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogRefreshBase|0x00000000E0BB0000|UINT64|0x00050005
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogControlBase|0x00000000E0BC0000|UINT64|0x00050006
+ gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV|371|UINT32|0x00050007
+ gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV|369|UINT32|0x00050008
+
+ # Trusted-Firmware
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport|TRUE|BOOLEAN|0x00060000
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase|0x8000000000|UINT64|0x00060001
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize|0xE80000|UINT64|0x0006002
+
+ # ISCP
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE|BOOLEAN|0x00070000
+
+ # PSCI
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE|BOOLEAN|0x00080000
+ gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext|0|UINT64|0x00080001
+
+ # Cores Per cluster
+ gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster|2|UINT32|0x00090000
+
+ # UEFI entry point
+ gAmdStyxTokenSpaceGuid.PcdUefiEntryAddress|0x8000E80000|UINT64|0x000a0000
+
+ # Parking Protocol
+ gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion|1|UINT32|0x000b0000
+
+ # The original offset in memory of the NV store firmware volume, before
+ # relocating it to a dynamically allocated buffer. We need this to correlate
+ # flash accesses to the in-memory copy with LBAs in the actual SPI flash
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|0|UINT64|0x000c0000
+ # block size to use when invoking the ISCP FV methods
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize|0x1000|UINT32|0x000c0001
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/AmdModulePkg.dec b/Platforms/AMD/Styx/Binary/AmdModulePkg/AmdModulePkg.dec new file mode 100644 index 0000000..15ee61b --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/AmdModulePkg.dec @@ -0,0 +1,133 @@ +#**
+# @file
+#
+# AmdModulePkg.dec
+#
+# AMD-specific package declaration file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 337482 $ @e date: $Date: 2016-03-11 21:39:02 -0600 (Fri, 11 Mar 2016) $
+#
+#
+##*****************************************************************************
+#
+# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = AmdModulePkg
+ PACKAGE_GUID = E967965B-4447-4CBB-9521-898B5A329240
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER
+#
+################################################################################
+[Includes]
+ Common
+ Include
+ Include/Library
+ Include/Ppi
+ Include/Protocol
+
+
+[LibraryClasses]
+ ## @libraryclass Provides a library function to get a DXE driver name
+ ##
+
+[Protocols]
+ gAmdIscpDxeProtocolGuid = { 0x05c794c8, 0x6aef, 0x4450, { 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 } }
+ gAmdRasApeiProtocolGuid = { 0xe9dbcc60, 0x8f93, 0x47ed, { 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a } }
+
+[Ppis]
+ gPeiIscpPpiGuid = { 0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } }
+ gPeiFusePpiGuid = { 0xe074fa9f, 0x1bc7, 0x4af9, { 0x8f, 0x0d, 0x90, 0x0b, 0x76, 0x50, 0x5f, 0xfe } }
+ gPeiGionbPpiGuid = { 0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0x0f, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } }
+
+[Guids]
+ gAmdModulePkgTokenSpaceGuid = { 0x2f9003d7, 0xac98, 0x407d, { 0xae, 0x38, 0x9d, 0xbf, 0x81, 0x27, 0xe5, 0xb1 } }
+ gAmdModulePkgVariableGuid = { 0xf3dd4189, 0xe1b7, 0x49da, { 0xa5, 0xd3, 0x34, 0x28, 0x6f, 0xae, 0x2f, 0x01 } }
+
+[PcdsFixedAtBuild]
+ gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMajor|0x1|UINT8|0x00000026
+ gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMinor|0x0|UINT8|0x00000027
+ gAmdModulePkgTokenSpaceGuid.PcdFdkVersionPoint|0x0|UINT8|0x00000028
+ gAmdModulePkgTokenSpaceGuid.PcdFdkVersionSubpoint|0x2|UINT8|0x00000029
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+ gAmdModulePkgTokenSpaceGuid.PcdCCPBase|0xE0100000|UINT64|0x00000001
+ gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes0|0xE0B00000|UINT64|0x00000002
+ gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes1|0xE0B20000|UINT64|0x00000003
+ gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes2|0xE0B40000|UINT64|0x00000004
+ gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes3|0xE0B60000|UINT64|0x00000005
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdes0|0xE1200000|UINT64|0x00000006
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdes1|0xE1210000|UINT64|0x00000007
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdes2|0xE1220000|UINT64|0x00000008
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdes3|0xE1230000|UINT64|0x00000009
+ gAmdModulePkgTokenSpaceGuid.PcdEthernetSerdes|0xE1240000|UINT64|0x0000000a
+ gAmdModulePkgTokenSpaceGuid.PcdSataMMU401|0xE0200000|UINT64|0x0000000b
+ gAmdModulePkgTokenSpaceGuid.PcdDMA330MMU401|0xE0400000|UINT64|0x0000000c
+ gAmdModulePkgTokenSpaceGuid.PcdCCN504Space|0xE8000000|UINT64|0x0000000d
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2|UINT8|0x0000000e
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000|UINT32|0x0000000f
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000|UINT32|0x00000010
+
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|FALSE|BOOLEAN|0x00000033
+
+#XGMAC ETH0 MAC
+ gAmdModulePkgTokenSpaceGuid.PcdEthMacA|0|UINT64|0x0000011
+#XGMAC ETH1 MAC
+ gAmdModulePkgTokenSpaceGuid.PcdEthMacB|0|UINT64|0x0000012
+
+ gAmdModulePkgTokenSpaceGuid.PcdPort0PhyMode|1|UINT8|0x0000013
+ gAmdModulePkgTokenSpaceGuid.PcdPort1PhyMode|1|UINT8|0x0000014
+ gAmdModulePkgTokenSpaceGuid.PcdPort0NetSpeed|1|UINT8|0x0000015
+ gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1|UINT8|0x0000016
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|FALSE|BOOLEAN|0x0000017
+
+ gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|0|UINT8|0x00000018
+ gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|UINT8|0x00000019
+ gAmdModulePkgTokenSpaceGuid.PcdIocClockGating|1|UINT8|0x0000001a
+ gAmdModulePkgTokenSpaceGuid.PcdAifClockGating|1|UINT8|0x0000001b
+ gAmdModulePkgTokenSpaceGuid.PcdPcieFuseEnable|TRUE|BOOLEAN|0x000001c
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|UINT8|0x000001d
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|UINT8|0x000001e
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|UINT8|0x000001f
+ gAmdModulePkgTokenSpaceGuid.PcdPcieGen3|0|UINT8|0x00000020
+ gAmdModulePkgTokenSpaceGuid.PcdPcieGen2|0|UINT8|0x00000021
+ gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|FALSE|BOOLEAN|0x0000022
+
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeRev|1|UINT8|0x0000002A
+
+ gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1|31|UINT32|0x0000002B
+ gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2|47|UINT32|0x0000002C
+ gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3|63|UINT32|0x0000002D
+ gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1|31|UINT32|0x0000002E
+ gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2|47|UINT32|0x0000002F
+ gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3|63|UINT32|0x00000030
+
+ gAmdModulePkgTokenSpaceGuid.PcdXgbePort0SwKrTrain|0|UINT8|0x00000031
+ gAmdModulePkgTokenSpaceGuid.PcdXgbePort1SwKrTrain|0|UINT8|0x00000032
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CoreState.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CoreState.h new file mode 100644 index 0000000..7ce4998 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CoreState.h @@ -0,0 +1,66 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * CoreState.h
+ *
+ * CPU Core State Structures and Definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+//#########################################################################
+//#########################################################################
+//#########################################################################
+// NOTE: This file shared between SCP and UEFI, make sure all //
+// changes are reflected in both copies. //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef CORESTATUS_H_
+#define CORESTATUS_H_
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/// Core State Enumeration
+typedef enum {
+ CPU_CORE_UNDEFINED = 0, ///< Core is undefined
+ CPU_CORE_DISABLED, ///< Core is disabled
+ CPU_CORE_POWERUP, ///< Core/cluster is powered up
+ CPU_CORE_POWERDOWN, ///< Core/cluster is powered down
+ CPU_CORE_RESET, ///< Core is powered but in reset
+ CPU_CORE_RUN, ///< Core is running
+ CPU_CORE_SLEEP, ///< Core is powered and sleeping (TBD)
+} CPU_CORE_STATE;
+
+/// SOC Core Status Structure
+typedef struct {
+ UINT32 ClusterId; ///< CPU Cluster ID
+ UINT32 CoreId; ///< CPU Core ID
+ CPU_CORE_STATE Status; ///< Core State Enumeration
+ UINT64 ResetVector; ///< CPU Core Reset Vector
+} SocCoreStatus;
+
+#endif /* CORESTATUS_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CpuIscp.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CpuIscp.h new file mode 100644 index 0000000..ca86894 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/CpuIscp.h @@ -0,0 +1,492 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * MemIscp.h
+ *
+ * Contains common Memory Training ISCP-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+// NOTE: This file shared between SCP and UEFI, make sure all //
+// changes are reflected in both copies. //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef CPUISCP_H_
+#define CPUISCP_H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+ #include <ProcessorBind.h> // Included just so this file can be built into both the RTOS
+ // and UEFI without needing separate copies for both build
+ // environments.
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+ /// Processor ID
+ typedef struct {
+ UINT32 ProcIDMsd; ///< Processor ID Msd
+ UINT32 ProcIDLsd; ///< Processor ID Lsd
+ } ISCP_PROC_ID;
+
+ /// Processor Type
+ typedef enum {
+ ISCP_CPU_TYPE_OTHER = 1, ///< Other
+ ISCP_CPU_TYPE_UNKNOWN, ///< Unknown
+ ISCP_CPU_TYPE_CENTRAL_PROCESSOR, ///< Central Processor
+ ISCP_CPU_TYPE_MATH_COPROCESSOR, ///< Math Coprocessor
+ ISCP_CPU_TYPE_DSP_PROCESSOR, ///< DSP Processor
+ ISCP_CPU_TYPE_VIDEO_PROCESSOR ///< Video Processor
+ } ISCP_PROCESSOR_TYPE;
+
+ /// Processor Information - Processor Family.
+ typedef enum {
+ ISCP_ProcessorFamilyOther = 0x01, ///< Processor Family - Other
+ ISCP_ProcessorFamilyUnknown = 0x02, ///< Processor Family - Unknown
+ ISCP_ProcessorFamily8086 = 0x03, ///< Processor Family - 8086
+ ISCP_ProcessorFamily80286 = 0x04, ///< Processor Family - 80286
+ ISCP_ProcessorFamilyIntel386 = 0x05, ///< Processor Family - Intel 386
+ ISCP_ProcessorFamilyIntel486 = 0x06, ///< Processor Family - Intel 486
+ ISCP_ProcessorFamily8087 = 0x07, ///< Processor Family - 8087
+ ISCP_ProcessorFamily80287 = 0x08, ///< Processor Family - 80287
+ ISCP_ProcessorFamily80387 = 0x09, ///< Processor Family - 80387
+ ISCP_ProcessorFamily80487 = 0x0A, ///< Processor Family - 80487
+ ISCP_ProcessorFamilyPentium = 0x0B, ///< Processor Family - Pentium
+ ISCP_ProcessorFamilyPentiumPro = 0x0C, ///< Processor Family - Pentium Pro
+ ISCP_ProcessorFamilyPentiumII = 0x0D, ///< Processor Family - Pentium II
+ ISCP_ProcessorFamilyPentiumMMX = 0x0E, ///< Processor Family - Pentium MMX
+ ISCP_ProcessorFamilyCeleron = 0x0F, ///< Processor Family - Celeron
+ ISCP_ProcessorFamilyPentiumIIXeon = 0x10, ///< Processor Family - Pentium II Xeon
+ ISCP_ProcessorFamilyPentiumIII = 0x11, ///< Processor Family - Pentium III
+ ISCP_ProcessorFamilyM1 = 0x12, ///< Processor Family - M1
+ ISCP_ProcessorFamilyM2 = 0x13, ///< Processor Family - M2
+ ISCP_ProcessorFamilyIntelCeleronM = 0x14, ///< Processor Family - Intel Celeron
+ ISCP_ProcessorFamilyIntelPentium4Ht = 0x15, ///< Processor Family - Intel Pentium 4Ht
+ ISCP_ProcessorFamilyAmdDuron = 0x18, ///< Processor Family - AMD Duron
+ ISCP_ProcessorFamilyK5 = 0x19, ///< Processor Family - K5
+ ISCP_ProcessorFamilyK6 = 0x1A, ///< Processor Family - K6
+ ISCP_ProcessorFamilyK6_2 = 0x1B, ///< Processor Family - K6-2
+ ISCP_ProcessorFamilyK6_3 = 0x1C, ///< Processor Family - K6-3
+ ISCP_ProcessorFamilyAmdAthlon = 0x1D, ///< Processor Family - AMD Athlon
+ ISCP_ProcessorFamilyAmd29000 = 0x1E, ///< Processor Family - AMD 29000
+ ISCP_ProcessorFamilyK6_2Plus = 0x1F, ///< Processor Family - K6-2 Plus
+ ISCP_ProcessorFamilyPowerPC = 0x20, ///< Processor Family - Power PC
+ ISCP_ProcessorFamilyPowerPC601 = 0x21, ///< Processor Family - Power PC 601
+ ISCP_ProcessorFamilyPowerPC603 = 0x22, ///< Processor Family - Power PC 603
+ ISCP_ProcessorFamilyPowerPC603Plus = 0x23, ///< Processor Family - Power PC 603 Plus
+ ISCP_ProcessorFamilyPowerPC604 = 0x24, ///< Processor Family - Power PC 604
+ ISCP_ProcessorFamilyPowerPC620 = 0x25, ///< Processor Family - Power PC 620
+ ISCP_ProcessorFamilyPowerPCx704 = 0x26, ///< Processor Family - Power PC x704
+ ISCP_ProcessorFamilyPowerPC750 = 0x27, ///< Processor Family - Power PC 750
+ ISCP_ProcessorFamilyIntelCoreDuo = 0x28, ///< Processor Family - Intel Core Duo
+ ISCP_ProcessorFamilyIntelCoreDuoMobile = 0x29, ///< Processor Family - Intel core Duo Mobile
+ ISCP_ProcessorFamilyIntelCoreSoloMobile = 0x2A, ///< Processor Family - Intel Core Solo Mobile
+ ISCP_ProcessorFamilyIntelAtom = 0x2B, ///< Processor Family - Intel Atom
+ ISCP_ProcessorFamilyAlpha = 0x30, ///< Processor Family - Alpha
+ ISCP_ProcessorFamilyAlpha21064 = 0x31, ///< Processor Family - Alpha 21064
+ ISCP_ProcessorFamilyAlpha21066 = 0x32, ///< Processor Family - Alpha 21166
+ ISCP_ProcessorFamilyAlpha21164 = 0x33, ///< Processor Family - Alpha 21164
+ ISCP_ProcessorFamilyAlpha21164PC = 0x34, ///< Processor Family - Alpha 21164PC
+ ISCP_ProcessorFamilyAlpha21164a = 0x35, ///< Processor Family - Alpha 21164a
+ ISCP_ProcessorFamilyAlpha21264 = 0x36, ///< Processor Family - Alpha 21264
+ ISCP_ProcessorFamilyAlpha21364 = 0x37, ///< Processor Family - Alpha 21364
+ ISCP_ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38, ///< Processor Family - AMD Turion II Ultra Dual Core Mobile M
+ ISCP_ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39, ///< Processor Family - AMD Turion II Dual Core Mobile M
+ ISCP_ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A, ///< Processor Family - AMD Athlon II Dual Core M
+ ISCP_ProcessorFamilyAmdOpteron6100Series = 0x3B, ///< Processor Family - AMD Opteron 6100 Series
+ ISCP_ProcessorFamilyAmdOpteron4100Series = 0x3C, ///< Processor Family - AMD Opteron 4100 Series
+ ISCP_ProcessorFamilyAmdOpteron6200Series = 0x3D, ///< Processor Family - AMD Opteron 6200 Series
+ ISCP_ProcessorFamilyAmdOpteron4200Series = 0x3E, ///< Processor Family - AMD Opteron 4200 Series
+ ISCP_ProcessorFamilyAmdFxSeries = 0x3F, ///< Processor Family - AMD FX Series
+ ISCP_ProcessorFamilyMips = 0x40, ///< Processor Family - MIPs
+ ISCP_ProcessorFamilyMIPSR4000 = 0x41, ///< Processor Family - MIPs R4000
+ ISCP_ProcessorFamilyMIPSR4200 = 0x42, ///< Processor Family - MIPs R4200
+ ISCP_ProcessorFamilyMIPSR4400 = 0x43, ///< Processor Family - MIPs R4400
+ ISCP_ProcessorFamilyMIPSR4600 = 0x44, ///< Processor Family - MIPs R4600
+ ISCP_ProcessorFamilyMIPSR10000 = 0x45, ///< Processor Family - MIPs R10000
+ ISCP_ProcessorFamilyAmdCSeries = 0x46, ///< Processor Family - AMD C Series
+ ISCP_ProcessorFamilyAmdESeries = 0x47, ///< Processor Family - AMD E Series
+ ISCP_ProcessorFamilyAmdASeries = 0x48, ///< Processor Family - AMD A Series
+ ISCP_ProcessorFamilyAmdGSeries = 0x49, ///< Processor Family - AMD G Series
+ ISCP_ProcessorFamilyAmdZSeries = 0x4A, ///< Processor Family - AMD Z Series
+ ISCP_ProcessorFamilyAmdRSeries = 0x4B, ///< Processor Family - AMD R Series
+ ISCP_ProcessorFamilyAmdOpteron4300 = 0x4C, ///< Processor Family - AMD Opteron 4300
+ ISCP_ProcessorFamilyAmdOpteron6300 = 0x4D, ///< Processor Family - AMD Opteron 6300
+ ISCP_ProcessorFamilyAmdOpteron3300 = 0x4E, ///< Processor Family - AMD Opteron 3300
+ ISCP_ProcessorFamilyAmdFireProSeries = 0x4F, ///< Processor Family - AMD Fire Pro Series
+ ISCP_ProcessorFamilySparc = 0x50, ///< Processor Family - Sparc
+ ISCP_ProcessorFamilySuperSparc = 0x51, ///< Processor Family - Super Sparc
+ ISCP_ProcessorFamilymicroSparcII = 0x52, ///< Processor Family - Sparc II
+ ISCP_ProcessorFamilymicroSparcIIep = 0x53, ///< Processor Family - Sparc IIep
+ ISCP_ProcessorFamilyUltraSparc = 0x54, ///< Processor Family - Ultra Sparc
+ ISCP_ProcessorFamilyUltraSparcII = 0x55, ///< Processor Family - Ultra Sparc II
+ ISCP_ProcessorFamilyUltraSparcIii = 0x56, ///< Processor Family - Ultra Sparc Iii
+ ISCP_ProcessorFamilyUltraSparcIII = 0x57, ///< Processor Family - Ultra Sparc III
+ ISCP_ProcessorFamilyUltraSparcIIIi = 0x58, ///< Processor Family - Ultra Sparc IIIi
+ ISCP_ProcessorFamily68040 = 0x60, ///< Processor Family - 68040
+ ISCP_ProcessorFamily68xxx = 0x61, ///< Processor Family - 68xxx
+ ISCP_ProcessorFamily68000 = 0x62, ///< Processor Family - 68000
+ ISCP_ProcessorFamily68010 = 0x63, ///< Processor Family - 68010
+ ISCP_ProcessorFamily68020 = 0x64, ///< Processor Family - 68020
+ ISCP_ProcessorFamily68030 = 0x65, ///< Processor Family - 68030
+ ISCP_ProcessorFamilyAmdOpteronASeries = 0x69, ///< Processor Family - AMD Opteron A Series
+ ISCP_ProcessorFamilyHobbit = 0x70, ///< Processor Family - Hobbit
+ ISCP_ProcessorFamilyCrusoeTM5000 = 0x78, ///< Processor Family - Crusoe TM5000
+ ISCP_ProcessorFamilyCrusoeTM3000 = 0x79, ///< Processor Family - Crusoe TM3000
+ ISCP_ProcessorFamilyEfficeonTM8000 = 0x7A, ///< Processor Family - Efficeon TM8000
+ ISCP_ProcessorFamilyWeitek = 0x80, ///< Processor Family - Weitek
+ ISCP_ProcessorFamilyItanium = 0x82, ///< Processor Family - Itanium
+ ISCP_ProcessorFamilyAmdAthlon64 = 0x83, ///< Processor Family - AMD Athlon64
+ ISCP_ProcessorFamilyAmdOpteron = 0x84, ///< Processor Family - AMD Opeteron
+ ISCP_ProcessorFamilyAmdSempron = 0x85, ///< Processor Family - AMD Sempron
+ ISCP_ProcessorFamilyAmdTurion64Mobile = 0x86, ///< Processor Family - AMD Turion 64 Modbile
+ ISCP_ProcessorFamilyDualCoreAmdOpteron = 0x87, ///< Processor Family - AMD Dual Core Opteron
+ ISCP_ProcessorFamilyAmdAthlon64X2DualCore = 0x88, ///< Processor Family - AMD Athlon 64 X2 Dual Core
+ ISCP_ProcessorFamilyAmdTurion64X2Mobile = 0x89, ///< Processor Family - AMD Turion 64 X2 Mobile
+ ISCP_ProcessorFamilyQuadCoreAmdOpteron = 0x8A, ///< Processor Family - AMD Quad Core Opteron
+ ISCP_ProcessorFamilyThirdGenerationAmdOpteron = 0x8B, ///< Processor Family - AMD 3rd Generation Opteron
+ ISCP_ProcessorFamilyAmdPhenomFxQuadCore = 0x8C, ///< Processor Family - AMD Phenom FX Quad Core
+ ISCP_ProcessorFamilyAmdPhenomX4QuadCore = 0x8D, ///< Processor Family - AMD Phenom X4 Quad Core
+ ISCP_ProcessorFamilyAmdPhenomX2DualCore = 0x8E, ///< Processor Family - AMD Phenom X2 Quad Core
+ ISCP_ProcessorFamilyAmdAthlonX2DualCore = 0x8F, ///< Processor Family - AMD Athlon X2 Dual Core
+ ISCP_ProcessorFamilyPARISC = 0x90, ///< Processor Family - PARISC
+ ISCP_ProcessorFamilyPaRisc8500 = 0x91, ///< Processor Family - PARISC 8500
+ ISCP_ProcessorFamilyPaRisc8000 = 0x92, ///< Processor Family - PARISC 8000
+ ISCP_ProcessorFamilyPaRisc7300LC = 0x93, ///< Processor Family - PARISC 7300LC
+ ISCP_ProcessorFamilyPaRisc7200 = 0x94, ///< Processor Family - PARISC 7200
+ ISCP_ProcessorFamilyPaRisc7100LC = 0x95, ///< Processor Family - PARISC 7100LC
+ ISCP_ProcessorFamilyPaRisc7100 = 0x96, ///< Processor Family - PARISC 7100
+ ISCP_ProcessorFamilyV30 = 0xA0, ///< Processor Family - V30
+ ISCP_ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1, ///< Processor Family - Intel Quad Core Xeon 3200 Series
+ ISCP_ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2, ///< Processor Family - Intel Dual Core Xeon 3000 Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3, ///< Processor Family - Intel Quad Core Xeon 5300 Series
+ ISCP_ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4, ///< Processor Family - Intel Dual Core Xeon 5100 Series
+ ISCP_ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5, ///< Processor Family - Intel Dual Core Xeon 5000 Series
+ ISCP_ProcessorFamilyDualCoreIntelXeonLV = 0xA6, ///< Processor Family - Intel Dual Core Xeon LV
+ ISCP_ProcessorFamilyDualCoreIntelXeonULV = 0xA7, ///< Processor Family - Intel Dual Core Xeon ULV
+ ISCP_ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8, ///< Processor Family - Intel Quad Core Xeon 7100 Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9, ///< Processor Family - Intel Quad Core Xeon 5400 Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon = 0xAA, ///< Processor Family - Intel Quad Core Xeon
+ ISCP_ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB, ///< Processor Family - Intel Dual Core Xeon 5200 Series
+ ISCP_ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC, ///< Processor Family - Intel Dual Core Xeon 7200 Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD, ///< Processor Family - Intel Quad Core Xeon 7300 Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE, ///< Processor Family - Intel Quad Core Xeon 7400 Series
+ ISCP_ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF, ///< Processor Family - Intel Multi-Core Xeon 7400 Series
+ ISCP_ProcessorFamilyPentiumIIIXeon = 0xB0, ///< Processor Family - Intel Pentium III Xeon
+ ISCP_ProcessorFamilyPentiumIIISpeedStep = 0xB1, ///< Processor Family - Intel Pentium III Speed Step
+ ISCP_ProcessorFamilyPentium4 = 0xB2, ///< Processor Family - Pentium 4
+ ISCP_ProcessorFamilyIntelXeon = 0xB3, ///< Processor Family - Intel Xeon
+ ISCP_ProcessorFamilyAS400 = 0xB4, ///< Processor Family - AS400
+ ISCP_ProcessorFamilyIntelXeonMP = 0xB5, ///< Processor Family - Intel Xeon MP
+ ISCP_ProcessorFamilyAMDAthlonXP = 0xB6, ///< Processor Family - AMD Athlon XP
+ ISCP_ProcessorFamilyAMDAthlonMP = 0xB7, ///< Processor Family - AMD Athlon MP
+ ISCP_ProcessorFamilyIntelItanium2 = 0xB8, ///< Processor Family - Intel Itanum2
+ ISCP_ProcessorFamilyIntelPentiumM = 0xB9, ///< Processor Family - Intel Pentium M
+ ISCP_ProcessorFamilyIntelCeleronD = 0xBA, ///< Processor Family - Intel Celeron D
+ ISCP_ProcessorFamilyIntelPentiumD = 0xBB, ///< Processor Family - Intel Pentium D
+ ISCP_ProcessorFamilyIntelPentiumEx = 0xBC, ///< Processor Family - Intel pentium Ex
+ ISCP_ProcessorFamilyIntelCoreSolo = 0xBD, ///< Processor Family - Intel Core Solo
+ ISCP_ProcessorFamilyReserved = 0xBE, ///< Processor Family - Reserved
+ ISCP_ProcessorFamilyIntelCore2 = 0xBF, ///< Processor Family - Intel Core 2
+ ISCP_ProcessorFamilyIntelCore2Solo = 0xC0, ///< Processor Family - Intel Core 2 Solo
+ ISCP_ProcessorFamilyIntelCore2Extreme = 0xC1, ///< Processor Family - Intel Core 2 Extreme
+ ISCP_ProcessorFamilyIntelCore2Quad = 0xC2, ///< Processor Family - Intel Core 2 Quad
+ ISCP_ProcessorFamilyIntelCore2ExtremeMobile = 0xC3, ///< Processor Family - Intel Core 2 Extremem Mobile
+ ISCP_ProcessorFamilyIntelCore2DuoMobile = 0xC4, ///< Processor Family - Intel core 2 Duo Mobile
+ ISCP_ProcessorFamilyIntelCore2SoloMobile = 0xC5, ///< Processor Family - Intel Core 2 Solo Mobile
+ ISCP_ProcessorFamilyIntelCoreI7 = 0xC6, ///< Processor Family - Intel Core I7
+ ISCP_ProcessorFamilyDualCoreIntelCeleron = 0xC7, ///< Processor Family - Intel Dual Core Celeron
+ ISCP_ProcessorFamilyIBM390 = 0xC8, ///< Processor Family - IBM 390
+ ISCP_ProcessorFamilyG4 = 0xC9, ///< Processor Family - G4
+ ISCP_ProcessorFamilyG5 = 0xCA, ///< Processor Family - G5
+ ISCP_ProcessorFamilyG6 = 0xCB, ///< Processor Family - G6
+ ISCP_ProcessorFamilyzArchitecture = 0xCC, ///< Processor Family - zArchitecture
+ ISCP_ProcessorFamilyIntelCoreI5 = 0xCD, ///< Processor Family - Intel Core I5
+ ISCP_ProcessorFamilyIntelCoreI3 = 0xCE, ///< Processor Family - Intel Core I3
+ ISCP_ProcessorFamilyViaC7M = 0xD2, ///< Processor Family - Via C7M
+ ISCP_ProcessorFamilyViaC7D = 0xD3, ///< Processor Family - Via C7D
+ ISCP_ProcessorFamilyViaC7 = 0xD4, ///< Processor Family - Via C7
+ ISCP_ProcessorFamilyViaEden = 0xD5, ///< Processor Family - Via Eden
+ ISCP_ProcessorFamilyMultiCoreIntelXeon = 0xD6, ///< Processor Family - Intel Multi-core Xeon
+ ISCP_ProcessorFamilyDualCoreIntelXeon3Series = 0xD7, ///< Processor Family - Intel Dual-core Xeon 3-Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8, ///< Processor Family - Intel Quad-core Xeon 3-Series
+ ISCP_ProcessorFamilyViaNano = 0xD9, ///< Processor Family - Via Nano
+ ISCP_ProcessorFamilyDualCoreIntelXeon5Series = 0xDA, ///< Processor Family - Intel Dual-core Xeon 5-Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB, ///< Processor Family - Intel Quad-core Xeon 5-Series
+ ISCP_ProcessorFamilyDualCoreIntelXeon7Series = 0xDD, ///< Processor Family - Intel Dual-core Xeon 7-Series
+ ISCP_ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE, ///< Processor Family - Intel Quad-core Xeon 7-Series
+ ISCP_ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF, ///< Processor Family - Intel Multi-core Xeon 7-Series
+ ISCP_ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0, ///< Processor Family - Intel Multi-core Xeon 3400-Series
+ ISCP_ProcessorFamilyAmdOpteron3000Series = 0xE4, ///< Processor Family - AMD Opteron 3000 Series
+ ISCP_ProcessorFamilyAmdSempronII = 0xE5, ///< Processor Family - AMD Sempron II
+ ISCP_ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6, ///< Processor Family - AMD Embedded Opteron Quad Core
+ ISCP_ProcessorFamilyAmdPhenomTripleCore = 0xE7, ///< Processor Family - AMD Phonon Triple Core
+ ISCP_ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8, ///< Processor Family - AMD Turion Ultra Dual Core Mobile
+ ISCP_ProcessorFamilyAmdTurionDualCoreMobile = 0xE9, ///< Processor Family - AMD Turion Dual Core Mobile
+ ISCP_ProcessorFamilyAmdAthlonDualCore = 0xEA, ///< Processor Family - AMD Turion Dual Core Mobile
+ ISCP_ProcessorFamilyAmdSempronSI = 0xEB, ///< Processor Family - AMD Sempron SI
+ ISCP_ProcessorFamilyAmdPhenomII = 0xEC, ///< Processor Family - AMD Phenon II
+ ISCP_ProcessorFamilyAmdAthlonII = 0xED, ///< Processor Family - AMD Athlon II
+ ISCP_ProcessorFamilySixCoreAmdOpteron = 0xEE, ///< Processor Family - AMD 6-Core Opteron
+ ISCP_ProcessorFamilyAmdSempronM = 0xEF, ///< Processor Family - AMD Sempon M
+ ISCP_ProcessorFamilyi860 = 0xFA, ///< Processor Family - i860
+ ISCP_ProcessorFamilyi960 = 0xFB, ///< Processor Family - i960
+ ISCP_ProcessorFamilyIndicatorFamily2 = 0xFE, ///< Processor Family - Indicator Family 2
+ ISCP_ProcessorFamilyReserved1 = 0xFF ///< Processor Family - Reserved
+ } ISCP_PROCESSOR_FAMILY_DATA;
+
+ /// Processor Information2 - Processor Family2.
+ typedef enum {
+ ISCP_ProcessorFamilySH3 = 0x0104, ///< ProcessorFamily - SH3
+ ISCP_ProcessorFamilySH4 = 0x0105, ///< ProcessorFamily - SH4
+ ISCP_ProcessorFamilyARM = 0x0118, ///< ProcessorFamily - ARM
+ ISCP_ProcessorFamilyStrongARM = 0x0119, ///< ProcessorFamily - Strong ARM
+ ISCP_ProcessorFamily6x86 = 0x012C, ///< ProcessorFamily - x86
+ ISCP_ProcessorFamilyMediaGX = 0x012D, ///< ProcessorFamily - Media GX
+ ISCP_ProcessorFamilyMII = 0x012E, ///< ProcessorFamily - MII
+ ISCP_ProcessorFamilyWinChip = 0x0140, ///< ProcessorFamily - WinChip
+ ISCP_ProcessorFamilyDSP = 0x015E, ///< ProcessorFamily - DSP
+ ISCP_ProcessorFamilyVideoProcessor = 0x01F4 ///< ProcessorFamily - Video Processor
+ } ISCP_PROCESSOR_FAMILY2_DATA;
+
+ /// Processor Information - Processor Upgrade.
+ typedef enum {
+ ISCP_ProcessorUpgradeOther = 0x01, ///< Processor Upgrade - Other
+ ISCP_ProcessorUpgradeUnknown = 0x02, ///< Processor Upgrade - Unknown
+ ISCP_ProcessorUpgradeDaughterBoard = 0x03, ///< Processor Upgrade - Daughter Board
+ ISCP_ProcessorUpgradeZIFSocket = 0x04, ///< Processor Upgrade - ZIF Socket
+ ISCP_ProcessorUpgradePiggyBack = 0x05, ///< Processor Upgrade - Piggyback
+ ISCP_ProcessorUpgradeNone = 0x06, ///< Processor Upgrade - None
+ ISCP_ProcessorUpgradeLIFSocket = 0x07, ///< Processor Upgrade - LIF Socket
+ ISCP_ProcessorUpgradeSlot1 = 0x08, ///< Processor Upgrade - Slot 1
+ ISCP_ProcessorUpgradeSlot2 = 0x09, ///< Processor Upgrade - Slot 2
+ ISCP_ProcessorUpgrade370PinSocket = 0x0A, ///< Processor Upgrade - 370 Pin Socket
+ ISCP_ProcessorUpgradeSlotA = 0x0B, ///< Processor Upgrade - Slot A
+ ISCP_ProcessorUpgradeSlotM = 0x0C, ///< Processor Upgrade - Slot M
+ ISCP_ProcessorUpgradeSocket423 = 0x0D, ///< Processor Upgrade - Socket 423
+ ISCP_ProcessorUpgradeSocketA = 0x0E, ///< Processor Upgrade - Socket A
+ ISCP_ProcessorUpgradeSocket478 = 0x0F, ///< Processor Upgrade - Socket 478
+ ISCP_ProcessorUpgradeSocket754 = 0x10, ///< Processor Upgrade - Socket 754
+ ISCP_ProcessorUpgradeSocket940 = 0x11, ///< Processor Upgrade - Socket 940
+ ISCP_ProcessorUpgradeSocket939 = 0x12, ///< Processor Upgrade - Socket 939
+ ISCP_ProcessorUpgradeSocketmPGA604 = 0x13, ///< Processor Upgrade - PGA 604
+ ISCP_ProcessorUpgradeSocketLGA771 = 0x14, ///< Processor Upgrade - LGA 771
+ ISCP_ProcessorUpgradeSocketLGA775 = 0x15, ///< Processor Upgrade - LGA 775
+ ISCP_ProcessorUpgradeSocketS1 = 0x16, ///< Processor Upgrade - S1
+ ISCP_ProcessorUpgradeAM2 = 0x17, ///< Processor Upgrade - AM2
+ ISCP_ProcessorUpgradeF1207 = 0x18, ///< Processor Upgrade - F1207
+ ISCP_ProcessorSocketLGA1366 = 0x19, ///< Processor Upgrade - LGA 1366
+ ISCP_ProcessorUpgradeSocketG34 = 0x1A, ///< Processor Upgrade - G34
+ ISCP_ProcessorUpgradeSocketAM3 = 0x1B, ///< Processor Upgrade - AM3
+ ISCP_ProcessorUpgradeSocketC32 = 0x1C, ///< Processor Upgrade - C32
+ ISCP_ProcessorUpgradeSocketLGA1156 = 0x1D, ///< Processor Upgrade - LGA 1156
+ ISCP_ProcessorUpgradeSocketLGA1567 = 0x1E, ///< Processor Upgrade - LGA 1567
+ ISCP_ProcessorUpgradeSocketPGA988A = 0x1F, ///< Processor Upgrade - PGA 988A
+ ISCP_ProcessorUpgradeSocketBGA1288 = 0x20, ///< Processor Upgrade - PGA 1288
+ ISCP_ProcessorUpgradeSocketrPGA988B = 0x21, ///< Processor Upgrade - PGA 988B
+ ISCP_ProcessorUpgradeSocketBGA1023 = 0x22, ///< Processor Upgrade - BGA 1023
+ ISCP_ProcessorUpgradeSocketBGA1224 = 0x23, ///< Processor Upgrade - BGA 1224
+ ISCP_ProcessorUpgradeSocketLGA1155 = 0x24, ///< Processor Upgrade - LGA 1155
+ ISCP_ProcessorUpgradeSocketLGA1356 = 0x25, ///< Processor Upgrade - LGA 1356
+ ISCP_ProcessorUpgradeSocketLGA2011 = 0x26, ///< Processor Upgrade - LGA 2011
+ ISCP_ProcessorUpgradeSocketFS1 = 0x27, ///< Processor Upgrade - FS1
+ ISCP_ProcessorUpgradeSocketFS2 = 0x28, ///< Processor Upgrade - FS2
+ ISCP_ProcessorUpgradeSocketFM1 = 0x29, ///< Processor Upgrade - FM1
+ ISCP_ProcessorUpgradeSocketFM2 = 0x2A, ///< Processor Upgrade - FM2
+ ISCP_ProcessorUpgradeSocketLGA2011_3 = 0x2B, ///< Processor Upgrade - LGA 2011-3
+ ISCP_ProcessorUpgradeSocketLGA1356_3 = 0x2C ///< Processor Upgrade - LGA 1356-3
+ } ISCP_PROCESSOR_UPGRADE;
+
+ /// CPU Information - Characteristics.
+ typedef struct {
+ UINT16 Reserved0 :1; ///< CPU Information - Reserved
+ UINT16 Unknown :1; ///< CPU Information - Unknown
+ UINT16 Capable64Bit :1; ///< CPU Information - Capable 64-Bit
+ UINT16 MultiCore :1; ///< CPU Information - Multi-core
+ UINT16 HardwareThread :1; ///< CPU Information - Hardware Thread
+ UINT16 ExecuteProtection :1; ///< CPU Information - Execute Protection
+ UINT16 EnhancedVirtualization :1; ///< CPU Information - Enhanced Virtualization
+ UINT16 PowerPerformanceControl :1; ///< CPU Information - Power Performance Control
+ UINT16 Reserved8_15 :8; ///< CPU Information - Reserved
+ } ISCP_PROCESSOR_CHARACTERISTICS;
+
+ /// CPU Information - CPU Status.
+ typedef enum {
+ ISCP_CPU_STATUS_UNKNOWN = 0, ///< CPU Status - Unknown
+ ISCP_CPU_STATUS_ENABLED, ///< CPU Status - Enabled
+ ISCP_CPU_STATUS_DISABLED_BY_USER, ///< CPU Status - Disabled by user
+ ISCP_CPU_STATUS_DISABLED_BY_BIOS, ///< CPU Status - Disabled by BIOS
+ ISCP_CPU_STATUS_IDLE, ///< CPU Status - Idle
+ ISCP_CPU_STATUS_RESERVED_5, ///< CPU Status - Reserved
+ ISCP_CPU_STATUS_RESERVED_6, ///< CPU Status - Reserved
+ ISCP_CPU_STATUS_OTHER ///< CPU Status - Other
+ } ISCP_CPU_STATUS;
+
+
+ /// CPU Information - Status.
+ typedef struct {
+ UINT16 CpuStatus :3; ///< CPU Status
+ UINT16 Reserved3_5 :3; ///< Reserved Bits[5:3]
+ UINT16 CpuSocketPopulated :1; ///< CPU Socket Populated
+ UINT16 Reserved7_15 :9; ///< Reserved Bits[15:9]
+ } PROCESSOR_STATUS;
+
+ /// Cache Information - Operation Mode.
+ typedef enum {
+ ISCP_CACHE_OPERATION_MODE_WRITE_THROUGH = 0, ///< Cache Operation Mode Write Through
+ ISCP_CACHE_OPERATION_MODE_WRITE_BACK, ///< Cache Operation Mode Write Back
+ ISCP_CACHE_OPERATION_MODE_VARIES_WITH_MEMORY_ADDRESS, ///< Cache Operation Mode Varies with Memory Address
+ ISCP_CACHE_OPERATION_MODE_UNKNOWN, ///< Cache Operation Mode Unknown
+ } ISCP_CACHE_OPERATION_MODE;
+
+ /// Cache Information - Location.
+ typedef enum {
+ ISCP_CACHE_LOCATION_INTERNAL = 0, ///< Cache Location Internal
+ ISCP_CACHE_LOCATION_EXTERNAL, ///< Cache Location External
+ ISCP_CACHE_LOCATION_RESERVED, ///< Cache Location Reserved
+ ISCP_CACHE_LOCATION_UNKNOWN, ///< Cache Location Unknown
+ } ISCP_CACHE_LOCATION;
+
+ /// Cache Information - Level.
+ typedef enum {
+ ISCP_CACHE_LEVEL_1 = 0, ///< Cache Level 1
+ ISCP_CACHE_LEVEL_2, ///< Cache Level 2
+ ISCP_CACHE_LEVEL_3, ///< Cache Level 3
+ ISCP_CACHE_LEVEL_4, ///< Cache Level 4
+ } ISCP_CACHE_LEVEL;
+
+ /// Cache Information - Configuration.
+ typedef struct {
+ UINT16 CacheLevel :3; ///< Cache Level
+ UINT16 CacheSocketd :1; ///< Cache Socket ID
+ UINT16 Reserved_4 :1; ///< Cache Reserved
+ UINT16 Location :2; ///< Cache Location
+ UINT16 EnabledDisabled :1; ///< Cache Enabled / Disabled
+ UINT16 OperationMode :2; ///< Operation Mode
+ UINT16 Reserved10_15 :6; ///< Cache Reserved
+ } ISCP_CACHE_CONFIGURATION;
+
+ /// Cache Information - SRAM Type.
+ typedef struct {
+ UINT16 Other :1; ///< SRAM Type - Other
+ UINT16 Unknown :1; ///< SRAM Type - Unknown
+ UINT16 NonBurst :1; ///< SRAM Type - NonBurst
+ UINT16 Burst :1; ///< SRAM Type - Burst
+ UINT16 PipelineBurst :1; ///< SRAM Type - Pipeline Burst
+ UINT16 Synchronous :1; ///< SRAM Type - Synchronous
+ UINT16 Asynchronous :1; ///< SRAM Type - Asynchronous
+ UINT16 Reserved7_15 :9; ///< SRAM Type - Reserved
+ } ISCP_CACHE_SRAM_TYPE;
+
+ /// Cache Information - Error Correction Type.
+ typedef enum {
+ ISCP_ECC_TYPE_OTHER = 1, ///< ECC Type - Other
+ ISCP_ECC_TYPE_UNKNOWN, ///< ECC Type - Unknown
+ ISCP_ECC_TYPE_NONE, ///< ECC Type - None
+ ISCP_ECC_TYPE_PARITY, ///< ECC Type - Parity
+ ISCP_ECC_TYPE_SINGLE_BIT, ///< ECC Type - Single-Bit
+ ISCP_ECC_TYPE_MULTI_BIT ///< ECC Type - Multi-Bit
+ } ISCP_CACHE_ECC_TYPE;
+
+ /// Cache Information - System Cache Type.
+ typedef enum {
+ ISCP_SYSTEM_CACHE_TYPE_OTHER = 1, ///< System Cache Type - Other
+ ISCP_SYSTEM_CACHE_TYPE_UNKNOWN, ///< System Cache Type - Unknown
+ ISCP_SYSTEM_CACHE_TYPE_INSTRUCTION, ///< System Cache Type - Instruction
+ ISCP_SYSTEM_CACHE_TYPE_DATA, ///< System Cache Type - Data
+ ISCP_SYSTEM_CACHE_TYPE_UNIFIED ///< System Cache Type - Unified
+ } ISCP_SYSTEM_CACHE_TYPE;
+
+ /// Cache Information - Associativity.
+ typedef enum {
+ ISCP_CACHE_ASSOCIATIVITY_OTHER = 1, ///< Cache Associativity - Other
+ ISCP_CACHE_ASSOCIATIVITY_UNKNOWN, ///< Cache Associativity - Unknown
+ ISCP_CACHE_ASSOCIATIVITY_DIRECT_MAPPED, ///< Cache Associativity - Direct Mapped
+ ISCP_CACHE_ASSOCIATIVITY_2_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 2-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_4_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 4-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_FULLY_ASSOCIATIVE, ///< Cache Associativity - Fully Assciative
+ ISCP_CACHE_ASSOCIATIVITY_8_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 8-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_16_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 16-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_12_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 12-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_24_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 24-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_32_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 32-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_48_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 48-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_64_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 64-way Set Assciative
+ ISCP_CACHE_ASSOCIATIVITY_20_WAY_SET_ASSOCIATIVE ///< Cache Associativity - 20-way Set Assciative
+ } ISCP_CACHE_ASSOCIATIVITY;
+
+ /// DMI TYPE 4 - CPU Information
+ typedef struct {
+ UINT16 T4ProcType; ///< Processor Type
+ UINT16 T4ProcFamily; ///< Processor Family
+ ISCP_PROC_ID T4ProcId; ///< Processor Id
+ UINT16 T4Voltage; ///< Processor Voltage
+ UINT16 T4ExternalClock; ///< Processor External Clock
+ UINT16 T4MaxSpeed; ///< Processor Maximum Speed
+ UINT16 T4CurrentSpeed; ///< Processor Current Speed
+ UINT16 T4Status; ///< Processor Status
+ UINT16 T4ProcUpgrade; ///< Processor Upgrade
+ UINT16 T4CoreCount; ///< Processor Core Count
+ UINT16 T4CoreEnabled; ///< Processor Core Enabled
+ UINT16 T4ThreadCount; ///< Processor Thread Count
+ UINT16 T4ProcCharacteristics; ///< Processor Characteristics
+ UINT16 T4ProcFamily2; ///< Processor Family 2
+ UINT16 T4CoreCount2; ///< Processor Core Count 2
+ UINT16 T4CoreEnabled2; ///< Processor Core Enabled 2
+ UINT16 T4ThreadCount2; ///< Processor Thread Count 2
+ UINT8 T4SerialNumber[8]; ///< Processor Serial Number
+ } ISCP_TYPE4_SMBIOS_INFO;
+
+ /// DMI Type 7 - Cache Information
+ typedef struct {
+ UINT16 T7CacheCfg; ///< Cache Configuration
+ UINT16 T7MaxCacheSize; ///< Maximum Cache Size
+ UINT16 T7InstallSize; ///< Cache Install Size
+ UINT16 T7SupportedSramType; ///< Supported SRAM Type
+ UINT16 T7CurrentSramType; ///< Current SRAM Type
+ UINT16 T7CacheSpeed; ///< Cache Speed in nanoseconds
+ UINT16 T7ErrorCorrectionType; ///< Cache Error Correction Type
+ UINT16 T7SystemCacheType; ///< System Cache Type
+ UINT16 T7Associativity; ///< Cache Associativity
+ } ISCP_TYPE7_SMBIOS_INFO;
+
+ #ifdef __cplusplus
+ }
+#endif
+
+
+#endif /* CPUISCP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Iscp.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Iscp.h new file mode 100644 index 0000000..30f8c65 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Iscp.h @@ -0,0 +1,400 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * Iscp.h
+ *
+ * Contains common ISCP-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+// NOTE: This file shared between SCP and UEFI, make sure all //
+// changes are reflected in both copies. //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef ISCP_H_
+#define ISCP_H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+ #include "SocConfiguration.h"
+ #include "IscpConfig.h"
+ #include "CoreState.h"
+ #include "MemSetup.h"
+ #include "MemIscp.h"
+ #include "UartLineSettings.h"
+ #include "CpuIscp.h"
+ #include "NetworkAddress.h"
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// *** NOTE: This controls the size of a queue in SRAM. This is the
+// maximum number of elements that will fit, without changing the
+// overall SRAM layout.
+#define ISCP_ECC_EVENT_QUEUE_SIZE 8
+
+ /// Types of ECC errors
+ typedef enum _ECC_FAIL_TYPE {
+ ECC_FAIL_NO_ERROR = 0, ///< ECC No Error
+ ECC_FAIL_CORRECTABLE, ///< ECC Multiple Correctable Error
+ ECC_FAIL_CORRECTABLE_MULTIPLE, ///< ECC Correctable Multiple Error
+ ECC_FAIL_UNCORRECTABLE, ///< ECC Correctable Error
+ ECC_FAIL_UNCORRECTABLE_MULTIPLE, ///< ECC Uncorrectable Multiple Error
+ ECC_FAIL_PARITY, ///< ECC Parity Error
+ ECC_FAIL_END ///< End of ECC Fail Types
+ } ECC_FAIL_TYPE;
+
+ /// ISCP ECC error events
+ typedef struct _ISCP_ECC_EVENT_DETAILS {
+ UINT64 Address; ///< Address
+ UINT64 PhysicalAddress; ///< DRAM Physical Address
+ UINT64 Data; ///< Data
+ UINT32 Channel; ///< DRAM Channel
+ UINT32 SourceId; ///< Scource ID
+ UINT32 Syndrome; ///< ECC Syndrome
+ UINT32 Type; ///< Restricted to ECC_FAIL_TYPE values
+ UINT32 Module; ///< DRAM Module
+ UINT32 Bank; ///< DRAM Bank
+ UINT32 Row; ///< DRAM Row
+ UINT32 Column; ///< DRAM Column
+ } ISCP_ECC_EVENT_DETAILS;
+
+ /// ISCP Block Transfer Memory Buffer
+ typedef struct {
+ UINT64 BuffAddress; ///< 64-Bit Communication Buffer Address
+ UINT64 BufferSize; ///< 64-Bit Communication Buffer Size
+ } BLOCK_TRANSFER_BUFFER;
+
+ /// ISCP Data Window
+ typedef struct {
+ union {
+ UINT8 szData[248]; ///< 8-bit ISCP data array
+ BLOCK_TRANSFER_BUFFER BlockTransferBuffer; ///< ISCP Memory block Transfer Buffer structure
+ } Data;
+ } DATA_WINDOW;
+
+ /// ISCP Communication Block. This structure must fit within the 4K SRAM area.
+ typedef struct {
+ UINT32 Signature; ///< Command Signature
+ UINT8 BlockLength; ///< Block Length of the entire message
+ UINT8 RequestCode; ///< Request Code - Operation Requested by the recipient
+ UINT8 ResponseCode; ///< Response Code - Response Code from recipient
+ UINT8 DataLength; ///< Data Length - Length in bytes of data
+ ///< being transmitted, zero if MEMORY_BUFFER is used
+ DATA_WINDOW DataWin; ///< Data Window Union (This completes the 256 byte header)
+ UINT8 ExtraPayload[3072]; ///< Reserved for large payloads (A maximum of 3K)
+ ISCP_ECC_EVENT_DETAILS FatalEccEvent; ///< Only one fatal ECC error event needed (56 bytes)
+ ISCP_ECC_EVENT_DETAILS EccEventList[ISCP_ECC_EVENT_QUEUE_SIZE]; ///< List of ECC error events (448 bytes, which nearly finishes the 4K area)
+ UINT8 HeadIndex; ///< Index of first ECC event, when head == tail queue is empty
+ UINT8 TailIndex; ///< Index of empty queue entry, to be filled next.
+ UINT8 Overflow; ///< Indicates a queue overflow, saturates at 0xFF
+ } ISCP_COMM_BLOCK __attribute__ ((__aligned__ (64)));
+
+ /// Memory info HOB structure
+ typedef struct {
+ UINT32 Version; ///< Version of HOB structure
+ UINT32 NumberOfDescriptor; ///< Number of memory range descriptor
+ AMD_MEMORY_RANGE_DESCRIPTOR Ranges; ///< Memory ranges
+ } ISCP_MEMORY_INFO;
+
+ /// SMBIOS Memory Buffer structure
+ typedef struct {
+ ISCP_TYPE16_SMBIOS_INFO T16; ///< SMBIOS Type 16 Record Data
+ ISCP_TYPE17_SMBIOS_INFO T17[2][2]; ///< SMBIOS Type 17 Record Data
+ ISCP_TYPE19_SMBIOS_INFO T19; ///< SMBIOS Type 19 Record Data
+ } AMD_SMBIOS_MEM_BUFFER;
+
+ /// SMBIOS CPU Buffer structure
+ typedef struct {
+ ISCP_TYPE4_SMBIOS_INFO T4[1]; ///< SMBIOS Type 4 Record Data
+ ISCP_TYPE7_SMBIOS_INFO T7L1[1]; ///< SMBIOS Type 7 Level 1 Cache Record Data
+ ISCP_TYPE7_SMBIOS_INFO T7L2[1]; ///< SMBIOS Type 7 Level 2 Cache Record Data
+ ISCP_TYPE7_SMBIOS_INFO T7L3[1]; ///< SMBIOS Type 7 Level 3 Cache Record Data
+ } AMD_SMBIOS_CPU_BUFFER;
+
+ /// SMBIOS Buffer structure
+ typedef struct {
+ AMD_SMBIOS_MEM_BUFFER SmbiosMemBuffer; ///< SMBIOS Memory Buffer
+ AMD_SMBIOS_CPU_BUFFER SmbiosCpuBuffer; ///< SMBIOS CPU Buffer
+ } ISCP_SMBIOS_INFO;
+
+ /// NV Data structure
+ typedef struct {
+ UINT32 Version; ///< Version of NV data structure
+ UINT32 FvOffset; ///< Offset from the base of the UEFI image
+ UINT32 FvSize; ///< Firmware Volume Data Size to be written, read, or erased
+ UINT8 FvData[64*1024]; ///< Firmware Volume Data block
+ } ISCP_OEM_NV_INFO;
+
+ /// Firmware Fuse Buffer structure
+ typedef struct {
+ UINT32 Version; ///< Version of Fuse Info Buffer structure
+ SocConfiguration SocConfiguration; ///< Fuse Structure to be passed to UEFI
+ } ISCP_FUSE_INFO;
+
+ /// Firmware CPU Reset Buffer structure
+ typedef struct {
+ UINT32 Version; ///< Version of CPU reset Buffer structure
+ UINT32 CoreNum; ///< The core number we want data for, e.g. 0,1,2,..
+ SocCoreStatus CoreStatus; ///< Core Status Structure
+ } ISCP_CPU_RESET_INFO;
+
+ /// Firmware MAC Address structure
+ typedef struct {
+ UINT32 Version; ///< Version of MAC address Info Buffer structure
+ UINT8 MacAddress0[6]; ///< MAC Address 0 10Gb Ethernet port 0
+ UINT8 MacAddress1[6]; ///< MAC Address 1 10Gb Ethernet port 1
+ UINT8 MacAddress2[6]; ///< MAC Address 2 1Gb Ethernet
+ } ISCP_MAC_INFO;
+
+ /// ISCP RTC Time structure (Based on subset of EFI_TIME structure)
+ typedef struct {
+ UINT32 Version; ///< Version of RTC Info Buffer structure
+ UINT16 Year; ///< Year: 2000 - 20XX
+ UINT8 Month; ///< Month: 1 - 12
+ UINT8 Day; ///< Day: 1 - 31
+ UINT8 Hour; ///< Hour: 0 - 23
+ UINT8 Minute; ///< Minute: 0 - 59
+ UINT8 Second; ///< Second: 0 - 59
+ UINT8 Pad; ///< Padding to made structure 32-bit aligned
+ } ISCP_RTC_INFO;
+
+ /// ISCP PCIE Reset structure
+ typedef struct {
+ UINT32 Version; ///< Version of PCIE reset Buffer structure
+ UINT8 ResetSeq; ///< Sequence of Reset
+ UINT16 SVID; ///< VRM value / Voltage
+ } ISCP_PCIE_RESET_INFO;
+
+ /// ISCP Ready To Boot structure
+ typedef struct {
+ UINT32 Version; ///< Version of Ready To Boot
+ UINT8 ReadyToBoot; ///< Signal Ready To Boot Event
+ } ISCP_READY_TO_BOOT_INFO;
+
+ /// ISCP BMC IP Address structure
+ typedef struct {
+ UINT32 Version; ///< Version of BMC IP Address
+ ISCP_BMC_IPV4_ADDRESS Ipv4Address; ///< BMC IPv4 Address Structure
+ ISCP_BMC_IPV6_ADDRESS Ipv6Address; ///< BMC IPv6 Address Structure
+ } ISCP_BMC_IP_ADDRESS_INFO;
+
+ /// EEPROM info structure
+ typedef struct {
+ UINT32 Version; ///< Version of EEPROM Info structure
+ UINT32 EepromOffset; ///< EEPROM Offset from the base of the UEFI image
+ UINT32 EepromSize; ///< EEPROM Data Size to be written, read, or erased
+ UINT32 EepromArea; ///< EEPROM Area to be affected by read, write,erase commands
+ UINT8 EepromData[64*1024]; ///< EEPROm Data block [64K]
+ } ISCP_EEPROM_INFO;
+
+ /// UART info structure. The legal values for these fields are in UartLineSettings.h and are
+ /// shared between the SCP and UEFI.
+ typedef struct {
+ UINT32 Version; ///< Version of UART Info structure
+ UART_LINE_SETTINGS A57UartConfig; ///< A57 UART Config
+ } ISCP_UART_INFO;
+
+ /// Override Command structure
+ typedef struct {
+ UINT32 Version; ///< Version of Override Command structure
+ UINT8 Command; ///< Override command
+ } ISCP_OVERRIDE_CMD_INFO;
+
+ /// SATA1 reset structure
+ typedef struct {
+ UINT32 Version; ///< Version of SATA en/disable structure
+ UINT8 State; ///< Enable/Disable state
+ } ISCP_SATA1_RESET_INFO;
+
+ /// BMC presence structure
+ typedef struct {
+ UINT32 Version; ///< Version of BMC presence structure
+ UINT8 BmcPresent; ///< BMC presence
+ } ISCP_BMC_PRESENCE_INFO;
+
+ /// BERT Region structure
+ typedef struct {
+ UINT32 IscpVersion; ///< Version of BERT Region structure
+ UINT64 RegionPhysAddr; ///< ACPI v6.0: Table 18-319 [Boot Error Region]
+ UINT32 RegionLength; ///< ACPI v6.0: Table 18-319 [Boot Error Region Length]
+ } ISCP_BERT_REGION_INFO;
+
+ /// SCP Doorbell Record structure
+ typedef struct {
+ UINT32 IscpVersion; ///< Version of Doorbell Info structure
+ UINT32 ToggleRateMilliSec; ///< Doorbell Toggle Rate
+ } ISCP_SCP_DOORBELL_INFO;
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define ISCP_TIMEOUT (1000000)
+
+// Request Codes
+#define ISCP_TRANSACTION_SUCCESS (0x00)
+
+#define ISCP_REQ_MEMORY (0x03)
+#define ISCP_RETRIEVE_SETUP (0x04)
+#define ISCP_STORE_SETUP (0x05)
+#define ISCP_FUSE_BLOB (0x07)
+#define ISCP_CPU_RETRIEVE_ID (0x09)
+#define ISCP_CPU_RESET (0x0A)
+#define ISCP_REQ_OEM_NV (0x0B)
+#define ISCP_STORE_OEM_NV (0x0C)
+#define ISCP_ERASE_OEM_NV (0x0D)
+#define ISCP_GET_MAC_ADDRESS (0x0E)
+#define ISCP_SET_MAC_ADDRESS (0x0F)
+#define ISCP_REQ_RTC (0x10)
+#define ISCP_SET_RTC (0x11)
+#define ISCP_GET_SMBIOS (0x12)
+#define ISCP_RESET_PCIE (0x13)
+#define ISCP_READY_TO_BOOT (0x14)
+#define ISCP_GET_BMC_IP (0x15)
+#define ISCP_RETRIEVE_VERSION (0x16)
+#define ISCP_STORE_EEPROM (0x17)
+#define ISCP_REQ_EEPROM (0x18)
+#define ISCP_ERASE_EEPROM (0x19)
+#define ISCP_MEM_SETUP (0x1A)
+#define ISCP_SEND_UART_CONFIG (0x1C)
+#define ISCP_OVERRIDE_CMD (0x1D)
+#define ISCP_SATA1_GET (0x1E)
+#define ISCP_SATA1_SET (0x1F)
+#define ISCP_BMC_PRESENT (0x20)
+#define ISCP_RETRIEVE_BERT_RECORD (0x21)
+#define ISCP_SUBMIT_BERT_RECORD (0x22)
+#define ISCP_POWER_OFF (0xAA)
+#define ISCP_SYSTEM_RESET (0xBB)
+
+// Response Codes
+#define ISCP_TRANSACTION_SUCCESS (0x00)
+#define ISCP_UNSUCCESSFUL (0x01)
+#define ISCP_INVALID (0x02)
+#define ISCP_SIGNATURE_NOT_FOUND (0x03)
+#define ISCP_NOT_SUPPORTED (0x04)
+#define ISCP_INVALID_BLOCK_LENGTH (0x05)
+#define ISCP_INVALID_REQUEST_CODE (0x06)
+#define ISCP_INVALID_DATA_LENGTH (0x07)
+#define ISCP_NV_WRITE_FAIL (0x0A)
+#define ISCP_NV_READ_FAIL (0x0B)
+#define ISCP_NV_ERASE_FAIL (0x0C)
+#define ISCP_SETUP_READ_FAIL (0x0D)
+#define ISCP_SETUP_WRITE_FAIL (0x0E)
+#define ISCP_EE_WRITE_FAIL (0x0F)
+#define ISCP_EE_READ_FAIL (0x10)
+#define ISCP_EE_ERASE_FAIL (0x11)
+#define ISCP_SMBIOS_FAIL (0x12)
+#define ISCP_INVALID_RESPONSE_CODE (0xFF)
+
+// ISCP Signatures
+#define BOOT_CORE_SIG (0x524F4342) //"BCOR" spelled backwards - Boot Core
+#define BERT_SIG (0x54524542) //"BERT" spelled backwards - BERT Error Block Buffer Address
+#define BMC_PRESENT_SIG (0x50434D42) //"BMCP" spelled backwards - BMC Present
+#define BMC_IP_ADDR_SIG (0x50494D42) //"BMIP" spelled backwards - BMC IP Address
+#define CPU_MP_SIG (0x4D555043) //"CPUM" spelled backwards - CPU Reset
+#define DOORBELL_SIG (0x4C454244) //"DBEL" spelled backwards - Doorbell
+#define EEPROM_SIG (0x52504545) //"EEPR" spelled backwards - EEPROM
+#define FUSE_BLOB_SIG (0x45535546) //"FUSE" spelled backwards - Fuse blob
+#define HOBS_SIG (0x53424F48) //"HOBS" spelled backwards - Memory HOBs buffer
+#define GET_MAC_ADDR_SIG (0x4143414D) //"MACA" spelled backwards - Get MAC Address
+#define OEM_NV_SIG (0x564E454F) //"OENV" spelled backwards - OEM NV Storage save and retrieval actions
+#define OVERRIDE_CMD_SIG (0x4452564F) //"OVRD" spelled backwards - Override Command
+#define PCIE_SIG (0x45494350) //"PCIE" spelled backwards - PCIE Reset
+#define READY2BOOT_SIG (0x54425452) //"RTBT" spelled backwards - Ready-To-Boot
+#define RTC_SIG (0x4B435452) //"RTCK" spelled backwards - Real-Time-Clock
+#define SATA1_GET_SIG (0x47544153) //"SATG" spelled backwards - SATA 1 get state
+#define SATA1_SET_SIG (0x53544153) //"SATS" spelled backwards - SATA 1 set state
+#define SETUP_SIG (0x55544553) //"SETU" spelled backwards - BIOS Setup
+#define SHUTDOWN_SIG (0x4E444853) //"SHDN" spelled backwards - System Shutdown
+#define SET_MAC_ADDR_SIG (0x43414D53) //"SMAC" spelled backwards - Set MAC Address
+#define SMBIOS_SIG (0x534D4253) //"SMBS" spelled backwards - SMBIOS
+#define UART_SIG (0x54524155) //"UART" spelled backwards - UART Config
+
+
+#define ISCP_BERT_REGION_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_BMC_PRESENT_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_BMC_IP_ADDR_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#define ISCP_CPU_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_DOORBELL_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_EEPROM_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#define ISCP_FUSE_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#define ISCP_MEMORY_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#define ISCP_MAC_INFO_VERSION (0x00000002ul) ///< Ver: 00.00.00.02
+#define ISCP_OEM_NV_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_OVERRIDE_CMD_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_PCIE_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_READY2BOOT_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_RTC_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+
+#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
+#define ISCP_SATA1_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+#endif
+
+#define ISCP_UART_CONFIG_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
+
+#define ISCP_COMM_BLK_MAX_SIZE (0x100) ///< Max length of ISCP communication block, 256 bytes
+#define MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR (2)
+#define MAX_SIZEOF_AMD_MEMORY_INFO_HOB_BUFFER (sizeof (ISCP_MEM_HOB) + \
+ (MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR * sizeof (AMD_MEMORY_RANGE_DESCRIPTOR)))
+#define MAX_SIZEOF_AMD_SETUP_BUFFER (sizeof (ISCP_SETUP_INFO))
+#define MAX_SIZEOF_AMD_SMBIOS_BUFFER (sizeof (AMD_ISCP_SMBIOS_INFO))
+
+#define FOREVER for (;;)
+#define USE_DRAM_BUFFER (0x00)
+#define ISCP_BLOCK_LENGTH (0x08)
+
+ #ifdef __cplusplus
+ }
+#endif
+
+#endif /* ISCP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/IscpConfig.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/IscpConfig.h new file mode 100644 index 0000000..cac451a --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/IscpConfig.h @@ -0,0 +1,63 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * IscpConfig.h
+ *
+ * Contains Intra-SoC Communication Protocol configuration definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+#ifndef ISCP_CONFIG_H_
+#define ISCP_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+ #include <ProcessorBind.h> // Included just so this file can be built into both the RTOS
+ // and UEFI without needing separate copies for both build
+ // environments.
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Door Bell Flag Register
+#define ISCP_DRAM_BUFFER_ADDR_REG_LO (0xE0000008UL)
+#define ISCP_DRAM_BUFFER_ADDR_REG_HI (0xE000000CUL)
+#define ISCP_BUFFER_SIZE (0x1000)
+#define DOORBELL_OFFSET_NS (0x100)
+#define DOORBELL_BIT_NS (UINT32) (1 << 7) // Door Bell bit = [GPIO_1 (Line 14)]
+#define DOORBELL_BIT_SEC (UINT32) (1 << 7) // Door Bell bit = [GPIO_1 (Line 15)]
+
+ #ifdef __cplusplus
+ }
+#endif
+
+
+#endif /* ISCP_CONFIG_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemIscp.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemIscp.h new file mode 100644 index 0000000..68cd0ec --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemIscp.h @@ -0,0 +1,174 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * MemIscp.h
+ *
+ * Contains common Memory Training ISCP-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+// NOTE: This file shared between SCP and UEFI, make sure all //
+// changes are reflected in both copies. //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef MEMISCP_H_
+#define MEMISCP_H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+ /// Memory Attribute enum
+ typedef enum {
+ MEM_AVAILABLE = 1, ///< Memory Available
+ MEM_RESERVED, ///< Memory Reserved
+ MEM_ACPI, ///< Memory ACPI
+ MEM_NVS, ///< Memory NVS
+ MEM_UNUSABLE ///< Memory Unavailable
+ } MEMORY_ATTRIBUTE;
+
+ /// Memory descriptor structure for each memory range
+ typedef struct {
+ UINT64 Base0; ///< Base address of memory range 0
+ UINT64 Size0; ///< Size of memory range 0
+ MEMORY_ATTRIBUTE Attribute0; ///< Attribute of memory range 0
+ UINT32 Padding0; ///< 4-byte Padding to get 8-byte alignment
+ UINT64 Base1; ///< Base address of memory range 1
+ UINT64 Size1; ///< Size of memory range 1
+ MEMORY_ATTRIBUTE Attribute1; ///< Attribute of memory range 1
+ UINT32 Padding1; ///< 4-byte Padding to get 8-byte alignment
+ UINT64 Base2; ///< Base address of memory range 2
+ UINT64 Size2; ///< Size of memory range 2
+ MEMORY_ATTRIBUTE Attribute2; ///< Attribute of memory range 2
+ UINT32 Padding2; ///< 4-byte Padding to get 8-byte alignment
+ UINT64 Base3; ///< Base address of memory range 3
+ UINT64 Size3; ///< Size of memory range 3
+ MEMORY_ATTRIBUTE Attribute3; ///< Attribute of memory range 3
+ UINT32 Padding3; ///< 4-byte Padding to get 8-byte alignment
+ } AMD_MEMORY_RANGE_DESCRIPTOR;
+
+ /// SMBIOS Structure Header
+ typedef struct {
+ UINT8 Type; ///< TYPE
+ UINT8 Length; ///< Length of TYPE
+ UINT16 Handle; ///< structure handle, a unique 16-bit number in the range 0 to 0FEFFh
+ } ISCP_SMBIOS_STRUCTURE_HEADER;
+
+ /// DMI Type 16 - Physical Memory Array
+ typedef struct {
+ UINT16 Location; ///< The physical location of the Memory Array,
+ ///< whether on the system board or an add-in board.
+ UINT16 Use; ///< Identifies the function for which the array
+ ///< is used.
+ UINT16 MemoryErrorCorrection; ///< The primary hardware error correction or
+ ///< detection method supported by this memory array.
+ ///< ..for memory devices in this array.
+ UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available..
+ ///< ..for memory devices in this array.
+ } ISCP_TYPE16_SMBIOS_INFO;
+
+ /// DMI Type 17 offset 13h - Type Detail
+ typedef struct {
+ UINT16 Reserved1:1; ///< Reserved
+ UINT16 Other:1; ///< Other
+ UINT16 Unknown:1; ///< Unknown
+ UINT16 FastPaged:1; ///< Fast-Paged
+ UINT16 StaticColumn:1; ///< Static column
+ UINT16 PseudoStatic:1; ///< Pseudo-static
+ UINT16 Rambus:1; ///< RAMBUS
+ UINT16 Synchronous:1; ///< Synchronous
+ UINT16 Cmos:1; ///< CMOS
+ UINT16 Edo:1; ///< EDO
+ UINT16 WindowDram:1; ///< Window DRAM
+ UINT16 CacheDram:1; ///< Cache Dram
+ UINT16 NonVolatile:1; ///< Non-volatile
+ UINT16 Registered:1; ///< Registered (Buffered)
+ UINT16 Unbuffered:1; ///< Unbuffered (Unregistered)
+ UINT16 Reserved2:1; ///< Reserved
+ } SMBIOS_T17_TYPE_DETAIL;
+
+ /// DMI Type 17 - Memory Device
+ typedef struct {
+ UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
+ UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ UINT16 MemorySize; ///< The size of the memory device.
+ UINT16 FormFactor; ///< The implementation form factor for this memory device.
+ UINT16 DeviceSet; ///< Identifies when the Memory Device is one of a set of..
+ ///< ..memory devices that must be populated with all devices of..
+ ///< ..the same type and size, and the set to which this device belongs.
+ CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ CHAR8 BankLocator[16]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ UINT16 MemoryType; ///< The type of memory used in this device.
+ SMBIOS_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type
+ UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ UINT8 ManufacturerIdCode[8]; ///< Manufacturer ID code.
+ CHAR8 SerialNumber[16]; ///< Serial Number.
+ CHAR8 PartNumber[20]; ///< Part Number.
+ UINT16 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ UINT32 ExtSize; ///< Extended Size.
+ UINT16 ConfigSpeed; ///< Configured memory clock speed
+ } ISCP_TYPE17_SMBIOS_INFO;
+
+ /// DMI Type 19 - Memory Array Mapped Address
+ typedef struct {
+ UINT32 StartingAddr; ///< The physical address, in kilobytes,
+ ///< of a range of memory mapped to the
+ ///< specified physical memory array.
+ UINT32 EndingAddr; ///< The physical ending address of the
+ ///< last kilobyte of a range of addresses
+ ///< mapped to the specified physical memory array.
+ UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
+ ///< with the physical memory array to which this
+ ///< address range is mapped.
+ UINT8 PartitionWidth; ///< Identifies the number of memory devices that
+ ///< form a single row of memory for the address
+ ///< partition defined by this structure.
+ UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+ UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+ } ISCP_TYPE19_SMBIOS_INFO;
+
+ #ifdef __cplusplus
+ }
+#endif
+
+
+#endif /* MEMISCP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemSetup.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemSetup.h new file mode 100644 index 0000000..ec7c3ce --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/MemSetup.h @@ -0,0 +1,84 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * MemSetup.h
+ *
+ * Contains common MemSetup-related structures and defines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+// NOTE: This file shared between SCP and UEFI, make sure all //
+// changes are reflected in both copies. //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef MEMSETUP_H_
+#define MEMSETUP_H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+ /// Memory Set up Structure for customer visibility
+ typedef struct {
+ UINT8 MemoryClockSpeed; ///< Memory clock speed
+ UINT8 DDR3RttWr; ///< DDR3 Rtt_Wr
+ UINT8 DDR3RttNom; ///< DDR3 Rtt_Nom
+ UINT8 DDR4RttWr; ///< DDR4 Rtt_Wr
+ UINT8 DDR4RttNom; ///< DDR4 Rtt_Nom
+ UINT8 AddCtrlDriveStrength; ///< Address/Control Drive Strength
+ UINT8 ClockDriveStrengt; ///< Clock Drive Strength
+ UINT8 DataDMDriveStrength; ///< Data/DM Drive Strength
+ UINT8 DQSDriveStrength; ///< DQS Drive Strength
+ UINT8 PowerdownEnable; ///< Power down Enable
+ UINT16 PowerdownIdleClocks; ///< Power down Idle Clocks
+ UINT8 LongCountMask; ///< Long Count Mask
+ UINT8 ECCEnable; ///< ECC Enable/Disable
+ UINT16 tref; ///< tref
+ UINT16 tselseldq; ///< tsel_sel_dq
+ UINT16 tselseldqs; ///< tsel_sel_dqs
+ UINT16 trainingProgress; ///< training progress
+ UINT16 trainingRestore; ///< restore training results
+ } MEM_SETUP_VAR;
+
+ #ifdef __cplusplus
+ }
+#endif
+
+
+#endif /* MEMSETUP_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/NetworkAddress.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/NetworkAddress.h new file mode 100644 index 0000000..9d1f77f --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/NetworkAddress.h @@ -0,0 +1,55 @@ +/**
+ * @file
+ *
+ * Network Definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: STYX
+ * @e sub-project: (TBD)
+ * @e \$Revision$ @e \$Date$
+ *
+ **/
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+
+#ifndef __NETWORK_ADDRESS_H__
+#define __NETWORK_ADDRESS_H__
+
+/// Indicates the status of an IP address field within a structure
+ typedef enum {
+ DISABLED, ///< Disabled
+ ENABLED ///< Enabled
+ } IP_ADDRESS_STATUS;
+
+/// Structure for an IPv4 address
+ typedef struct {
+ UINT32 Status; ///< Indicates if the address is valid
+ UINT8 IpAddress[4]; ///< IPv4 address data, if enabled (xxx.xxx.xxx.xxx)
+ } ISCP_BMC_IPV4_ADDRESS;
+
+/// Structure for an IPv6 address
+ typedef struct {
+ UINT32 Status; ///< Indicates if the address is valid
+ UINT8 IpAddress[16]; ///< IPv6 address data, if enabled (xxxx:xxxx:xxxx:xxx:xxxx:xxxx:xxxx:xxxx)
+ } ISCP_BMC_IPV6_ADDRESS;
+
+/// Structure for any combination of an IPv4 and an IPv6 address
+ typedef struct {
+ ISCP_BMC_IPV4_ADDRESS Ipv4Address; ///< IPv4 Network Address Structure
+ ISCP_BMC_IPV6_ADDRESS Ipv6Address; ///< IPv6 Network Address Structure
+ } IP_ADDRESS_INFO;
+
+#endif /* __NETWORK_ADDRESS_H__ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/PostCode.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/PostCode.h new file mode 100644 index 0000000..dabd58e --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/PostCode.h @@ -0,0 +1,82 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * PostCode.h
+ *
+ * Contains Where's-The-Fimrware (WTF) POST code definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+#ifndef __POSTCODE__H_
+#define __POSTCODE__H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+// AMD UEFI WTF POST Codes
+#define POST_ENTER_SEC_CORE 0x200 ///< Enter SEC Phase Core
+#define POST_INIT_GIG_SEC 0x201 ///< Initialize GIC in Secure Mode
+#define POST_EXIT_SEC_CORE 0x202 ///< Exit SEC Phase Core
+#define POST_INIT_GIC_NON_SEC 0x203 ///< Initalize GIC in Non-Secure Mode
+#define POST_INIT_FV 0x204 ///< Initialize Firmware Volume
+#define POST_RE_INIT_FV 0x205 ///< Re-Initialize Firmware Volume
+#define POST_PROCESS_FV_FILE 0x206 ///< Process Firmware Volume File
+#define POST_PROCESS_FV_FILE_SECT 0x207 ///< Process Firmware Volume Sections
+#define POST_CSP_LIB_INIT_PEI 0x208 ///< Initialize CSP Library PEI Phase
+#define POST_BSP_CORE_MAIN_PRE_PEI 0x209 ///< BSP Core Main Pre-PEI
+#define POST_AP_CORE_MAIN_PRE_PEI 0x20A ///< AP Core Main Pre-PEI
+#define POST_ENTER_PEI_CORE 0x20B ///< Enter PEI Core
+#define POST_INIT_GIC_PEI 0x20C ///< Initialize PEI GIC
+#define POST_UART_INIT 0x20D ///< Initialize UART
+#define POST_UART_INIT_PORT 0x20E ///< Initiaize the UART port attributes
+#define POST_PEI_ISCP_INIT 0x20F ///< Initialize PEI ISCP
+#define POST_EXIT_PEI_CORE 0x210 ///< Exit PEI Core
+#define POST_PRE_PI_MAIN 0x211 ///< Enter Pre-DXE Main
+#define POST_BSP_CORE_MAIN_PRE_PI 0x212 ///< Enter BSP Pre-DXE Core
+#define POST_AP_CORE_MAIN_PRE_PI 0x213 ///< Enter AP Core Main Pre-DXE
+#define POST_DXE_MAIN_UEFI_DECOMP 0x214 ///< Decompress DXE
+#define POST_ENTER_DXE_CORE 0x215 ///< Enter DXE Core
+#define POST_DXE_CORE_MEM_ADD_SPACE 0x216 ///< Add Memory Space in DXE Core
+#define POST_DXE_CORE_MEM_FREE_SPACE 0x217 ///< Free Memory Space in DXE Core
+#define POST_INIT_GIC_DXE 0x218 ///< Initialize GIC in DXE phase
+#define POST_INIT_ISCP_DXE 0x219 ///< Initialize ISCP DXE
+#define POST_EXIT_DXE_CORE 0x21A ///< Exit DXE Core
+#define POST_EXIT_BOOT_SERV 0x21B ///< Exit Boot Services
+#define POST_FINAL 0x3FF ///< Final POST code
+
+
+// AMD UEFI WTF Error Codes
+#define ERROR_ISCP_TIMEOUT 0x250 ///< ISCP Timeout (no response from SCP)
+#define ERROR_PXE_DHCP_FAIL 0x251 ///< PXE DHCP Fail
+#define ERROR_PXE_DHCP_PASS 0x252 ///< PXE DHCP Pass
+#define ERROR_PCIE_TRAIN_ERROR 0x261 ///< GIONB PCIE training error
+#define ERROR_PCIE_SPEED_ERROR 0x262 ///< GIONB PCIE data rate error
+#define ERROR_PCIE_PLL_ERROR 0x263 ///< GIONB PCIE PLL error
+#define ERROR_NO_HDD_DETECTED 0x2CF ///< No HDD Detected from SATA ports
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+ #ifdef __cplusplus
+ }
+#endif
+#endif
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/SocConfiguration.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/SocConfiguration.h new file mode 100644 index 0000000..4ca9785 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/SocConfiguration.h @@ -0,0 +1,100 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * SocConfiguration.h
+ *
+ * Contains SoC Fuse Data structure definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+// NOTE: This file shared between SCP and UEFI, make sure all //
+// changes are reflected in both copies. //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+#ifndef __SOC_CONFIGURATION_H_
+#define __SOC_CONFIGURATION_H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+ #include "ProcessorBind.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define SOC_BRAND_NAME_SIZE (48)
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+ /// SOC Security Modes Enumeration
+ typedef enum {
+ SOC_SECURITY_MODE_BLANK = 0, ///< Security Mode Blank
+ SOC_SECURITY_MODE_NOT_SECURE, ///< Security Mode Non-secure
+ SOC_SECURITY_MODE_SECURE, ///< Security Mode Secure
+ SOC_SECURITY_MODE_UNDEFINED, ///< Security Mode Undefined
+ } SOC_SECURITY_MODES;
+
+ /// SOC Configuration, i.e. fusing structure
+ typedef struct {
+ UINT64 SerialNumber; ///< SOC Serial Number
+ SOC_SECURITY_MODES SecurityState; ///< Indicates what security mode the SOC is in.
+ INT32 CpuMap; ///< Map of CPU cores in SOC.
+ INT32 CpuDefaultAClock; ///< Default fused core frequency
+ INT32 CpuClusterCount; ///< Number of CPU clusters in SOC.
+ INT32 CpuCoreCount; ///< Number of CPU cores in SOC.
+ INT32 CpuClusterBoot; ///< Primary cluster used for boot.
+ INT32 CpuCoreBoot; ///< Primary core used for boot.
+ INT32 CcpEnabled; ///< Indicates CCP enabled state. Zero if disabled; otherwise, enabled.
+ INT32 PcieEnabled; ///< Indicates PCIe enabled state. Zero if disabled; otherwise, enabled.
+ INT32 SataEnabled; ///< Indicates SATA enabled state. Zero if disabled; otherwise, enabled.
+ INT32 XgeEnabled; ///< Indicates 10 gigabit Ethernet port enabled state. Zero if disabled; otherwise, enabled.
+ UINT32 BrandId; ///< Brand ID
+ UINT32 ConfigurationId; ///< Configuration ID
+ UINT32 CpuIdModel; ///< CPU ID - Model
+ UINT32 CpuIdExtModel; ///< CPU ID - Extended Model
+ UINT32 CpuIdStepping; ///< CPU ID - Stepping
+ UINT32 FixedErrata; ///< Fixed Errata
+ UINT32 InternalRevision; ///< Internal Revision
+ UINT32 ManufacturingSpecifiedId; ///< Manufacturing Specified Field
+ CHAR8 BrandName[SOC_BRAND_NAME_SIZE]; ///< Null appended at end
+ } SocConfiguration;
+
+ #ifdef __cplusplus
+ }
+#endif
+
+#endif // __SOC_CONFIGURATION_H__
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/UartLineSettings.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/UartLineSettings.h new file mode 100644 index 0000000..36df534 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/UartLineSettings.h @@ -0,0 +1,97 @@ +/**
+ * @file
+ *
+ * Generic UART line setting values. These are shared between UEFI and the SCP.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: STYX
+ * @e sub-project: (TBD)
+ * @e \$Revision$ @e \$Date$
+ *
+ **/
+/*****************************************************************************
+ *
+ * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * This program and the accompanying materials are licensed and made available
+ * under the terms and conditions of the BSD License which accompanies this
+ * distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ *
+ * ***************************************************************************
+ **/
+
+#ifndef _UART_LINE_SETTINGS_H_
+#define _UART_LINE_SETTINGS_H_
+
+//#########################################################################
+//#########################################################################
+//#########################################################################
+// NOTE: This file shared between SCP and UEFI, make sure all //
+// changes are reflected in both copies. //
+//#########################################################################
+//#########################################################################
+//#########################################################################
+
+
+/// UART Baudrate enum
+typedef enum {
+ /// This subset is defined/used in UEFI
+ UART_BAUDRATE_9600 = 9600, ///< 9600 Baudrate
+ UART_BAUDRATE_19200 = 19200, ///< 19200 Baudrate
+ UART_BAUDRATE_38400 = 38400, ///< 38400 Baudrate
+ UART_BAUDRATE_57600 = 57600, ///< 57600 Baudrate
+ UART_BAUDRATE_115200 = 115200, ///< 115200 Baudrate
+
+ /// These could be used within the SCP.
+ UART_BAUDRATE_110 = 110, ///< 110 Baudrate
+ UART_BAUDRATE_300 = 300, ///< 300 Baudrate
+ UART_BAUDRATE_600 = 600, ///< 600 Baudrate
+ UART_BAUDRATE_1200 = 1200, ///< 1200 Baudrate
+ UART_BAUDRATE_2400 = 2400, ///< 2400 Baudrate
+ UART_BAUDRATE_4800 = 4800, ///< 4800 Baudrate
+ UART_BAUDRATE_14400 = 14400, ///< 14400 Baudrate
+ UART_BAUDRATE_230400 = 230400, ///< 230400 Baudrate
+ UART_BAUDRATE_460800 = 460800, ///< 460800 Baudrate
+ UART_BAUDRATE_921600 = 921600, ///< 921600 Baudrate
+} UART_BAUDRATE;
+
+/// UART Parity enum
+typedef enum {
+ DEFAULT_PARITY = 0, ///< Default Parity
+ NO_PARITY, ///< No Parity
+ EVEN_PARITY, ///< Even Parity
+ ODD_PARITY, ///< Odd Parity
+ MARK_PARITY, ///< Mark Parity
+ SPACE_PARITY ///< Space Parity
+} UART_PARITY;
+
+/// UART Stop Bit enum
+typedef enum {
+ UART_STOP_BIT_0 = 0, ///< No Stop Bits
+ UART_STOP_BIT_1, ///< One Stop Bit
+ UART_STOP_BIT_1_5, ///< One and One Half Stop bits
+ UART_STOP_BIT_2 ///< Two Stop Bits
+} UART_STOP_BITS;
+
+/// UART Data Length enum
+typedef enum {
+ UART_DATA_BITS_5 = 5, ///< Five Data Bits
+ UART_DATA_BITS_6, ///< Six Data Bits
+ UART_DATA_BITS_7, ///< Seven Data Bits
+ UART_DATA_BITS_8, ///< Eight Data Bits
+} UART_DATA_BITS;
+
+/// UART Line Settings structure
+typedef struct _UART_LINE_SETTINGS {
+ UART_BAUDRATE BaudRate; ///< UART Baudrate
+ UART_DATA_BITS DataBits; ///< UART Data Bits
+ UART_PARITY Parity; ///< UART Parity
+ UART_STOP_BITS StopBits; ///< UART Stop Bits
+} UART_LINE_SETTINGS;
+
+#endif /* _UART_LINE_SETTINGS_H_ */
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Wtf_Reg.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Wtf_Reg.h new file mode 100644 index 0000000..736edab --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/Wtf_Reg.h @@ -0,0 +1,133 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * Wtf_Reg.h
+ *
+ * Contains Where's-The-Firmware (WTF) definitions and Macros.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+#ifndef __WTF_REG__H_
+#define __WTF_REG__H_
+
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define WTF_STATUS_REG 0xE0000000 // "Where's The Firmware" Register
+
+#define WTF_STATUS_REG_SIZE 32
+#define WTF_STATUS_ERROR_SIZE 12
+#define WTF_STATUS_POST_SIZE 10
+#define WTF_STATUS_FW_INDICATOR_SIZE 2
+#define WTF_STATUS_BT_CHKSUMFAIL_SIZE 1
+
+#define WTF_STATUS_ERROR_SHIFT 0
+#define WTF_STATUS_POST_SHIFT 12
+#define WTF_STATUS_FW_INDICATOR_SHIFT 22
+#define WTF_STATUS_BT_CHKSUMFAIL_SHIFT 31
+
+#define WTF_STATUS_ERROR_MASK 0x00000FFF
+#define WTF_STATUS_POST_MASK 0x003FF000
+#define WTF_STATUS_FW_INDICATOR_MASK 0x00C00000
+#define WTF_STATUS_BT_CHKSUMFAIL_MASK 0x80000000
+
+#define WTF_STATUS_MASK \
+ (WTF_STATUS_ERROR_MASK | \
+ WTF_STATUS_POST_MASK | \
+ WTF_STATUS_FW_INDICATOR_MASK | \
+ WTF_STATUS_BT_CHKSUMFAIL_MASK)
+
+#define WTF_STATUS_DEFAULT 0x00000000
+#define WTF_STATUS_FW_INDICATOR_UEFI 0x2
+
+#define WTF_STATUS_GET_ERROR(wtf_status) \
+ ((wtf_status & WTF_STATUS_ERROR_MASK) >> WTF_STATUS_ERROR_SHIFT)
+#define WTF_STATUS_GET_POST(wtf_status) \
+ ((wtf_status & WTF_STATUS_POST_MASK) >> WTF_STATUS_POST_SHIFT)
+#define WTF_STATUS_GET_FW_INDICATOR(wtf_status) \
+ ((wtf_status & WTF_STATUS_FW_INDICATOR_MASK) >> WTF_STATUS_FW_INDICATOR_SHIFT)
+#define WTF_STATUS_GET_BT_CHKSUMFAIL(wtf_status) \
+ ((wtf_status & WTF_STATUS_BT_CHECKSUMFAIL_MASK) >> WTF_STATUS_BT_CHECKSUMFAIL_SHIFT)
+
+#define WTF_STATUS_SET_ERROR(error) { \
+ UINT32 wtf_status_reg; \
+ wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+ wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_ERROR_MASK) | (error << WTF_STATUS_ERROR_SHIFT); \
+ wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \
+ MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+#define WTF_STATUS_SET_POST(post) { \
+ UINT32 wtf_status_reg; \
+ wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+ wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_POST_MASK) | (post << WTF_STATUS_POST_SHIFT); \
+ wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \
+ MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+#define WTF_STATUS_SET_FW_INDICATOR(fwindicator) { \
+ UINT32 wtf_status_reg; \
+ wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+ wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (fwindicator << WTF_STATUS_FW_INDICATOR_SHIFT); \
+ MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+#define WTF_STATUS_SET_BT_CHKSUMFAIL(btchksmfail) { \
+ UINT32 wtf_status_reg; \
+ wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
+ wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_BT_CHKSUMFAIL_MASK) | (btchksmfail << WTF_STATUS_BT_CHKSUMFAIL_SHIFT); \
+ MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
+}
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// WTF Status Structure
+typedef
+struct _WTF_STATUS_T {
+ UINT64 error : WTF_STATUS_ERROR_SIZE; ///< WTF Status Error Size
+ UINT64 post : WTF_STATUS_POST_SIZE; ///< WTF Status Post Size
+ UINT64 fwindicator : WTF_STATUS_FW_INDICATOR_SIZE; ///< WTF Status Firmware Indicator Size
+ UINT64 reserved : 7; ///< Reserved
+ UINT64 btchksmfail : WTF_STATUS_BT_CHKSUMFAIL_SIZE; ///< WTF Status Bit Checksum Fail Size
+} WTF_STATUS_T;
+
+/// WTF Status Union
+typedef
+union {
+ UINT32 val : 32; ///< Value
+ WTF_STATUS_T f; ///< WTF Status Structure
+} WTF_STATUS_U;
+
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.depex new file mode 100644 index 0000000..81f1fd5 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.depex @@ -0,0 +1 @@ +Í ,ÊDZI®$›o¨q;#
\ No newline at end of file diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.efi Binary files differnew file mode 100644 index 0000000..bbd2e1c --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.efi diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.inf new file mode 100644 index 0000000..9b06cf6 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Gionb/Gionb.inf @@ -0,0 +1,51 @@ +#**
+# @file
+#
+# Gionb.inf
+#
+# AMD-specific Gionb module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 325775 $ @e date: $Date: 2015-08-31 17:45:22 -0500 (Mon, 31 Aug 2015) $
+#
+#
+#*****************************************************************************
+#
+# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+INF_VERSION = 0x00010015
+VERSION_STRING = 1.0
+BASE_NAME = Gionb
+MODULE_TYPE = PEIM
+FILE_GUID = 3D65D81A-6E60-436F-951A-C9878BF77390
+ENTRY_POINT = PeiInitGionb
+
+[Binaries.AARCH64]
+ PE32|Gionb.efi|*
+ PEI_DEPEX|Gionb.depex|*
+
+[Packages]
+ AmdModulePkg/AmdModulePkg.dec
+
+[PatchPcd]
+ gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2|0xa4d9
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|0xa4c2
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|0xa4ab
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|0xa4d8
+ gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE|0xa4ac
+ gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|0xa4ad
+ gAmdModulePkgTokenSpaceGuid.PcdPcieGen3|0|0xa4c1
+ gAmdModulePkgTokenSpaceGuid.PcdPcieGen2|0|0xa4c0
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdNvLib.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdNvLib.h new file mode 100644 index 0000000..20a234a --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdNvLib.h @@ -0,0 +1,78 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * AmdNvLib.c
+ *
+ * Provides library calls for NV (SPI and EEPROM) access.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 306428 $ @e date: $Date: 2014-10-23 14:42:26 -0500 (Thu, 23 Oct 2014) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+#ifndef _AMD_NV_H_
+#define _AMD_NV_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #pragma pack(1)
+
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define EEPROM_PAGE_SIZE 0x2000 // 8K block size
+#define EEPROM_ERASE_POLARITY 0x1 // Erase Polarity Positive (all bits ON)
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S
+ *----------------------------------------------------------------------------------------
+ */
+
+ VOID
+ AmdNvEepromRead (
+ volatile UINT8 *Address,
+ UINT8 *Data,
+ UINT32 *Size
+ );
+
+ VOID
+ AmdNvEepromWrite (
+ volatile UINT8 *Address,
+ UINT8 *Data,
+ UINT32 *Size
+ );
+
+ VOID
+ AmdNvEepromErase (
+ volatile UINT8 *Address,
+ UINT32 *Size
+ );
+
+ #pragma pack()
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+ #ifdef __cplusplus
+ }
+#endif
+#endif
+
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdSataInitLib.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdSataInitLib.h new file mode 100644 index 0000000..a5a6039 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Library/AmdSataInitLib.h @@ -0,0 +1,150 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * AmdSataInitLib.h
+ *
+ * Public SATA PHY layer initilization and training routines for Serdes registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+#ifndef _AMD_SATA_INIT_LIB_H_
+#define _AMD_SATA_INIT_LIB_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ /**
+ *---------------------------------------------------------------------------------------
+ *
+ * SataPhyInit
+ *
+ * Description:
+ * Library call that trains the SATA PHY.
+ *
+ * Control flow:
+ * 1. Initialize variables
+ * 2. Continue to set Serdes bits while not locked
+ *
+ * Parameters:
+ * @param[in] cmu_number Cmu block number. Port 0,1 belongs to CMU 0
+ * @param[in] EvenPortGen Port Gen value for even port in given CMU
+ * @param[in] OddPortGen Port Gen Value for Odd Port in given CMU
+ *
+ * @return VOID
+ *
+ *------------------------------------------------------------------------------------
+ **/
+ VOID
+ EFIAPI
+ SataPhyInit (
+ IN UINT32 cmu_number,
+ IN UINT32 EvenPortGen,
+ IN UINT32 OddPortGen
+ );
+
+ /**
+ *---------------------------------------------------------------------------------------
+ *
+ * SetCwMinSata0
+ *
+ * Description:
+ *
+ * Parameters:
+ * @param[in] Portnum Port number
+ *
+ * @return VOID
+ *
+ *------------------------------------------------------------------------------------
+ **/
+ VOID
+ EFIAPI
+ SetCwMinSata0 (
+ IN UINT32 Portnum
+ );
+
+ /**
+ *---------------------------------------------------------------------------------------
+ *
+ * SetCwMinSata1
+ *
+ * Description:
+ *
+ * Parameters:
+ * @param[in] Portnum Port number
+ *
+ * @return VOID
+ *
+ *------------------------------------------------------------------------------------
+ **/
+ VOID
+ EFIAPI
+ SetCwMinSata1 (
+ IN UINT32 Portnum
+ );
+
+ /**
+ *---------------------------------------------------------------------------------------
+ *
+ * SetPrdSingleSata0
+ *
+ * Description:
+ *
+ * Parameters:
+ * @param[in] Portnum Port number
+ *
+ * @return VOID
+ *
+ *------------------------------------------------------------------------------------
+ **/
+ VOID
+ EFIAPI
+ SetPrdSingleSata0 (
+ IN UINT32 Portnum
+ );
+
+ /**
+ *---------------------------------------------------------------------------------------
+ *
+ * SetPrdSingleSata1
+ *
+ * Description:
+ *
+ * Parameters:
+ * @param[in] Portnum Port number
+ *
+ * @return VOID
+ *
+ *------------------------------------------------------------------------------------
+ **/
+ VOID
+ EFIAPI
+ SetPrdSingleSata1 (
+ IN UINT32 Portnum
+ );
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+ #ifdef __cplusplus
+ }
+#endif
+#endif
+
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/GionbPpi.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/GionbPpi.h new file mode 100644 index 0000000..85b088c --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/GionbPpi.h @@ -0,0 +1,78 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * GionbPpi.h
+ *
+ * GioNb Protocol-Protocol Interface header file.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+
+#ifndef _PEI_GIONB_PPI_H_
+#define _PEI_GIONB_PPI_H_
+
+///
+/// Global ID for the PEI_GIONB_PPI.
+///
+#define PEI_GIONB_PPI_GUID \
+{ \
+ 0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0xf, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } \
+}
+
+///
+/// Forward declaration for the PEI_CAPSULE_PPI.
+///
+typedef struct _EFI_PEI_GIONB_PPI EFI_PEI_GIONB_PPI;
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ * PEI_INIT_GIONB_REGISTERS
+ *
+ * Description:
+ * Initialize GIONB registers.
+ *
+ * Parameters:
+ * @param[in] **PeiServices Pointer to the PEI
+ * Services Table.
+ *
+ * @return EFI_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_INIT_GIONB_REGISTERS)(
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+///
+/// This PPI provides several services in PEI to initialize and configure GIO NB registers.
+///
+struct _EFI_PEI_GIONB_PPI {
+ PEI_INIT_GIONB_REGISTERS GioNbEarlyInit;
+};
+
+extern EFI_GUID gPeiGionbPpiGuid;
+
+#endif // #ifndef _PEI_GIONB_PPI_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/IscpPpi.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/IscpPpi.h new file mode 100644 index 0000000..ca59b11 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Ppi/IscpPpi.h @@ -0,0 +1,219 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * IscpPpi.h
+ *
+ * Contains Intra-SoC Communication Protocol-Protocol Interface definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+
+#ifndef _PEI_ISCP_PPI_H_
+#define _PEI_ISCP_PPI_H_
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include <Iscp.h>
+
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define PEI_ISCP_PPI_GUID {\
+ 0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } \
+}
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct _EFI_PEI_ISCP_PPI EFI_PEI_ISCP_PPI;
+
+
+/// ISCP Memory Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_MEMORY_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT AMD_MEMORY_RANGE_DESCRIPTOR *MemRangeDescriptor ///< Pointer to Memory Range Descriptor
+ );
+
+
+/// ISCP Fuse Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_FUSE_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_FUSE_INFO *FuseInfo ///< Pointer to the Fuse Info structure
+ );
+
+
+/// ISCP CPU Retrieve ID Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
+ );
+
+
+/// ISCP CPU Reset transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_CPU_RESET_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
+ );
+
+
+/// ISCP Get Real-Time-Clock Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_GET_RTC_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock
+ );
+
+
+/// ISCP Set Real-Time-Clock Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SET_RTC_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock
+ );
+
+
+/// ISCP Get MAC Address Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the MAC Address info
+ );
+
+
+/// ISCP Set MAC Address Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the MAC Address info
+ );
+
+
+/// ISCP Update Firmware Volume Block Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN CONST UINT32 Offset, ///< Offset from base of FV Block
+ IN OUT UINT8 *NvData, ///< Pointer to the NV data being stored
+ IN CONST UINT32 NvSize ///< Size of NV Data being stored
+ );
+
+
+/// SCP Load Firmware Volume Block Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN CONST UINT32 Offset, ///< Offset from base of FV Block
+ IN OUT UINT8 *NvData, ///< Pointer to the NV data being stored
+ IN CONST UINT32 NvSize ///< Size of NV Data being stored
+ );
+
+
+/// ISCP Erase Firmware Volume Block Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN CONST UINT32 Offset, ///< Offset from base of FV Block
+ IN CONST UINT32 NvSize ///< Size of NV Data being stored
+ );
+
+
+/// ISCP PCIE Reset Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_PCIE_RESET_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_PCIE_RESET_INFO *PcieResetInfo ///< Pointer to PCIE Reset info structure
+ );
+
+
+/// ISCP Send UART Config Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SEND_UART_CONFIG_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_UART_INFO *UartInfo ///< Pointer to UART Config info structure
+ );
+
+/// ISCP Sata1 get Transaction
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_SATA1_GET_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ IN OUT ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to SATA1 reset structure
+ );
+
+/// ISCP BMC Present
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ISCP_BMC_PRESENT_TRANSACTION)(
+ IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
+ OUT ISCP_BMC_PRESENCE_INFO *BmcPresenceInfo ///< Pointer to BMC presence structure
+ );
+
+/// This PPI provides several services in PEI to work with the underlying
+/// Intra-SOC Communication Protocol capabilities of the platform. These
+/// services include the ability for PEI to send/receive Firmware Setup data,
+/// retrieve memory data, retrieve fuse data, perform CPU core reset, e.g launch,
+/// retrieve OEM NVRAM transactions.
+struct _EFI_PEI_ISCP_PPI {
+ PEI_ISCP_MEMORY_TRANSACTION ExecuteMemoryTransaction;
+ PEI_ISCP_FUSE_TRANSACTION ExecuteFuseTransaction;
+ PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION ExecuteCpuRetrieveIdTransaction;
+ PEI_ISCP_CPU_RESET_TRANSACTION ExecuteCpuResetTransaction;
+ PEI_ISCP_GET_RTC_TRANSACTION ExecuteGetRtcTransaction;
+ PEI_ISCP_SET_RTC_TRANSACTION ExecuteSetRtcTransaction;
+ PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION ExecuteGetMacAddressTransaction;
+ PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION ExecuteSetMacAddressTransaction;
+ PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION ExecuteUpdateFvBlock;
+ PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION ExecuteLoadNvBlock;
+ PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION ExecuteEraseNvBlock;
+ PEI_ISCP_PCIE_RESET_TRANSACTION ExecutePcieResetTransaction;
+ PEI_ISCP_SEND_UART_CONFIG_TRANSACTION ExecuteSendUartConfigTransaction;
+ PEI_ISCP_SATA1_GET_TRANSACTION ExecuteSata1GetTransaction;
+ PEI_ISCP_BMC_PRESENT_TRANSACTION ExecuteBmcPresentTransaction;
+};
+
+extern EFI_GUID gPeiIscpPpiGuid;
+
+#endif // #ifndef _PEI_ISCP_PPI_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h new file mode 100644 index 0000000..5daeb0c --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h @@ -0,0 +1,309 @@ +/* $NoKeywords */
+/**
+ * @file
+ *
+ * AmdIscpDxeProtocol.h
+ *
+ * Contains Intra-SoC Communication DXE Protocol definitions.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e version: $Revision: 337020 $ @e date: $Date: 2016-03-02 11:49:34 -0600 (Wed, 02 Mar 2016) $
+ *
+ */
+/*****************************************************************************
+*
+* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+* IMPLIED.
+*
+***************************************************************************/
+
+#ifndef __AMD_ISCP_DXE_PROTOCOL__H_
+#define __AMD_ISCP_DXE_PROTOCOL__H_
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include <Iscp.h>
+
+
+/*----------------------------------------------------------------------------------------
+ * G U I D D E F I N I T I O N
+ *----------------------------------------------------------------------------------------
+ */
+#define AMD_ISCP_DXE_PROTOCOL_GUID {\
+ 0x5c794c8, 0x6aef, 0x4450, 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 \
+}
+
+/*----------------------------------------------------------------------------------------
+ * E X T E R N S
+ *----------------------------------------------------------------------------------------
+ */
+extern EFI_GUID gAmdIscpDxeProtocolGuid;
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct _AMD_ISCP_DXE_PROTOCOL AMD_ISCP_DXE_PROTOCOL;
+
+ /// HEST Notification type
+ typedef enum {
+ HEST_NOTIFY_POLLED = 0, ///< Polled
+ HEST_NOTIFY_GPIO = 7, ///< GPIO-Signal
+ } HEST_NOTIFY_TYPE;
+
+ /// Trusted Firmware Generic Error Source structure
+ typedef struct {
+ UINT32 IscpVersion; ///< Version of BERT Region structure
+ UINT8 SourceGUID[16]; ///< ACPI v6.0: Table 18-331 [Section Type]
+ UINT64 ErrorStatusPhysAddr; ///< ACPI v6.0: Table 18-329 [Error Status Address]
+ UINT32 ErrorStatusLength; ///< ACPI v6.0: Table 18-329 [Error Status Block Length]
+ HEST_NOTIFY_TYPE NotificationType; ///< ACPI v6.0: Table 18-332 [Type]
+ } ISCP_TFW_GENERIC_ERROR_SOURCE;
+
+/// CPU Core Reset Prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_CPU_CORE_RESET) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_CPU_RETRIEVE_ID) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
+ );
+
+/// ISCP call to get MAC Address
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_GET_MAC_ADDRESS) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure
+ );
+
+
+/// ISCP call to set MAC Address
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SET_MAC_ADDRESS) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure
+ );
+
+
+/// ISCP call to get Real-Time-Clock
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_GET_RTC) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure
+ );
+
+
+/// ISCP call to set Real-Time-Clock
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SET_RTC) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure
+ );
+
+
+/// Update Firmware Volume Block into SPI from local memory
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_UPDATE_FV_BLOCK_DXE) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
+ IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block
+ IN CONST UINT32 NvSize ///< Size of data being stored FV Block
+ );
+
+
+/// Load Firmware Volume Block from SPI into local memory
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_LOAD_FV_BLOCK_DXE) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
+ IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block
+ IN CONST UINT32 NvSize ///< Size of data being retrieved from FV Block
+ );
+
+
+/// Erase Firmware Volume Block Prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_ERASE_FV_BLOCK_DXE) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
+ IN CONST UINT32 NvSize ///< Size of data being erased
+ );
+
+
+/// Update EEPROM Block from local memory prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
+ IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block
+ IN CONST UINT32 Size ///< Size of data being stored EEPROM Block
+ );
+
+
+/// Load EEPROM Block into local memory prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
+ IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block
+ IN CONST UINT32 Size ///< Size of data being retrieved from EEPROM Block
+ );
+
+
+/// Erase EEPROM Block prototype
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
+ IN CONST UINT32 Size ///< Size of data being erased
+ );
+
+
+/// Issue ISCP Doorbell command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_GET_BMC_IP_ADDRESS) (
+ IN AMD_ISCP_DXE_PROTOCOL *This,
+ IN OUT ISCP_BMC_IP_ADDRESS_INFO *BmcIpAddressInfo
+ );
+
+/// Issue ISCP command to retrieve SMBIOS info
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SMBIOS_INFO) (
+ IN AMD_ISCP_DXE_PROTOCOL *This,
+ IN OUT ISCP_SMBIOS_INFO *SmbiosInfo
+ );
+
+/// Issue ISCP command to issue SoC shutdown command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SOC_SHUTDOWN) (
+ IN AMD_ISCP_DXE_PROTOCOL *This
+ );
+
+/// Issue ISCP command to issue SoC reset command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SOC_RESET) (
+ IN AMD_ISCP_DXE_PROTOCOL *This
+ );
+
+/// ISCP call to set Memory Set up Nodes
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_MEM_SETUP) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT MEM_SETUP_VAR *SetupInfo ///< Pointer to the Firmware MAC Address structure
+ );
+
+/// Issue Override Command
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_OVERRIDE_CMD) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN ISCP_OVERRIDE_CMD_INFO *OverrideCmdInfo ///< Pointer to the Overrride Command structure
+ );
+
+/// Issue Sata1 get state
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SATA1_GET) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN OUT ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure
+ );
+
+/// Issue Sata1 set state
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_SATA1_SET) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ IN ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure
+ );
+
+/// Issue BMC presence check
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_BMC_PRESENT) (
+ IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
+ OUT ISCP_BMC_PRESENCE_INFO *BmcPresenceInfo ///< Pointer to BMC presence structure
+ );
+
+/// Register Boot Error Region
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_RETRIEVE_BERT_RECORD) (
+ IN AMD_ISCP_DXE_PROTOCOL *This,
+ IN OUT ISCP_BERT_REGION_INFO *BertRegionInfo
+ );
+
+/// Register generic hardware error soure
+typedef
+EFI_STATUS
+(EFIAPI *AMD_EXECUTE_REGISTER_ERROR_SOURCE) (
+ IN AMD_ISCP_DXE_PROTOCOL *This,
+ IN ISCP_TFW_GENERIC_ERROR_SOURCE *GenericErrorSource
+ );
+
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O C O L S T R U C T U R E
+ *----------------------------------------------------------------------------------------
+ */
+/// ISCP DXE Protocol Structure
+typedef
+struct _AMD_ISCP_DXE_PROTOCOL {
+ AMD_EXECUTE_CPU_CORE_RESET AmdExecuteCpuCoreReset; ///< Execute CPU Core Reset
+ AMD_EXECUTE_CPU_RETRIEVE_ID AmdExecuteCpuRetrieveId; ///< Execute CPU Retrieve ID
+ AMD_EXECUTE_GET_MAC_ADDRESS AmdExecuteGetMacAddress; ///< Execute Get MAC Address
+ AMD_EXECUTE_SET_MAC_ADDRESS AmdExecuteSetMacAddress; ///< Execute Set MAC Address
+ AMD_EXECUTE_GET_RTC AmdExecuteGetRtc; ///< Execute Get Real-Time-Clock Time
+ AMD_EXECUTE_SET_RTC AmdExecuteSetRtc; ///< Execute Set Real-Time-Clock Time
+ AMD_EXECUTE_UPDATE_FV_BLOCK_DXE AmdExecuteUpdateFvBlockDxe; ///< Execute Update FV Block Data on the SPI device
+ AMD_EXECUTE_LOAD_FV_BLOCK_DXE AmdExecuteLoadFvBlockDxe; ///< Execute Load FV Block Data from the SPI device
+ AMD_EXECUTE_ERASE_FV_BLOCK_DXE AmdExecuteEraseFvBlockDxe; ///< Execute Erase FV Block Data on the SPI device
+ AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE AmdExecuteUpdateEepromBlockDxe; ///< Execute Update EEPROM Data on the EEPROM device
+ AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE AmdExecuteLoadEepromBlockDxe; ///< Execute Load EEPROM Data on the EEPROM device
+ AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE AmdExecuteEraseEepromBlockDxe; ///< Execute Erase EEPROM Data on the EEPROM device
+ AMD_EXECUTE_GET_BMC_IP_ADDRESS AmdExecuteGetBmcIpAddress; ///< Execute Get BMC IP Address
+ AMD_EXECUTE_SMBIOS_INFO AmdExecuteSmbiosInfoDxe; ///< Execute SMBIOS info
+ AMD_EXECUTE_SOC_SHUTDOWN AmdExecuteSocShutdownDxe; ///< Execute SoC Shutdown
+ AMD_EXECUTE_SOC_RESET AmdExecuteSocResetDxe; ///< Execute SoC Reset
+ AMD_EXECUTE_MEM_SETUP AmdExecuteMemSetup; ///< Execute Set MAC Address
+ AMD_EXECUTE_OVERRIDE_CMD AmdExecuteOverrideCmd; ///< Execute Override Command
+ AMD_EXECUTE_SATA1_GET AmdExecuteSata1Get; ///< Execute Sata1 get state
+ AMD_EXECUTE_SATA1_SET AmdExecuteSata1Set; ///< Execute Sata1 set state
+ AMD_EXECUTE_BMC_PRESENT AmdExecuteBmcPresent; ///< Execute BMC presence check
+ AMD_EXECUTE_RETRIEVE_BERT_RECORD AmdExecuteRetrieveBertRecord; ///< Execute Retrieve Boot Error Record
+ AMD_EXECUTE_REGISTER_ERROR_SOURCE AmdExecuteRegisterErrorSource; ///< Execute Register Generic Hardware Error Source
+} AMD_ISCP_DXE_PROTOCOL;
+
+#endif //_AMD_ISCP_DXE_PROTOCOL_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h new file mode 100644 index 0000000..94f4f26 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h @@ -0,0 +1,86 @@ +/* $NoKeywords: $ */
+/**
+ * @file
+ *
+ * AMD RAS APEI Protocol
+ *
+ * AMD Ras Interface Protocol GUID initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: FDK
+ * @e sub-project: UEFI
+ * @e \$Revision: 281924 $ @e \$Date: 2014-01-02 13:57:19 -0600 (Thu, 02 Jan 2014) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * This program and the accompanying materials are licensed and made available
+ * under the terms and conditions of the BSD License which accompanies this
+ * distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ *
+ ***************************************************************************/
+
+#ifndef _AMD_RAS_APEI_PROTOCOL_H_
+#define _AMD_RAS_APEI_PROTOCOL_H_
+
+#include "AmdApei.h"
+
+//
+// GUID definition
+//
+#define AMD_RAS_APEI_PROTOCOL_GUID \
+ { 0xe9dbcc60, 0x8f93, 0x47ed, 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a }
+// {E9DBCC60-8F93-47ed-8478-4678F19F734A}
+
+extern EFI_GUID gAmdRasApeiProtocolGuid;
+
+// current PPI revision
+#define AMD_RAS_APEI_REV 0x01
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct _AMD_RAS_APEI_PROTOCOL AMD_RAS_APEI_PROTOCOL;
+
+/// APEI Interface data pointer
+typedef
+struct _AMD_APEI_INTERFACE {
+ APEI_DRIVER_PRIVATE_DATA *ApeiPrivData;
+} AMD_APEI_INTERFACE;
+
+
+/// APEI add Boot error record
+typedef
+EFI_STATUS
+(EFIAPI *AMD_ADD_BOOT_ERROR_RECORD_ENTRY) (
+ IN UINT8 *ErrorRecord,
+ IN UINT32 RecordLen,
+ IN UINT8 ErrorType,
+ IN UINT8 SeverityType
+);
+
+/// APEI add HEST error source
+typedef
+EFI_STATUS
+(EFIAPI *ADD_HEST_ERROR_SOURCE_ENTRY) (
+ IN UINT8 *pErrorRecord,
+ IN UINT32 RecordLen
+);
+
+
+/// RAS APEI Protocol Structure
+typedef struct _AMD_RAS_APEI_PROTOCOL {
+ AMD_APEI_INTERFACE *AmdApeiInterface; /// APEI Interface
+ AMD_ADD_BOOT_ERROR_RECORD_ENTRY AddBootErrorRecordEntry; /// Boot error record to be added
+ ADD_HEST_ERROR_SOURCE_ENTRY AddHestErrorSourceEntry; /// HEST error source to be added
+} AMD_RAS_APEI_PROTOCOL;
+
+
+#endif //_AMD_RAS_APEI_PROTOCOL_H_
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.depex new file mode 100644 index 0000000..0dc7ce4 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.depex @@ -0,0 +1 @@ +öð£J&ð>òàÞÅ4/4
\ No newline at end of file diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.efi Binary files differnew file mode 100644 index 0000000..3bfc2a8 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.efi diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.inf new file mode 100644 index 0000000..4cb7bb2 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpDxe.inf @@ -0,0 +1,47 @@ +# $NoKeywords */
+#
+# @file
+#
+# IscpDxe.inf
+#
+# AMD-specific DXE-Phase Intra-SoC Communication Protocol module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 323117 $ @e date: $Date: 2015-07-22 15:39:01 -0500 (Wed, 22 Jul 2015) $
+#
+#
+#*****************************************************************************
+#
+# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IscpDxe
+ FILE_GUID = 2FC9C0DD-1CB9-44E1-874F-C63B751F34B3
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = IscpInitEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Binaries.AARCH64]
+ PE32|IscpDxe.efi|*
+ DXE_DEPEX|IscpDxe.depex|*
+
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.depex new file mode 100644 index 0000000..53e435a --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.depex @@ -0,0 +1 @@ +%MóâM#?ó65?ó#ñ
\ No newline at end of file diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.efi Binary files differnew file mode 100644 index 0000000..7e917fd --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.efi diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.inf new file mode 100644 index 0000000..98fd81c --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Iscp/IscpPei.inf @@ -0,0 +1,45 @@ +#**
+# @file
+#
+# IscpPei.inf
+#
+# AMD-specific PEI-Phase Intra-SoC Communication Protocol module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 321113 $ @e date: $Date: 2015-06-19 10:25:47 -0500 (Fri, 19 Jun 2015) $
+#
+#
+#*****************************************************************************
+#
+# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IscpPei
+ FILE_GUID = 4C4C6624-DDDA-4C49-B542-DAFF4CBF2F20
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PeiInitIscp
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Binaries.AARCH64]
+ PE32|IscpPei.efi|*
+ PEI_DEPEX|IscpPei.depex
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInit.lib b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInit.lib Binary files differnew file mode 100644 index 0000000..2ea410d --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInit.lib diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf new file mode 100644 index 0000000..97b7305 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf @@ -0,0 +1,49 @@ +# $NoKeywords */
+#
+# @file
+#
+# AmdSataInitLib.inf
+#
+# AMD-specific SATA Library Initialization information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 19:25:20 -0500 (Thu, 29 May 2014) $
+#
+#
+#*****************************************************************************
+#
+# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdSataInit
+ FILE_GUID = 15336efd-ab12-512E-cca1-2584695123a0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = AmdSataInit
+
+[Binaries.AARCH64]
+ LIB|AmdSataInit.lib|*
+
+[Packages]
+ AmdModulePkg/AmdModulePkg.dec
+
+[FixedPcd]
+ gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1
+ gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2
+ gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3
+ gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1
+ gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2
+ gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.depex Binary files differnew file mode 100644 index 0000000..cb68e14 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.depex diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.efi Binary files differnew file mode 100644 index 0000000..7575200 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.efi diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.inf new file mode 100644 index 0000000..e45d360 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort0.inf @@ -0,0 +1,48 @@ +# $NoKeywords */
+#
+# @file
+#
+# SnpDxePort0.inf
+#
+# Ethernet port 0 driver module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $
+#
+#
+#*****************************************************************************
+#
+# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ VERSION_STRING = 1.0
+ BASE_NAME = SnpDxePort0
+ MODULE_TYPE = UEFI_DRIVER
+ FILE_GUID = 25ac458a-cf60-476e-861a-211c757657a6
+ ENTRY_POINT = UefiMain
+
+[Binaries.AARCH64]
+ PE32|SnpDxePort0.efi
+ DEPEX|SnpDxePort0.depex
+
+[Packages]
+ AmdModulePkg/AmdModulePkg.dec
+
+[PatchPcd]
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeRev
+ gAmdModulePkgTokenSpaceGuid.PcdEthMacA
+ gAmdModulePkgTokenSpaceGuid.PcdEthMacB
diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.depex b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.depex Binary files differnew file mode 100644 index 0000000..cb68e14 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.depex diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.efi b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.efi Binary files differnew file mode 100644 index 0000000..bf2c84d --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.efi diff --git a/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.inf b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.inf new file mode 100644 index 0000000..12f8be2 --- /dev/null +++ b/Platforms/AMD/Styx/Binary/AmdModulePkg/SnpDxe/SnpDxePort1.inf @@ -0,0 +1,48 @@ +# $NoKeywords */
+#
+# @file
+#
+# SnpDxePort1.inf
+#
+# Ethernet port 1 driver module information file.
+#
+# @xrefitem bom "File Content Label" "Release Content"
+# @e project: FDK
+# @e sub-project: UEFI
+# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $
+#
+#
+#*****************************************************************************
+#
+# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#***************************************************************************/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ VERSION_STRING = 1.0
+ BASE_NAME = SnpDxePort1
+ MODULE_TYPE = UEFI_DRIVER
+ FILE_GUID = 92ea3d06-5990-4436-b4e1-07a02f4a98a9
+ ENTRY_POINT = UefiMain
+
+[Binaries.AARCH64]
+ PE32|SnpDxePort1.efi
+ DEPEX|SnpDxePort1.depex
+
+[Packages]
+ AmdModulePkg/AmdModulePkg.dec
+
+[PatchPcd]
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeRev
+ gAmdModulePkgTokenSpaceGuid.PcdEthMacA
+ gAmdModulePkgTokenSpaceGuid.PcdEthMacB
diff --git a/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin b/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin Binary files differnew file mode 100644 index 0000000..6efb6a8 --- /dev/null +++ b/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc new file mode 100644 index 0000000..4372868 --- /dev/null +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -0,0 +1,656 @@ +#
+# Copyright (c) 2015 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may
+# be found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE NUM_CORES = 8
+DEFINE DO_KCS = 0
+
+ PLATFORM_NAME = Cello
+ PLATFORM_GUID = 77861b3e-74b0-4ff3-8d18-c5ba5803e1bf
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/Cello
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = OpenPlatformPkg/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ #
+ # Allow dynamic PCDs
+ #
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+ # 1/123 faster than Stm or Vstm version
+ #BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
+ ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+ # ARM PL011 UART Driver
+ PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+ #
+ # PCI support
+ #
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciHostBridgeLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+ #
+ # Styx specific libraries
+ #
+ AmdSataInit|AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+ AmdStyxAcpiLib|OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf
+ EfiResetSystemLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf
+ RealTimeClockLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+ ArmPlatformSecLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf
+ ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+ MemoryInitPeiLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ *_*_*_ASL_FLAGS = -tc -li -l -so
+ *_*_*_ASLPP_FLAGS = -x c -E -P $(ARCHCC_FLAGS)
+ *_*_*_ASLCC_FLAGS = -x c $(ARCHCC_FLAGS)
+
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+ GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ # All pages are cached by default
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+ ## created by ConsplitterDxe. It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD Seattle"
+
+ # Number of configured cores
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+ # Declare system memory base
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ #
+ # ARM PrimeCell
+ #
+
+ ## PL011 - Serial Terminal (Atlas UART)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ # serial port is clocked at 100MHz
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+ gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
+
+ #
+ # Bitmask for ports implemented on the SATA controller
+ # (enabling 4 ports by default: 00001111b)
+ #
+ gAmdStyxTokenSpaceGuid.PcdSataPi|0x0F
+
+ # PCIe Support
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0
+ gArmTokenSpaceGuid.PcdPciBusMax|0xFF
+
+ gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+ gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+ ## ACPI (no tables < 4GB)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+
+ # SMBIOS 3.0 only
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x2x2
+ gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicExHii.common.DEFAULT]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # PEI Phase modules
+ #
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ AmdModulePkg/Iscp/IscpPei.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ #
+ # Console IO support
+ #
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # PCI support
+ #
+ AmdModulePkg/Gionb/Gionb.inf
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # AHCI Support
+ #
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataControllerDxe.inf
+
+ #
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf new file mode 100644 index 0000000..148c0a6 --- /dev/null +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf @@ -0,0 +1,383 @@ +#
+# Copyright (c) 2015 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.STYX_ROM]
+BaseAddress = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00500000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = OpenPlatformPkg/Platforms/AMD/Styx/CelloBoard/Binary/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include OpenPlatformPkg/Platforms/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ INF AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # PCI support
+ #
+ INF AmdModulePkg/Gionb/Gionb.inf
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # AHCI Support
+ #
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataControllerDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+
+[FV.STYX_EFI]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF AmdModulePkg/Iscp/IscpPei.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.Binary]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ TE TE Align = Auto |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
+
diff --git a/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h new file mode 100644 index 0000000..698a5d3 --- /dev/null +++ b/Platforms/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -0,0 +1,61 @@ +/** @file
+ This library provides support for various platform-specific DXE drivers.
+
+ Copyright (c) 2014 - 2015, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMDSTYX_ACPI_LIB_H_
+#define _AMDSTYX_ACPI_LIB_H_
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_DESCRIPTION_HEADER *FadtTable (void);
+EFI_ACPI_DESCRIPTION_HEADER *FacsTable (void);
+EFI_ACPI_DESCRIPTION_HEADER *MadtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *GtdtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *DsdtHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *McfgHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void);
+EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void);
+EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void);
+
+#define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'}
+#define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ')
+#define EFI_ACPI_AMD_OEM_REVISION 0
+#define EFI_ACPI_AMD_CREATOR_ID SIGNATURE_32('A','M','D',' ')
+#define EFI_ACPI_AMD_CREATOR_REVISION 0
+
+/**
+ * A macro to initialize the common header part of EFI ACPI tables
+ * as defined by EFI_ACPI_DESCRIPTION_HEADER structure.
+ **/
+#define AMD_ACPI_HEADER(sign, type, rev) { \
+ sign, /* UINT32 Signature */ \
+ sizeof (type), /* UINT32 Length */ \
+ rev, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ EFI_ACPI_AMD_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \
+ EFI_ACPI_AMD_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_AMD_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_AMD_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_AMD_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#define NULL_GAS {EFI_ACPI_5_1_SYSTEM_MEMORY, 0, 0, EFI_ACPI_5_1_UNDEFINED, 0L}
+#define AMD_GAS8(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 8, 0, EFI_ACPI_5_1_BYTE, address}
+#define AMD_GAS16(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 16, 0, EFI_ACPI_5_1_WORD, address}
+#define AMD_GAS32(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_1_DWORD, address}
+#define AMD_GAS64(address) {EFI_ACPI_5_1_SYSTEM_MEMORY, 64, 0, EFI_ACPI_5_1_QWORD, address}
+#define AMD_GASN(address) AMD_GAS32(address)
+
+#endif // _AMDSTYX_ACPI_LIB_H_
+
diff --git a/Platforms/AMD/Styx/Common/Protocol/AmdMpBoot.h b/Platforms/AMD/Styx/Common/Protocol/AmdMpBoot.h new file mode 100644 index 0000000..2aa4c55 --- /dev/null +++ b/Platforms/AMD/Styx/Common/Protocol/AmdMpBoot.h @@ -0,0 +1,39 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMD_MP_BOOT_H_
+#define _AMD_MP_BOOT_H_
+
+extern EFI_GUID gAmdMpBootProtocolGuid;
+
+typedef
+VOID
+(EFIAPI *PARK_SECONDARY_CORE) (
+ IN ARM_CORE_INFO *ArmCoreInfo,
+ IN EFI_PHYSICAL_ADDRESS SecondaryEntry
+ );
+
+typedef struct _AMD_MP_BOOT_INFO {
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+} AMD_MP_BOOT_INFO;
+
+typedef struct _AMD_MP_BOOT_PROTOCOL {
+ PARK_SECONDARY_CORE ParkSecondaryCore;
+ AMD_MP_BOOT_INFO *MpBootInfo;
+} AMD_MP_BOOT_PROTOCOL;
+
+#endif // _AMD_MP_BOOT_H_
diff --git a/Platforms/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h b/Platforms/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h new file mode 100644 index 0000000..95f46e8 --- /dev/null +++ b/Platforms/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h @@ -0,0 +1,45 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _AMD_MP_CORE_INFO_H_
+#define _AMD_MP_CORE_INFO_H_
+
+extern EFI_GUID gAmdMpCoreInfoProtocolGuid;
+
+typedef
+ARM_CORE_INFO *
+(EFIAPI *GET_ARM_CORE_INFO_TABLE) (
+ OUT UINTN *NumEntries
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_PMU_SPI_FROM_MPID) (
+ IN UINT32 MpId,
+ OUT UINT32 *PmuSpi
+ );
+
+typedef
+EFI_PHYSICAL_ADDRESS
+(EFIAPI *GET_MP_PARKING_BASE) (
+ OUT UINTN *MpParkingSize
+ );
+
+typedef struct _AMD_MP_CORE_INFO_PROTOCOL {
+ GET_ARM_CORE_INFO_TABLE GetArmCoreInfoTable;
+ GET_PMU_SPI_FROM_MPID GetPmuSpiFromMpId;
+ GET_MP_PARKING_BASE GetMpParkingBase;
+} AMD_MP_CORE_INFO_PROTOCOL;
+
+#endif // _AMD_MP_CORE_INFO_H_
diff --git a/Platforms/AMD/Styx/Common/Varstore.fdf.inc b/Platforms/AMD/Styx/Common/Varstore.fdf.inc new file mode 100644 index 0000000..83aa433 --- /dev/null +++ b/Platforms/AMD/Styx/Common/Varstore.fdf.inc @@ -0,0 +1,70 @@ +## @file
+# FDF include file with Layout Regions that define an empty variable store.
+#
+# Copyright (C) 2016, Linaro, Ltd.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+0x00460000|0x0000F000
+gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x30000
+ 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0xF Blocks * 0x1000 Bytes / Block
+ 0x0F, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ # Size: 0xF000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xefb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xEF, 0x00, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x0046F000|0x00001000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00470000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c new file mode 100644 index 0000000..1bad597 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,110 @@ +/** @file
+
+ Sample ACPI Platform Driver
+
+ Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ Derived from:
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatform.c
+**/
+
+#include <AmdStyxAcpiLib.h>
+#include <Protocol/AcpiTable.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+#define MAX_ACPI_TABLES 12
+
+EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES];
+
+
+/**
+ Entrypoint of Acpi Platform driver.
+
+ @param ImageHandle
+ @param SystemTable
+
+ @return EFI_SUCCESS
+ @return EFI_LOAD_ERROR
+ @return EFI_OUT_OF_RESOURCES
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ UINTN TableHandle;
+ UINTN TableIndex;
+
+ ZeroMem(AcpiTableList, sizeof(AcpiTableList));
+
+ TableIndex = 0;
+ AcpiTableList[TableIndex++] = FadtTable();
+ AcpiTableList[TableIndex++] = DsdtHeader();
+ AcpiTableList[TableIndex++] = MadtHeader();
+ AcpiTableList[TableIndex++] = GtdtHeader();
+ AcpiTableList[TableIndex++] = Dbg2Header();
+ AcpiTableList[TableIndex++] = SpcrHeader();
+ AcpiTableList[TableIndex++] = McfgHeader();
+ AcpiTableList[TableIndex++] = CsrtHeader();
+ AcpiTableList[TableIndex++] = NULL;
+
+ DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__));
+
+ //
+ // Find the AcpiTable protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR, "Failed to locate AcpiTable protocol. Status = %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ }
+
+ TableIndex = 0;
+ while (AcpiTableList[TableIndex] != NULL) {
+ //
+ // Install ACPI table
+ //
+ DEBUG ((EFI_D_ERROR, "Installing %c%c%c%c Table (Revision %d, Length %d) ...\n",
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature),
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature + 1),
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature + 2),
+ *((UINT8*)&AcpiTableList[TableIndex]->Signature + 3),
+ AcpiTableList[TableIndex]->Revision,
+ AcpiTableList[TableIndex]->Length));
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ AcpiTableList[TableIndex],
+ (AcpiTableList[TableIndex])->Length,
+ &TableHandle
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG((DEBUG_ERROR,"Error adding ACPI Table. Status = %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ }
+ TableIndex++;
+ ASSERT( TableIndex < MAX_ACPI_TABLES );
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 0000000..9f4c3ea --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,49 @@ +#/** @file
+# Sample ACPI Platform Driver
+#
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiPlatform
+ FILE_GUID = f229c831-6a35-440b-9c84-dd3bc71e3865
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiPlatformEntryPoint
+
+[Sources]
+ AcpiPlatform.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ AmdStyxAcpiLib
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED
+
+[Depex]
+ gEfiAcpiTableProtocolGuid
diff --git a/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c new file mode 100644 index 0000000..bd72446 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c @@ -0,0 +1,170 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Guid/ArmMpCoreInfo.h>
+#include <Protocol/AmdMpBoot.h>
+
+
+/* These externs are used to relocate our Pen code into pre-allocated memory */
+extern VOID *SecondariesPenStart;
+extern VOID *SecondariesPenEnd;
+extern UINTN *AsmParkingBase;
+extern UINTN *AsmMailboxBase;
+
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+ConfigurePen (
+ IN EFI_PHYSICAL_ADDRESS MpParkingBase,
+ IN UINTN MpParkingSize,
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN ArmCoreCount
+ )
+{
+ EFI_PHYSICAL_ADDRESS PenBase;
+ UINTN PenSize;
+ UINTN MailboxBase;
+ UINTN CoreNum;
+ UINTN CoreMailbox;
+ UINTN CoreParking;
+
+ //
+ // Set Pen at the 2K-offset of the Parking area, skipping an 8-byte slot for the Core#.
+ // For details, refer to the "Multi-processor Startup for ARM Platforms" document:
+ // https://acpica.org/sites/acpica/files/MP%20Startup%20for%20ARM%20platforms.docx
+ //
+ PenBase = (EFI_PHYSICAL_ADDRESS)((UINTN)MpParkingBase + SIZE_2KB + sizeof(UINT64));
+ PenSize = (UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart;
+
+ // Relocate the Pen code
+ CopyMem ((VOID*)(PenBase), (VOID*)&SecondariesPenStart, PenSize);
+
+ // Put spin-table mailboxes below the pen code so we know where they are relative to code.
+ // Make sure this is 8 byte aligned.
+ MailboxBase = (UINTN)PenBase + ((UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart);
+ if (MailboxBase % sizeof(UINT64) != 0) {
+ MailboxBase += sizeof(UINT64) - MailboxBase % sizeof(UINT64);
+ }
+
+ // Update variables used in the Pen code
+ *(UINTN*)(PenBase + ((UINTN)&AsmMailboxBase - (UINTN)&SecondariesPenStart)) = MailboxBase;
+ *(UINTN*)(PenBase + ((UINTN)&AsmParkingBase - (UINTN)&SecondariesPenStart)) = (UINTN)MpParkingBase;
+
+ for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
+ // Clear the jump address at spin-table slot
+ CoreMailbox = MailboxBase + CoreNum * sizeof (UINT64);
+ *((UINTN*)(CoreMailbox)) = 0x0;
+
+ // Clear the jump address and set Core# at mp-parking slot
+ CoreParking = (UINTN)MpParkingBase + CoreNum * SIZE_4KB;
+ *((UINTN*)(CoreParking + sizeof (UINT64))) = 0x0;
+ *((UINTN*)(CoreParking + SIZE_2KB)) = CoreNum;
+
+ // Update table entry to be consumed by FDT parser
+ ArmCoreInfoTable[CoreNum].MailboxSetAddress = CoreMailbox;
+ }
+
+ // flush the cache before launching secondary cores
+ WriteBackDataCacheRange ((VOID *)MpParkingBase, MpParkingSize);
+
+ return PenBase;
+}
+
+
+EFI_STATUS
+EFIAPI
+MpBootDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ AMD_MP_BOOT_PROTOCOL *MpBootProtocol;
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+ UINTN CoreNum;
+ EFI_PHYSICAL_ADDRESS PenBase;
+
+ DEBUG ((EFI_D_ERROR, "MpBootDxe Loaded\n"));
+
+ MpBootProtocol = NULL;
+ Status = gBS->LocateProtocol (
+ &gAmdMpBootProtocolGuid,
+ NULL,
+ (VOID **)&MpBootProtocol
+ );
+ if (EFI_ERROR (Status) || MpBootProtocol == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: Failed to locate MP-Boot Protocol.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((VOID *)MpBootProtocol->MpBootInfo == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpBootInfo not allocated.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ MpParkingBase = MpBootProtocol->MpBootInfo->MpParkingBase;
+ if ((VOID *)MpParkingBase == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not allocated.\n"));
+ return EFI_UNSUPPORTED;
+ }
+ if (((UINTN)MpParkingBase & (SIZE_4KB -1)) != 0) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not 4K aligned.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmCoreInfoTable = MpBootProtocol->MpBootInfo->ArmCoreInfoTable;
+ if (ArmCoreInfoTable == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: ArmCoreInfoTable not allocated.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmCoreCount = MpBootProtocol->MpBootInfo->ArmCoreCount;
+ if (ArmCoreCount < 2) {
+ DEBUG ((EFI_D_ERROR, "Warning: Found %d cores.\n", ArmCoreCount));
+ return EFI_UNSUPPORTED;
+ }
+
+ MpParkingSize = ArmCoreCount * SIZE_4KB;
+ if (MpParkingSize > MpBootProtocol->MpBootInfo->MpParkingSize) {
+ DEBUG ((EFI_D_ERROR, "Warning: MpParkingSize = 0x%lX, not large enough for %d cores.\n",
+ MpBootProtocol->MpBootInfo->MpParkingSize, ArmCoreCount));
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((VOID *)MpBootProtocol->ParkSecondaryCore == NULL) {
+ DEBUG ((EFI_D_ERROR, "Warning: ParkSecondaryCore() not supported.\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ // Move secondary cores to our new Pen
+ PenBase = ConfigurePen (MpParkingBase, MpParkingSize, ArmCoreInfoTable, ArmCoreCount);
+ for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) {
+ MpBootProtocol->ParkSecondaryCore (&ArmCoreInfoTable[CoreNum], PenBase);
+ }
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf new file mode 100644 index 0000000..ff6ccb6 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf @@ -0,0 +1,53 @@ +#/* @file
+#
+# Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MpBootDxe
+ FILE_GUID = ff3f9c9b-6d36-4787-9144-6b22acba5e9b
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = MpBootDxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Sources.common]
+ MpBootDxe.c
+
+[Sources.AARCH64]
+ MpBootHelper.S
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ CacheMaintenanceLib
+ BaseMemoryLib
+ DebugLib
+
+[Protocols]
+ gAmdMpBootProtocolGuid ## CONSUMED
+
+[Depex]
+ gAmdMpBootProtocolGuid
diff --git a/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S new file mode 100644 index 0000000..c16cc59 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S @@ -0,0 +1,87 @@ +//
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//**
+// Derived from:
+// ArmPkg/Library/BdsLib/AArch64/BdsLinuxLoaderHelper.S
+//
+//**
+
+/* Secondary core pens for AArch64 Linux booting.
+
+ This code is placed in Linux kernel memory and marked reserved. UEFI ensures
+ that the secondary cores get to this pen and the kernel can then start the
+ cores from here.
+ NOTE: This code must be self-contained.
+*/
+
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(SecondariesPenStart)
+ASM_GLOBAL SecondariesPenEnd
+
+ASM_PFX(SecondariesPenStart):
+ // Registers x0-x3 are reserved for future use and should be set to zero.
+ mov x0, xzr
+ mov x1, xzr
+ mov x2, xzr
+ mov x3, xzr
+
+ mrs x4, mpidr_el1 // Get MPCore register
+ and x5, x4, #ARM_CORE_MASK // Get core number
+ and x4, x4, #ARM_CLUSTER_MASK // Get cluster number
+
+ add x4, x5, x4, LSR #7 // Add scaled cluster number to core number
+ mov x6, x4 // Save a copy to compute mp-parking offset
+
+ ldr x5, AsmMailboxBase // Get mailbox addr relative to PC
+ lsl x4, x4, 3 // Add 8-byte offset for this core
+ add x4, x4, x5 //
+
+ ldr x5, AsmParkingBase // Get mp-parking addr relative to PC
+ lsl x6, x6, 12 // Add 4K-byte offset for this core
+ add x6, x6, x5 //
+
+ mov x5, 1 // Get mp-parking id# at 2K offset
+ lsl x5, x5, 11 //
+ add x5, x5, x6 //
+ ldr x10, [x5] //
+
+1: ldr x5, [x4] // Load jump-addr from spin-table mailbox
+ cmp xzr, x5 // Has the value been set?
+ b.ne 4f // If so, break out of loop
+
+ ldr x5, [x6] // Load mp-parking id#
+ cmp w10, w5 // Is it my id?
+ b.ne 2f // If not, continue polling
+
+ ldr x5, [x6, 8] // Load jump-addr from mp-parking
+ cmp xzr, x5 // Has the value been set?
+ b.ne 3f // If so, break out of loop
+
+2: wfe // Wait a bit
+ b 1b // Wait over, check again
+
+3: str xzr, [x6, 8] // Clear to acknowledge
+ mov x0, x6 // Return mp-parking address
+4: br x5 // Jump to new addr
+
+.align 3 // Make sure the variable below is 8 byte aligned.
+ .global AsmParkingBase
+AsmParkingBase: .xword 0xdeaddeadbeefbeef
+ .global AsmMailboxBase
+AsmMailboxBase: .xword 0xdeaddeadbeefbeef
+
+SecondariesPenEnd:
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c new file mode 100644 index 0000000..fd5bb96 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c @@ -0,0 +1,237 @@ +/** @file
+
+ Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <PiDxe.h>
+#include <Uefi.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Common/CoreState.h>
+#include <Library/ArmSmcLib.h>
+#include <IndustryStandard/ArmStdSmc.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <Protocol/AmdMpCoreInfo.h>
+#include <Protocol/AmdMpBoot.h>
+
+
+STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 };
+STATIC AMD_MP_BOOT_PROTOCOL mAmdMpBootProtocol = { 0 };
+STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 };
+
+
+STATIC
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+ OUT UINTN *NumEntries
+ );
+
+STATIC
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+ IN UINT32 MpId,
+ OUT UINT32 *PmuSpi
+ );
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+AmdStyxGetMpParkingBase (
+ OUT UINTN *MpParkingSize
+ );
+
+STATIC
+VOID
+AmdStyxParkSecondaryCore (
+ ARM_CORE_INFO *ArmCoreInfo,
+ EFI_PHYSICAL_ADDRESS SecondaryEntry
+ );
+
+
+#pragma pack(push, 1)
+typedef struct _PMU_INFO {
+ UINT32 MpId;
+ UINT32 PmuSpi;
+} PMU_INFO;
+
+STATIC
+PMU_INFO mPmuInfo[] = {
+ {0x000, 7},
+ {0x001, 8},
+ {0x100, 9},
+ {0x101, 10},
+ {0x200, 11},
+ {0x201, 12},
+ {0x300, 13},
+ {0x301, 14}
+};
+#pragma pack(pop)
+
+#define MAX_CPUS sizeof(mPmuInfo) / sizeof(PMU_INFO)
+
+
+EFI_STATUS
+EFIAPI
+PlatInitDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MpParkingBase;
+ UINTN MpParkingSize;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+ EFI_HANDLE Handle = NULL;
+
+ DEBUG ((EFI_D_ERROR, "PlatInitDxe Loaded\n"));
+
+ // Get core information
+ ArmCoreCount = 0;
+ ArmCoreInfoTable = AmdStyxGetArmCoreInfoTable (&ArmCoreCount);
+ ASSERT (ArmCoreInfoTable != NULL);
+ ASSERT (ArmCoreCount != 0);
+
+ // Install CoreInfo Protocol
+ mAmdMpCoreInfoProtocol.GetArmCoreInfoTable = AmdStyxGetArmCoreInfoTable;
+ mAmdMpCoreInfoProtocol.GetPmuSpiFromMpId = AmdStyxGetPmuSpiFromMpId;
+ mAmdMpCoreInfoProtocol.GetMpParkingBase = AmdStyxGetMpParkingBase;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gAmdMpCoreInfoProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ (VOID *)&mAmdMpCoreInfoProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Install MP-Boot Protocol
+ if (!FixedPcdGetBool (PcdPsciOsSupport) &&
+ FixedPcdGetBool (PcdTrustedFWSupport)) {
+ // Allocate Parking area (4KB-aligned, 4KB per core) as Reserved memory
+ MpParkingBase = 0;
+ MpParkingSize = ArmCoreCount * SIZE_4KB;
+ Status = gBS->AllocatePages (AllocateAnyPages, EfiReservedMemoryType,
+ EFI_SIZE_TO_PAGES (MpParkingSize),
+ &MpParkingBase);
+ if (EFI_ERROR (Status) || MpParkingBase == 0) {
+ DEBUG ((EFI_D_ERROR, "Warning: Failed to allocate MpParkingBase."));
+ } else {
+ mAmdMpBootInfo.MpParkingBase = MpParkingBase;
+ mAmdMpBootInfo.MpParkingSize = MpParkingSize;
+ mAmdMpBootInfo.ArmCoreInfoTable = ArmCoreInfoTable;
+ mAmdMpBootInfo.ArmCoreCount = ArmCoreCount;
+
+ mAmdMpBootProtocol.ParkSecondaryCore = AmdStyxParkSecondaryCore;
+ mAmdMpBootProtocol.MpBootInfo = &mAmdMpBootInfo;
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gAmdMpBootProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ (VOID *)&mAmdMpBootProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Warning: Failed to install MP-Boot Protocol."));
+ gBS->FreePages (MpParkingBase, EFI_SIZE_TO_PAGES (MpParkingSize));
+ }
+ }
+ }
+
+ return Status;
+}
+
+
+STATIC
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+ OUT UINTN *NumEntries
+ )
+{
+ EFI_HOB_GUID_TYPE *Hob;
+
+ ASSERT (NumEntries != NULL);
+
+ Hob = GetFirstGuidHob (&gAmdStyxMpCoreInfoGuid);
+ if (Hob == NULL) {
+ return NULL;
+ }
+
+ *NumEntries = GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (ARM_CORE_INFO);
+ return GET_GUID_HOB_DATA (Hob);
+}
+
+
+STATIC
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+ IN UINT32 MpId,
+ OUT UINT32 *PmuSpi
+ )
+{
+ UINT32 i;
+
+ for (i = 0; i < MAX_CPUS; ++i) {
+ if (mPmuInfo[ i ].MpId == MpId) {
+ *PmuSpi = mPmuInfo[ i ].PmuSpi;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+
+STATIC
+EFI_PHYSICAL_ADDRESS
+AmdStyxGetMpParkingBase (
+ OUT UINTN *MpParkingSize
+ )
+{
+ ASSERT (MpParkingSize != NULL);
+
+ *MpParkingSize = mAmdMpBootInfo.MpParkingBase;
+ return mAmdMpBootInfo.MpParkingBase;
+}
+
+
+STATIC
+VOID
+AmdStyxParkSecondaryCore (
+ ARM_CORE_INFO *ArmCoreInfo,
+ EFI_PHYSICAL_ADDRESS SecondaryEntry
+ )
+{
+ ARM_SMC_ARGS SmcRegs = {0};
+ UINTN MpId;
+
+ MpId = GET_MPID (ArmCoreInfo->ClusterId, ArmCoreInfo->CoreId);
+
+ SmcRegs.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64;
+ SmcRegs.Arg1 = MpId;
+ SmcRegs.Arg2 = SecondaryEntry;
+ SmcRegs.Arg3 = FixedPcdGet64 (PcdPsciCpuOnContext);
+ ArmCallSmc (&SmcRegs);
+
+ if (SmcRegs.Arg0 == ARM_SMC_PSCI_RET_SUCCESS ||
+ SmcRegs.Arg0 == ARM_SMC_PSCI_RET_ALREADY_ON) {
+ DEBUG ((EFI_D_ERROR, "CPU[MpId] = 0x%X at RUN state.\n", MpId));
+ } else {
+ DEBUG ((EFI_D_ERROR, "Warning: Could not transition CPU[MpId] = 0x%X to RUN state.\n", MpId));
+ }
+}
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf new file mode 100644 index 0000000..2eb77cd --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -0,0 +1,62 @@ +#/* @file
+#
+# Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatInitDxe
+ FILE_GUID = 6ae8bdbc-c0eb-40c5-9b3e-18119c0e2710
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatInitDxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Sources.common]
+ PlatInitDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ ArmSmcLib
+ HobLib
+ PcdLib
+ DebugLib
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid
+
+[Protocols]
+ gAmdMpCoreInfoProtocolGuid ## PRODUCER
+ gAmdMpBootProtocolGuid ## PRODUCER
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+ gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+
+[Depex]
+ TRUE
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c new file mode 100644 index 0000000..61e3734 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -0,0 +1,256 @@ +/** @file
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/ArmLib.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+#include <Ppi/IscpPpi.h>
+#include <Iscp.h>
+
+/*----------------------------------------------------------------------------------------
+ * G L O B A L S
+ *----------------------------------------------------------------------------------------
+ */
+//
+// CoreInfo table
+//
+STATIC ARM_CORE_INFO mAmdMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+ },
+ {
+ // Cluster 1, Core 0
+ 0x1, 0x0,
+ },
+ {
+ // Cluster 1, Core 1
+ 0x1, 0x1,
+ },
+ {
+ // Cluster 2, Core 0
+ 0x2, 0x0,
+ },
+ {
+ // Cluster 2, Core 1
+ 0x2, 0x1,
+ },
+ {
+ // Cluster 3, Core 0
+ 0x3, 0x0,
+ },
+ {
+ // Cluster 3, Core 1
+ 0x3, 0x1,
+ }
+};
+
+//
+// Core count
+//
+STATIC UINTN mAmdCoreCount = sizeof (mAmdMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
+
+
+/*----------------------------------------------------------------------------------------
+ * P P I L I S T
+ *----------------------------------------------------------------------------------------
+ */
+STATIC EFI_PEI_ISCP_PPI *PeiIscpPpi;
+
+
+/*----------------------------------------------------------------------------------------
+ * P P I D E S C R I P T O R
+ *----------------------------------------------------------------------------------------
+ */
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatInitPpiDescriptor =
+{
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gAmdStyxPlatInitPpiGuid,
+ NULL
+};
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ * PlatInitPeiEntryPoint
+ *
+ * Description:
+ * Entry point of the PlatInit PEI module.
+ *
+ * Control flow:
+ * Query platform parameters via ISCP.
+ *
+ * Parameters:
+ * @param[in] FfsHeader EFI_PEI_FILE_HANDLE
+ * @param[in] **PeiServices Pointer to the PEI Services Table.
+ *
+ * @return EFI_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+EFI_STATUS
+EFIAPI
+PlatInitPeiEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FfsHeader,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ AMD_MEMORY_RANGE_DESCRIPTOR IscpMemDescriptor = {0};
+ ISCP_FUSE_INFO IscpFuseInfo = {0};
+ ISCP_CPU_RESET_INFO CpuResetInfo = {0};
+#if DO_XGBE == 1
+ ISCP_MAC_INFO MacAddrInfo = {0};
+ UINT64 MacAddr0, MacAddr1;
+#endif
+ UINTN CpuCoreCount, CpuMap, CpuMapSize;
+ UINTN Index, CoreNum;
+ UINT32 *CpuIdReg = (UINT32 *)FixedPcdGet32 (PcdCpuIdRegister);
+
+ DEBUG ((EFI_D_ERROR, "PlatInit PEIM Loaded\n"));
+
+ // CPUID
+ PcdSet32 (PcdSocCpuId, *CpuIdReg);
+ DEBUG ((EFI_D_ERROR, "SocCpuId = 0x%X\n", PcdGet32 (PcdSocCpuId)));
+
+ // Update core count based on PCD option
+ if (mAmdCoreCount > PcdGet32 (PcdSocCoreCount)) {
+ mAmdCoreCount = PcdGet32 (PcdSocCoreCount);
+ }
+
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ // Get fuse information from ISCP
+ Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo);
+ ASSERT_EFI_ERROR (Status);
+
+ CpuMap = IscpFuseInfo.SocConfiguration.CpuMap;
+ CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount;
+ CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8;
+
+ ASSERT (CpuMap != 0);
+ ASSERT (CpuCoreCount != 0);
+ ASSERT (CpuCoreCount <= CpuMapSize);
+
+ // Update core count based on fusing
+ if (mAmdCoreCount > CpuCoreCount) {
+ mAmdCoreCount = CpuCoreCount;
+ }
+ }
+
+ //
+ // Update per-core information from ISCP
+ //
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ DEBUG ((EFI_D_ERROR, "Warning: Could not get CPU info via ISCP, using default values.\n"));
+ } else {
+ //
+ // Walk CPU map to enumerate active cores
+ //
+ for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) {
+ if (CpuMap & 1) {
+ CpuResetInfo.CoreNum = CoreNum;
+ Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction (
+ PeiServices, &CpuResetInfo );
+ ASSERT_EFI_ERROR (Status);
+ ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED);
+ ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED);
+
+ mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId;
+ mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId;
+
+ DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n",
+ Index, mAmdMpCoreInfoTable[Index].ClusterId,
+ mAmdMpCoreInfoTable[Index].CoreId));
+
+ // Next core in Table
+ ++Index;
+ }
+ // Next core in Map
+ CpuMap >>= 1;
+ }
+
+ // Update core count based on CPU map
+ if (mAmdCoreCount > Index) {
+ mAmdCoreCount = Index;
+ }
+ }
+
+ // Update SocCoreCount on Dynamic PCD
+ if (PcdGet32 (PcdSocCoreCount) != mAmdCoreCount) {
+ PcdSet32 (PcdSocCoreCount, mAmdCoreCount);
+ }
+
+ DEBUG ((EFI_D_ERROR, "SocCoreCount = %d\n", PcdGet32 (PcdSocCoreCount)));
+
+ // Build AmdMpCoreInfo HOB
+ BuildGuidDataHob (&gAmdStyxMpCoreInfoGuid, mAmdMpCoreInfoTable, sizeof (ARM_CORE_INFO) * mAmdCoreCount);
+
+ // Get SystemMemorySize from ISCP
+ IscpMemDescriptor.Size0 = 0;
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ // Update SystemMemorySize on Dynamic PCD
+ if (IscpMemDescriptor.Size0) {
+ PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0);
+ }
+ }
+ if (IscpMemDescriptor.Size0 == 0) {
+ DEBUG ((EFI_D_ERROR, "Warning: Could not get SystemMemorySize via ISCP, using default value.\n"));
+ }
+
+ DEBUG ((EFI_D_ERROR, "SystemMemorySize = %ld\n", PcdGet64 (PcdSystemMemorySize)));
+
+#if DO_XGBE == 1
+ // Get MAC Address from ISCP
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ Status = PeiIscpPpi->ExecuteGetMacAddressTransaction (
+ PeiServices, &MacAddrInfo );
+ ASSERT_EFI_ERROR (Status);
+
+ MacAddr0 = MacAddr1 = 0;
+ for (Index = 0; Index < 6; ++Index) {
+ MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8);
+ MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8);
+ }
+ PcdSet64 (PcdEthMacA, MacAddr0);
+ PcdSet64 (PcdEthMacB, MacAddr1);
+ }
+
+ DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA)));
+ DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB)));
+#endif
+
+ // Let other PEI modules know we're done!
+ Status = (*PeiServices)->InstallPpi (PeiServices, &mPlatInitPpiDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf new file mode 100644 index 0000000..8084fbd --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf @@ -0,0 +1,76 @@ +#/* @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatInitPei
+ FILE_GUID = 769694a4-2572-4f29-a5bb-33d7df7be001
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = PlatInitPeiEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Sources]
+ PlatInitPei.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ BaseMemoryLib
+ HobLib
+ PcdLib
+ DebugLib
+ ArmLib
+ ArmSmcLib
+
+[Ppis]
+ gPeiIscpPpiGuid ## CONSUMER
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMER
+ gAmdStyxPlatInitPpiGuid ## PRODUCER
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid ## PRODUCER
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+
+ gAmdStyxTokenSpaceGuid.PcdEthMacA
+ gAmdStyxTokenSpaceGuid.PcdEthMacB
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdCpuIdRegister
+
+[Depex]
+ gPeiIscpPpiGuid
+
diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c new file mode 100644 index 0000000..5ee5d92 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -0,0 +1,989 @@ +/** @file
+ Static SMBIOS Table for ARM platform
+ Derived from EmulatorPkg package
+
+ Note SMBIOS 2.7.1 Required structures:
+ BIOS Information (Type 0)
+ System Information (Type 1)
+ Board Information (Type 2)
+ System Enclosure (Type 3)
+ Processor Information (Type 4) - CPU Driver
+ Cache Information (Type 7) - For cache that is external to processor
+ System Slots (Type 9) - If system has slots
+ Physical Memory Array (Type 16)
+ Memory Device (Type 17) - For each socketed system-memory Device
+ Memory Array Mapped Address (Type 19) - One per contiguous block per Physical Memroy Array
+ System Boot Information (Type 32)
+
+ Copyright (c) 2012, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2013, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Guid/SmBios.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Protocol/AmdIscpDxeProtocol.h>
+
+/*----------------------------------------------------------------------------------------
+ * E X T E R N S
+ *----------------------------------------------------------------------------------------
+ */
+extern EFI_BOOT_SERVICES *gBS;
+
+
+/*----------------------------------------------------------------------------------------
+ * G L O B A L S
+ *----------------------------------------------------------------------------------------
+ */
+EFI_SMBIOS_PROTOCOL *mSmbiosProtocol;
+AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol;
+ISCP_SMBIOS_INFO mSmbiosInfo;
+
+
+/***********************************************************************
+ SMBIOS data definition TYPE0 BIOS Information
+************************************************************************/
+SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = {
+ { EFI_SMBIOS_TYPE_BIOS_INFORMATION, sizeof (SMBIOS_TABLE_TYPE0), 0 },
+ 1, // Vendor String
+ 2, // BiosVersion String
+ 0xE000, // BiosSegment
+ 3, // BiosReleaseDate String
+ 0x7F, // BiosSize
+ { // BiosCharacteristics
+ 0, // Reserved :2; ///< Bits 0-1.
+ 0, // Unknown :1;
+ 0, // BiosCharacteristicsNotSupported :1;
+ 0, // IsaIsSupported :1;
+ 0, // McaIsSupported :1;
+ 0, // EisaIsSupported :1;
+ 0, // PciIsSupported :1;
+ 0, // PcmciaIsSupported :1;
+ 0, // PlugAndPlayIsSupported :1;
+ 0, // ApmIsSupported :1;
+ 1, // BiosIsUpgradable :1;
+ 1, // BiosShadowingAllowed :1;
+ 0, // VlVesaIsSupported :1;
+ 0, // EscdSupportIsAvailable :1;
+ 0, // BootFromCdIsSupported :1;
+ 1, // SelectableBootIsSupported :1;
+ 0, // RomBiosIsSocketed :1;
+ 0, // BootFromPcmciaIsSupported :1;
+ 0, // EDDSpecificationIsSupported :1;
+ 0, // JapaneseNecFloppyIsSupported :1;
+ 0, // JapaneseToshibaFloppyIsSupported :1;
+ 0, // Floppy525_360IsSupported :1;
+ 0, // Floppy525_12IsSupported :1;
+ 0, // Floppy35_720IsSupported :1;
+ 0, // Floppy35_288IsSupported :1;
+ 0, // PrintScreenIsSupported :1;
+ 0, // Keyboard8042IsSupported :1;
+ 0, // SerialIsSupported :1;
+ 0, // PrinterIsSupported :1;
+ 0, // CgaMonoIsSupported :1;
+ 0, // NecPc98 :1;
+ 0 // ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor
+ ///< and bits 48-63 reserved for System Vendor.
+ },
+ { // BIOSCharacteristicsExtensionBytes[]
+ 0x81, // AcpiIsSupported :1;
+ // UsbLegacyIsSupported :1;
+ // AgpIsSupported :1;
+ // I2OBootIsSupported :1;
+ // Ls120BootIsSupported :1;
+ // AtapiZipDriveBootIsSupported :1;
+ // Boot1394IsSupported :1;
+ // SmartBatteryIsSupported :1;
+ // BIOSCharacteristicsExtensionBytes[1]
+ 0x0a, // BiosBootSpecIsSupported :1;
+ // FunctionKeyNetworkBootIsSupported :1;
+ // TargetContentDistributionEnabled :1;
+ // UefiSpecificationSupported :1;
+ // VirtualMachineSupported :1;
+ // ExtensionByte2Reserved :3;
+ },
+ 0x00, // SystemBiosMajorRelease
+ 0x01, // SystemBiosMinorRelease
+ 0xFF, // EmbeddedControllerFirmwareMajorRelease
+ 0xFF, // EmbeddedControllerFirmwareMinorRelease
+};
+
+CHAR8 *mBIOSInfoType0Strings[] = {
+ "edk2.sourceforge.net", // Vendor String
+ __TIME__, // BiosVersion String
+ __DATE__, // BiosReleaseDate String
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE1 System Information
+************************************************************************/
+SMBIOS_TABLE_TYPE1 mSysInfoType1 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, sizeof (SMBIOS_TABLE_TYPE1), 0 },
+ 1, // Manufacturer String
+ 2, // ProductName String
+ 3, // Version String
+ 4, // SerialNumber String
+ { 0x25EF0280, 0xEC82, 0x42B0, { 0x8F, 0xB6, 0x10, 0xAD, 0xCC, 0xC6, 0x7C, 0x02 } },
+ SystemWakeupTypePowerSwitch,
+ 5, // SKUNumber String
+ 6, // Family String
+};
+CHAR8 *mSysInfoType1Strings[] = {
+ "AMD",
+ "Seattle",
+ "1.0",
+ "System Serial#",
+ "System SKU#",
+ "edk2",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE2 Board Information
+************************************************************************/
+SMBIOS_TABLE_TYPE2 mBoardInfoType2 = {
+ { EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, sizeof (SMBIOS_TABLE_TYPE2), 0 },
+ 1, // Manufacturer String
+ 2, // ProductName String
+ 3, // Version String
+ 4, // SerialNumber String
+ 5, // AssetTag String
+ { // FeatureFlag
+ 1, // Motherboard :1;
+ 0, // RequiresDaughterCard :1;
+ 0, // Removable :1;
+ 0, // Replaceable :1;
+ 0, // HotSwappable :1;
+ 0, // Reserved :3;
+ },
+ 6, // LocationInChassis String
+ 0, // ChassisHandle;
+ BaseBoardTypeMotherBoard, // BoardType;
+ 0, // NumberOfContainedObjectHandles;
+ { 0 } // ContainedObjectHandles[1];
+};
+CHAR8 *mBoardInfoType2Strings[] = {
+ "AMD",
+ "Seattle",
+ "1.0",
+ "Base Board Serial#",
+ "Base Board Asset Tag#",
+ "Part Component",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE3 Enclosure Information
+************************************************************************/
+SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, sizeof (SMBIOS_TABLE_TYPE3), 0 },
+ 1, // Manufacturer String
+ MiscChassisTypeLapTop, // Type;
+ 2, // Version String
+ 3, // SerialNumber String
+ 4, // AssetTag String
+ ChassisStateSafe, // BootupState;
+ ChassisStateSafe, // PowerSupplyState;
+ ChassisStateSafe, // ThermalState;
+ ChassisSecurityStatusNone,// SecurityStatus;
+ { 0, 0, 0, 0 }, // OemDefined[4];
+ 0, // Height;
+ 0, // NumberofPowerCords;
+ 0, // ContainedElementCount;
+ 0, // ContainedElementRecordLength;
+ { { 0 } }, // ContainedElements[1];
+};
+CHAR8 *mEnclosureInfoType3Strings[] = {
+ "AMD",
+ "1.0",
+ "Chassis Board Serial#",
+ "Chassis Board Asset Tag#",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE4 Processor Information
+************************************************************************/
+SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = {
+ { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0},
+ 1, // Socket String
+ ProcessorOther, // ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.
+ ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY2_DATA.
+ 2, // ProcessorManufacture String;
+ { // ProcessorId;
+ { // PROCESSOR_SIGNATURE
+ 0, // ProcessorSteppingId:4;
+ 0, // ProcessorModel: 4;
+ 0, // ProcessorFamily: 4;
+ 0, // ProcessorType: 2;
+ 0, // ProcessorReserved1: 2;
+ 0, // ProcessorXModel: 4;
+ 0, // ProcessorXFamily: 8;
+ 0, // ProcessorReserved2: 4;
+ },
+
+ { // PROCESSOR_FEATURE_FLAGS
+ 0, // ProcessorFpu :1;
+ 0, // ProcessorVme :1;
+ 0, // ProcessorDe :1;
+ 0, // ProcessorPse :1;
+ 0, // ProcessorTsc :1;
+ 0, // ProcessorMsr :1;
+ 0, // ProcessorPae :1;
+ 0, // ProcessorMce :1;
+ 0, // ProcessorCx8 :1;
+ 0, // ProcessorApic :1;
+ 0, // ProcessorReserved1 :1;
+ 0, // ProcessorSep :1;
+ 0, // ProcessorMtrr :1;
+ 0, // ProcessorPge :1;
+ 0, // ProcessorMca :1;
+ 0, // ProcessorCmov :1;
+ 0, // ProcessorPat :1;
+ 0, // ProcessorPse36 :1;
+ 0, // ProcessorPsn :1;
+ 0, // ProcessorClfsh :1;
+ 0, // ProcessorReserved2 :1;
+ 0, // ProcessorDs :1;
+ 0, // ProcessorAcpi :1;
+ 0, // ProcessorMmx :1;
+ 0, // ProcessorFxsr :1;
+ 0, // ProcessorSse :1;
+ 0, // ProcessorSse2 :1;
+ 0, // ProcessorSs :1;
+ 0, // ProcessorReserved3 :1;
+ 0, // ProcessorTm :1;
+ 0, // ProcessorReserved4 :2;
+ }
+ },
+ 3, // ProcessorVersion String;
+ { // Voltage;
+ 1, // ProcessorVoltageCapability5V :1;
+ 1, // ProcessorVoltageCapability3_3V :1;
+ 1, // ProcessorVoltageCapability2_9V :1;
+ 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero.
+ 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero.
+ 0 // ProcessorVoltageIndicateLegacy :1;
+ },
+ 0, // ExternalClock;
+ 0, // MaxSpeed;
+ 0, // CurrentSpeed;
+ 0x41, // Status;
+ ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.
+ 0, // L1CacheHandle;
+ 0, // L2CacheHandle;
+ 0, // L3CacheHandle;
+ 4, // SerialNumber;
+ 5, // AssetTag;
+ 6, // PartNumber;
+ 0, // CoreCount;
+ 0, // EnabledCoreCount;
+ 0, // ThreadCount;
+ 0, // ProcessorCharacteristics;
+ ProcessorFamilyARM, // ARM Processor Family;
+};
+
+CHAR8 *mProcessorInfoType4Strings[] = {
+ "Socket",
+ "ARM",
+#ifdef ARM_CPU_AARCH64
+ "v8",
+#else
+ "v7",
+#endif
+ "1.0",
+ "1.0",
+ "1.0",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE7 Cache Information
+************************************************************************/
+SMBIOS_TABLE_TYPE7 mCacheInfoType7 = {
+ { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 },
+ 1, // SocketDesignation String
+ 0x018A, // Cache Configuration
+ 0x00FF, // Maximum Size 256k
+ 0x00FF, // Install Size 256k
+ { // Supported SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ { // Current SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ 0, // Cache Speed unknown
+ CacheErrorMultiBit, // Error Correction Multi
+ CacheTypeUnknown, // System Cache Type
+ CacheAssociativity2Way // Associativity
+};
+#if (FixedPcdGetBool (PcdIscpSupport))
+CHAR8 *mCacheInfoType7Strings[] = {
+ "L# Cache",
+ NULL
+};
+#else
+CHAR8 *mCacheInfoType7Strings[] = {
+ "Cache1",
+ NULL
+};
+#endif
+
+/***********************************************************************
+ SMBIOS data definition TYPE9 System Slot Information
+************************************************************************/
+SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_SLOTS, sizeof (SMBIOS_TABLE_TYPE9), 0 },
+ 1, // SlotDesignation String
+ SlotTypeOther, // SlotType; ///< The enumeration value from MISC_SLOT_TYPE.
+ SlotDataBusWidthOther, // SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
+ SlotUsageAvailable, // CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.
+ SlotLengthOther, // SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.
+ 0, // SlotID;
+ { // SlotCharacteristics1;
+ 1, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0, // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2;
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0, // Reserved :5; ///< Set to 0.
+ },
+ 0, // SegmentGroupNum;
+ 0, // BusNum;
+ 0, // DevFuncNum;
+};
+CHAR8 *mSysSlotInfoType9Strings[] = {
+ "SD Card",
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE16 Physical Memory ArrayInformation
+************************************************************************/
+SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = {
+ { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 },
+ MemoryArrayLocationSystemBoard, // Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.
+ MemoryArrayUseSystemMemory, // Use; ///< The enumeration value from MEMORY_ARRAY_USE.
+ MemoryErrorCorrectionUnknown, // MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.
+ 0x80000000, // MaximumCapacity;
+ 0xFFFE, // MemoryErrorInformationHandle;
+ 1, // NumberOfMemoryDevices;
+ 0x3fffffffffffffffULL, // ExtendedMaximumCapacity;
+};
+CHAR8 *mPhyMemArrayInfoType16Strings[] = {
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE17 Memory Device Information
+************************************************************************/
+SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = {
+ { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 },
+ 0, // MemoryArrayHandle;
+ 0xFFFE, // MemoryErrorInformationHandle;
+ 0xFFFF, // TotalWidth;
+ 0xFFFF, // DataWidth;
+ 0xFFFF, // Size;
+ MemoryFormFactorUnknown, // FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.
+ 0xff, // DeviceSet;
+ 1, // DeviceLocator String
+ 2, // BankLocator String
+ MemoryTypeDram, // MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.
+ { // TypeDetail;
+ 0, // Reserved :1;
+ 0, // Other :1;
+ 1, // Unknown :1;
+ 0, // FastPaged :1;
+ 0, // StaticColumn :1;
+ 0, // PseudoStatic :1;
+ 0, // Rambus :1;
+ 0, // Synchronous :1;
+ 0, // Cmos :1;
+ 0, // Edo :1;
+ 0, // WindowDram :1;
+ 0, // CacheDram :1;
+ 0, // Nonvolatile :1;
+ 0, // Registered :1;
+ 0, // Unbuffered :1;
+ 0, // Reserved1 :1;
+ },
+ 0, // Speed;
+ 3, // Manufacturer String
+ 0, // SerialNumber String
+ 0, // AssetTag String
+ 0, // PartNumber String
+ 0, // Attributes;
+ 0, // ExtendedSize;
+ 0, // ConfiguredMemoryClockSpeed;
+};
+
+#if (FixedPcdGetBool (PcdIscpSupport))
+CHAR8 *mMemDevInfoType17Strings[ 7 ] = {0};
+#else
+CHAR8 *mMemDevInfoType17Strings[] = {
+ "OS Virtual Memory",
+ "malloc",
+ "OSV",
+ NULL
+};
+#endif
+
+/***********************************************************************
+ SMBIOS data definition TYPE19 Memory Array Mapped Address Information
+************************************************************************/
+SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = {
+ { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 },
+ 0x80000000, // StartingAddress;
+ 0xbfffffff, // EndingAddress;
+ 0, // MemoryArrayHandle;
+ 1, // PartitionWidth;
+ 0, // ExtendedStartingAddress;
+ 0, // ExtendedEndingAddress;
+};
+CHAR8 *mMemArrMapInfoType19Strings[] = {
+ NULL
+};
+
+/***********************************************************************
+ SMBIOS data definition TYPE32 Boot Information
+************************************************************************/
+SMBIOS_TABLE_TYPE32 mBootInfoType32 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, sizeof (SMBIOS_TABLE_TYPE32), 0 },
+ { 0, 0, 0, 0, 0, 0 }, // Reserved[6];
+ BootInformationStatusNoError // BootStatus
+};
+
+CHAR8 *mBootInfoType32Strings[] = {
+ NULL
+};
+
+
+/**
+
+ Create SMBIOS record.
+
+ Converts a fixed SMBIOS structure and an array of pointers to strings into
+ an SMBIOS record where the strings are cat'ed on the end of the fixed record
+ and terminated via a double NULL and add to SMBIOS table.
+
+ SMBIOS_TABLE_TYPE32 gSmbiosType12 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof (SMBIOS_TABLE_TYPE12), 0 },
+ 1 // StringCount
+ };
+
+ CHAR8 *gSmbiosType12Strings[] = {
+ "Not Found",
+ NULL
+ };
+
+ ...
+
+ LogSmbiosData (
+ (EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12,
+ gSmbiosType12Strings
+ );
+
+ @param Template Fixed SMBIOS structure, required.
+ @param StringArray Array of strings to convert to an SMBIOS string pack.
+ NULL is OK.
+**/
+
+EFI_STATUS
+EFIAPI
+LogSmbiosData (
+ IN EFI_SMBIOS_TABLE_HEADER *Template,
+ IN CHAR8 **StringPack
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_TABLE_HEADER *Record;
+ UINTN Index;
+ UINTN StringSize;
+ UINTN Size;
+ CHAR8 *Str;
+
+
+ // Calculate the size of the fixed record and optional string pack
+ Size = Template->Length;
+ if (StringPack == NULL) {
+ // At least a double null is required
+ Size += 2;
+ } else {
+ for (Index = 0; StringPack[Index] != NULL; Index++) {
+ StringSize = AsciiStrSize (StringPack[Index]);
+ Size += StringSize;
+ }
+ if (StringPack[0] == NULL) {
+ // At least a double null is required
+ Size += 1;
+ }
+
+ // Don't forget the terminating double null
+ Size += 1;
+ }
+
+ // Copy over Template
+ Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size);
+ if (Record == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (Record, Template, Template->Length);
+
+ // Append string pack
+ Str = ((CHAR8 *)Record) + Record->Length;
+ for (Index = 0; StringPack[Index] != NULL; Index++) {
+ StringSize = AsciiStrSize (StringPack[Index]);
+ CopyMem (Str, StringPack[Index], StringSize);
+ Str += StringSize;
+ }
+ *Str = 0;
+
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbiosProtocol->Add (
+ mSmbiosProtocol,
+ gImageHandle,
+ &SmbiosHandle,
+ Record
+ );
+
+ ASSERT_EFI_ERROR (Status);
+ FreePool (Record);
+ return Status;
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE0 BIOS Information
+************************************************************************/
+VOID
+BIOSInfoUpdateSmbiosType0 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBIOSInfoType0, mBIOSInfoType0Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE1 System Information
+************************************************************************/
+VOID
+SysInfoUpdateSmbiosType1 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysInfoType1, mSysInfoType1Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE2 Board Information
+************************************************************************/
+VOID
+BoardInfoUpdateSmbiosType2 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBoardInfoType2, mBoardInfoType2Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE3 Enclosure Information
+************************************************************************/
+VOID
+EnclosureInfoUpdateSmbiosType3 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mEnclosureInfoType3, mEnclosureInfoType3Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE4 Processor Information
+************************************************************************/
+VOID
+ProcessorInfoUpdateSmbiosType4 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE4_SMBIOS_INFO *SmbiosT4 = &mSmbiosInfo.SmbiosCpuBuffer.T4[0];
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType4 from ISCP.\n"));
+
+ mProcessorInfoType4.ProcessorType = SmbiosT4->T4ProcType;
+ mProcessorInfoType4.ProcessorFamily = SmbiosT4->T4ProcFamily;
+ mProcessorInfoType4.ProcessorFamily2 = SmbiosT4->T4ProcFamily2;
+ mProcessorInfoType4.ProcessorCharacteristics = SmbiosT4->T4ProcCharacteristics;
+ mProcessorInfoType4.MaxSpeed = SmbiosT4->T4MaxSpeed;
+ mProcessorInfoType4.CurrentSpeed = SmbiosT4->T4CurrentSpeed;
+ mProcessorInfoType4.CoreCount = SmbiosT4->T4CoreCount;
+ mProcessorInfoType4.EnabledCoreCount = SmbiosT4->T4CoreEnabled;
+ mProcessorInfoType4.ThreadCount = SmbiosT4->T4ThreadCount;
+ mProcessorInfoType4.ProcessorUpgrade = SmbiosT4->T4ProcUpgrade;
+ mProcessorInfoType4.Status= (UINT8)SmbiosT4->T4Status;
+ mProcessorInfoType4.ExternalClock = SmbiosT4->T4ExternalClock;
+ CopyMem (&mProcessorInfoType4.ProcessorId.Signature,
+ &SmbiosT4->T4ProcId.ProcIDLsd, sizeof(UINT32));
+ CopyMem (&mProcessorInfoType4.ProcessorId.FeatureFlags,
+ &SmbiosT4->T4ProcId.ProcIDMsd, sizeof(UINT32));
+ CopyMem (&mProcessorInfoType4.Voltage,
+ &SmbiosT4->T4Voltage, sizeof(UINT8));
+#else
+ mProcessorInfoType4.ProcessorType = CentralProcessor;
+ mProcessorInfoType4.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ mProcessorInfoType4.ProcessorFamily2 = ProcessorFamilyARM;
+ #ifdef ARM_CPU_AARCH64
+ mProcessorInfoType4.ProcessorCharacteristics = 0x6C;
+ #else
+ mProcessorInfoType4.ProcessorCharacteristics = 0x68;
+ #endif
+ mProcessorInfoType4.MaxSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz
+ mProcessorInfoType4.CurrentSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz
+ mProcessorInfoType4.CoreCount = PcdGet32(PcdCoreCount);
+ mProcessorInfoType4.EnabledCoreCount = PcdGet32(PcdCoreCount);
+ mProcessorInfoType4.ThreadCount = PcdGet32(PcdCoreCount);
+ mProcessorInfoType4.ProcessorUpgrade = ProcessorUpgradeDaughterBoard;
+#endif
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4, mProcessorInfoType4Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE7 Cache Information
+************************************************************************/
+VOID
+CacheInfoUpdateSmbiosType7 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE7_SMBIOS_INFO *SmbiosT7;
+ SMBIOS_TABLE_TYPE7 dstType7 = {{0}};
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType7 from ISCP.\n"));
+
+ CopyMem ((VOID *) &dstType7.Hdr, (VOID *) &mCacheInfoType7.Hdr, sizeof (SMBIOS_STRUCTURE));
+ dstType7.SocketDesignation = 1; // "L# Cache"
+
+ // L1 cache settings
+ mCacheInfoType7Strings[0][1] = '1'; // "L# Cache" --> "L1 Cache"
+ SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L1[0];
+ dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg;
+ dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize;
+ dstType7.InstalledSize = SmbiosT7->T7InstallSize;
+ CopyMem (&dstType7.SupportedSRAMType,
+ &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+ CopyMem (&dstType7.CurrentSRAMType,
+ &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+ dstType7.CacheSpeed = SmbiosT7->T7CacheSpeed;
+ dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+ dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType;
+ dstType7.Associativity = SmbiosT7->T7Associativity;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+
+ // L2 cache settings
+ mCacheInfoType7Strings[0][1] = '2'; // "L# Cache" --> "L2 Cache"
+ SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L2[0];
+ dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg;
+ dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize;
+ dstType7.InstalledSize = SmbiosT7->T7InstallSize;
+ CopyMem (&dstType7.SupportedSRAMType,
+ &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+ CopyMem (&dstType7.CurrentSRAMType,
+ &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+ dstType7.CacheSpeed = SmbiosT7->T7CacheSpeed;
+ dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+ dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType;
+ dstType7.Associativity = SmbiosT7->T7Associativity;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+
+ // L3 cache settings
+ mCacheInfoType7Strings[0][1] = '3'; // "L# Cache" --> "L3 Cache"
+ SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L3[0];
+ dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg;
+ dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize;
+ dstType7.InstalledSize = SmbiosT7->T7InstallSize;
+ CopyMem (&dstType7.SupportedSRAMType,
+ &SmbiosT7->T7SupportedSramType, sizeof(UINT16));
+ CopyMem (&dstType7.CurrentSRAMType,
+ &SmbiosT7->T7CurrentSramType, sizeof(UINT16));
+ dstType7.CacheSpeed = SmbiosT7->T7CacheSpeed;
+ dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType;
+ dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType;
+ dstType7.Associativity = SmbiosT7->T7Associativity;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings);
+#else
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings);
+#endif
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE9 System Slot Information
+************************************************************************/
+VOID
+SysSlotInfoUpdateSmbiosType9 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysSlotInfoType9, mSysSlotInfoType9Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE16 Physical Memory Array Information
+************************************************************************/
+VOID
+PhyMemArrayInfoUpdateSmbiosType16 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE16_SMBIOS_INFO *SmbiosT16 = &mSmbiosInfo.SmbiosMemBuffer.T16;
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType16 from ISCP.\n"));
+
+ mPhyMemArrayInfoType16.Location = SmbiosT16->Location;
+ mPhyMemArrayInfoType16.Use = SmbiosT16->Use;
+ mPhyMemArrayInfoType16.MemoryErrorCorrection = SmbiosT16->MemoryErrorCorrection;
+ mPhyMemArrayInfoType16.NumberOfMemoryDevices = SmbiosT16->NumberOfMemoryDevices;
+#endif
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings);
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE17 Memory Device Information
+************************************************************************/
+VOID
+MemDevInfoUpdatedstType17 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ SMBIOS_TABLE_TYPE17 dstType17 = {{0}};
+ ISCP_TYPE17_SMBIOS_INFO *srcType17;
+ UINTN i, j, StrIndex, LastIndex;
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType17 from ISCP.\n"));
+
+ LastIndex = (sizeof(mMemDevInfoType17Strings) / sizeof (CHAR8 *)) - 1;
+ for (i = 0; i < 2; ++i) {
+ for (j = 0; j < 2; ++j) {
+ srcType17 = &mSmbiosInfo.SmbiosMemBuffer.T17[i][j];
+
+ CopyMem ((VOID *) &dstType17.Hdr, (VOID *) &mMemDevInfoType17.Hdr, sizeof (SMBIOS_STRUCTURE));
+ dstType17.MemoryArrayHandle = srcType17->Handle;
+ dstType17.TotalWidth = srcType17->TotalWidth;
+ dstType17.DataWidth = srcType17->DataWidth;
+ dstType17.Size = srcType17->MemorySize;
+ dstType17.FormFactor = srcType17->FormFactor;
+ dstType17.DeviceSet = srcType17->DeviceSet;
+ dstType17.MemoryType = srcType17->MemoryType;
+
+ CopyMem ((VOID *) &dstType17.TypeDetail, (VOID *) &mMemDevInfoType17.TypeDetail, sizeof (UINT16));
+ dstType17.Speed = srcType17->Speed;
+ dstType17.Attributes = srcType17->Attributes;
+ dstType17.ExtendedSize = srcType17->ExtSize;
+ dstType17.ConfiguredMemoryClockSpeed = srcType17->ConfigSpeed;
+
+ // Build table of TYPE17 strings
+ StrIndex = 0;
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->DeviceLocator) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->DeviceLocator;
+ dstType17.DeviceLocator = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.DeviceLocator = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->BankLocator) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->BankLocator;
+ dstType17.BankLocator = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.BankLocator = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->ManufacturerIdCode) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->ManufacturerIdCode;
+ dstType17.Manufacturer = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.Manufacturer = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->SerialNumber) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->SerialNumber;
+ dstType17.SerialNumber = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.SerialNumber = 0;
+ }
+
+ if (AsciiStrLen ((CHAR8 *)srcType17->PartNumber) && StrIndex < LastIndex) {
+ mMemDevInfoType17Strings[StrIndex++] = (CHAR8 *)srcType17->PartNumber;
+ dstType17.PartNumber = (SMBIOS_TABLE_STRING) StrIndex;
+ } else {
+ dstType17.PartNumber = 0;
+ }
+
+ mMemDevInfoType17Strings[StrIndex] = NULL;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType17, mMemDevInfoType17Strings);
+ }
+ }
+#else
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings);
+#endif
+}
+
+/***********************************************************************
+ SMBIOS data update TYPE19 Memory Array Map Information
+************************************************************************/
+VOID
+MemArrMapInfoUpdateSmbiosType19 (
+ VOID
+ )
+{
+#if (FixedPcdGetBool (PcdIscpSupport))
+ ISCP_TYPE19_SMBIOS_INFO *SmbiosT19 = &mSmbiosInfo.SmbiosMemBuffer.T19;
+
+ DEBUG ((EFI_D_ERROR, "Logging SmbiosType19 from ISCP.\n"));
+
+ mMemArrMapInfoType19.StartingAddress = SmbiosT19->StartingAddr;
+ mMemArrMapInfoType19.EndingAddress = SmbiosT19->EndingAddr;
+ mMemArrMapInfoType19.MemoryArrayHandle = SmbiosT19->MemoryArrayHandle;
+ mMemArrMapInfoType19.PartitionWidth = SmbiosT19->PartitionWidth;
+ mMemArrMapInfoType19.ExtendedStartingAddress = SmbiosT19->ExtStartingAddr;
+ mMemArrMapInfoType19.ExtendedEndingAddress = SmbiosT19->ExtEndingAddr;
+#endif
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings);
+}
+
+
+/***********************************************************************
+ SMBIOS data update TYPE32 Boot Information
+************************************************************************/
+VOID
+BootInfoUpdateSmbiosType32 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBootInfoType32, mBootInfoType32Strings);
+}
+
+/***********************************************************************
+ Driver Entry
+************************************************************************/
+EFI_STATUS
+EFIAPI
+PlatformSmbiosDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_ERROR, "PlatformSmbiosDxe Loaded\n"));
+
+ //
+ // Locate Smbios protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&mSmbiosProtocol
+ );
+
+ if (EFI_ERROR (Status)) {
+ mSmbiosProtocol = NULL;
+ DEBUG ((EFI_D_ERROR, "Failed to Locate SMBIOS Protocol"));
+ return Status;
+ }
+
+#if (FixedPcdGetBool (PcdIscpSupport))
+ Status = gBS->LocateProtocol (
+ &gAmdIscpDxeProtocolGuid,
+ NULL,
+ (VOID **)&mIscpDxeProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ mIscpDxeProtocol = NULL;
+ DEBUG ((EFI_D_ERROR, "Failed to Locate ISCP DXE Protocol"));
+ return Status;
+ }
+
+ Status = mIscpDxeProtocol-> AmdExecuteSmbiosInfoDxe (
+ mIscpDxeProtocol,
+ &mSmbiosInfo
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Failed to get SMBIOS data via ISCP"));
+ return Status;
+ }
+#endif
+
+ BIOSInfoUpdateSmbiosType0();
+
+ SysInfoUpdateSmbiosType1();
+
+ BoardInfoUpdateSmbiosType2();
+
+ EnclosureInfoUpdateSmbiosType3();
+
+ ProcessorInfoUpdateSmbiosType4();
+
+ CacheInfoUpdateSmbiosType7();
+
+ SysSlotInfoUpdateSmbiosType9();
+
+ PhyMemArrayInfoUpdateSmbiosType16();
+
+ MemDevInfoUpdatedstType17();
+
+ MemArrMapInfoUpdateSmbiosType19();
+
+ BootInfoUpdateSmbiosType32();
+
+ return Status;
+}
diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf new file mode 100644 index 0000000..82684ad --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf @@ -0,0 +1,60 @@ +#/** @file
+# SMBIOS Table for ARM platform
+#
+# Copyright (c) 2013, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformSmbiosDxe
+ FILE_GUID = 3847D23F-1D95-4772-B60C-4BBFBC4D532F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformSmbiosDriverEntryPoint
+
+[Sources]
+ PlatformSmbiosDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ BaseLib
+ UefiLib
+ UefiDriverEntryPoint
+ DebugLib
+
+
+[Protocols]
+ gEfiSmbiosProtocolGuid ## CONSUMER
+ gAmdIscpDxeProtocolGuid ## CONSUMER
+
+[Guids]
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+[Depex]
+ gEfiSmbiosProtocolGuid AND
+ gAmdIscpDxeProtocolGuid
+
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/ComponentName.c b/Platforms/AMD/Styx/Drivers/SataControllerDxe/ComponentName.c new file mode 100644 index 0000000..943daac --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/ComponentName.c @@ -0,0 +1,178 @@ +/** @file
+ UEFI Component Name(2) protocol implementation for Sata Controller driver.
+
+ Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SataController.h"
+
+//
+/// EFI Component Name Protocol
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName = {
+ SataControllerComponentNameGetDriverName,
+ SataControllerComponentNameGetControllerName,
+ "eng"
+};
+
+//
+/// EFI Component Name 2 Protocol
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SataControllerComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SataControllerComponentNameGetControllerName,
+ "en"
+};
+
+//
+/// Driver Name Strings
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverNameTable[] = {
+ {
+ "eng;en",
+ (CHAR16 *)L"Sata Controller Init Driver"
+ },
+ {
+ NULL,
+ NULL
+ }
+};
+
+///
+/// Controller Name Strings
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerControllerNameTable[] = {
+ {
+ "eng;en",
+ (CHAR16 *)L"Sata Controller"
+ },
+ {
+ NULL,
+ NULL
+ }
+};
+
+/**
+ Retrieves a Unicode string that is the user readable name of the UEFI Driver.
+
+ @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param Language A pointer to a three character ISO 639-2 language identifier.
+ This is the language of the driver name that that the caller
+ is requesting, and it must match one of the languages specified
+ in SupportedLanguages. The number of languages supported by a
+ driver is up to the driver writer.
+ @param DriverName A pointer to the Unicode string to return. This Unicode string
+ is the name of the driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by This
+ and the language specified by Language was returned
+ in DriverName.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+**/
+EFI_STATUS
+EFIAPI
+SataControllerComponentNameGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ )
+{
+ return LookupUnicodeString2 (
+ Language,
+ This->SupportedLanguages,
+ mSataControllerDriverNameTable,
+ DriverName,
+ (BOOLEAN)(This == &gSataControllerComponentName)
+ );
+}
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by an UEFI Driver.
+
+ @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param ControllerHandle The handle of a controller that the driver specified by
+ This is managing. This handle specifies the controller
+ whose name is to be returned.
+ @param ChildHandle OPTIONAL The handle of the child controller to retrieve the name
+ of. This is an optional parameter that may be NULL. It
+ will be NULL for device drivers. It will also be NULL
+ for a bus drivers that wish to retrieve the name of the
+ bus controller. It will not be NULL for a bus driver
+ that wishes to retrieve the name of a child controller.
+ @param Language A pointer to a three character ISO 639-2 language
+ identifier. This is the language of the controller name
+ that that the caller is requesting, and it must match one
+ of the languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up to the
+ driver writer.
+ @param ControllerName A pointer to the Unicode string to return. This Unicode
+ string is the name of the controller specified by
+ ControllerHandle and ChildHandle in the language
+ specified by Language from the point of view of the
+ driver specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in the
+ language specified by Language for the driver
+ specified by This was returned in DriverName.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+**/
+EFI_STATUS
+EFIAPI
+SataControllerComponentNameGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Make sure this driver is currently managing ControllHandle
+ //
+ Status = EfiTestManagedDevice (
+ ControllerHandle,
+ gSataControllerDriverBinding.DriverBindingHandle,
+ &gEfiPciIoProtocolGuid
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (ChildHandle != NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return LookupUnicodeString2 (
+ Language,
+ This->SupportedLanguages,
+ mSataControllerControllerNameTable,
+ ControllerName,
+ (BOOLEAN)(This == &gSataControllerComponentName)
+ );
+}
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/InitController.c b/Platforms/AMD/Styx/Drivers/SataControllerDxe/InitController.c new file mode 100644 index 0000000..f605bf7 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/InitController.c @@ -0,0 +1,172 @@ +/** @file
+ Initialize SATA Phy, Serdes, and Controller.
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "SataController.h"
+#include <Library/IoLib.h>
+#include "SataRegisters.h"
+#include "PciEmulation.h"
+#include <Library/AmdSataInitLib.h>
+
+VOID
+ResetSataController (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr
+ )
+{
+ UINT32 RegVal;
+
+ // Make a minimal global reset for HBA regiser
+ RegVal = MmioRead32(AhciBaseAddr + EFI_AHCI_GHC_OFFSET);
+ RegVal |= EFI_AHCI_GHC_RESET;
+ MmioWrite32(AhciBaseAddr + EFI_AHCI_GHC_OFFSET, RegVal);
+
+ // Clear all interrupts
+ MmioWrite32(AhciBaseAddr + EFI_AHCI_PORT_IS, EFI_AHCI_PORT_IS_CLEAR);
+
+ // Turn on interrupts and ensure that the HBA is working in AHCI mode
+ RegVal = MmioRead32(AhciBaseAddr + EFI_AHCI_GHC_OFFSET);
+ RegVal |= EFI_AHCI_GHC_IE | EFI_AHCI_GHC_ENABLE;
+ MmioWrite32(AhciBaseAddr + EFI_AHCI_GHC_OFFSET, RegVal);
+}
+
+
+VOID
+SetSataCapabilities (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr
+ )
+{
+ UINT32 Capability;
+
+ Capability = MmioRead32(AhciBaseAddr + EFI_AHCI_CAPABILITY_OFFSET);
+ if (PcdGetBool(PcdSataSssSupport)) // Staggered Spin-Up Support bit
+ Capability |= EFI_AHCI_CAP_SSS;
+ if (PcdGetBool(PcdSataSmpsSupport)) // Mechanical Presence Support bit
+ Capability |= EFI_AHCI_CAP_SMPS;
+ MmioWrite32(AhciBaseAddr + EFI_AHCI_CAPABILITY_OFFSET, Capability);
+}
+
+
+VOID
+InitializeSataPorts (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr
+ )
+{
+ INTN PortNum;
+ UINT32 SataPi;
+ BOOLEAN IsPortImplemented;
+ BOOLEAN IsCpd;
+ BOOLEAN IsMpsp;
+ UINT32 PortRegAddr;
+ UINT32 RegVal;
+
+ // Set Ports Implemented (PI)
+ SataPi = PcdGet32(PcdSataPi);
+ MmioWrite32(AhciBaseAddr + EFI_AHCI_PI_OFFSET, SataPi);
+
+ IsCpd = PcdGetBool(PcdSataPortCpd);
+ IsMpsp = PcdGetBool(PcdSataPortMpsp);
+ for (PortNum = 0; PortNum < EFI_AHCI_MAX_PORTS; PortNum++) {
+ IsPortImplemented = (SataPi & (1 << PortNum)) ? 1 : 0;
+ if (IsPortImplemented && (IsCpd || IsMpsp)) {
+ PortRegAddr = EFI_AHCI_PORT_OFFSET(PortNum) + EFI_AHCI_PORT_CMD;
+ RegVal = MmioRead32(AhciBaseAddr + PortRegAddr);
+ if (IsCpd)
+ RegVal |= EFI_AHCI_PORT_CMD_CPD;
+ else
+ RegVal &= ~EFI_AHCI_PORT_CMD_CPD;
+ if (IsMpsp)
+ RegVal |= EFI_AHCI_PORT_CMD_MPSP;
+ else
+ RegVal &= ~EFI_AHCI_PORT_CMD_MPSP;
+ RegVal |= EFI_AHCI_PORT_CMD_HPCP;
+ MmioWrite32(AhciBaseAddr + PortRegAddr, RegVal);
+ }
+ }
+}
+
+
+EFI_STATUS
+InitializeSataController (
+ VOID
+ )
+{
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr;
+ UINT8 SataPortCount;
+ UINT8 SataChPerSerdes;
+ UINT32 StartPort;
+ UINT32 PortNum;
+ UINT32 EvenPort;
+ UINT32 OddPort;
+ EFI_STATUS Status;
+
+#ifdef BUILD_FOR_SATA1
+ AhciBaseAddr = PcdGet32(PcdSata1CtrlAxiSlvPort);
+ SataPortCount = PcdGet8(PcdSata1PortCount);
+ StartPort = PcdGet8(PcdSataPortCount);
+#else
+ AhciBaseAddr = PcdGet32(PcdSataCtrlAxiSlvPort);
+ SataPortCount = PcdGet8(PcdSataPortCount);
+ StartPort = 0;
+#endif
+
+ SataChPerSerdes = PcdGet8(PcdSataNumChPerSerdes);
+
+ //
+ // Perform SATA workarounds
+ //
+ for (PortNum = 0; PortNum < SataPortCount; PortNum++) {
+#ifdef BUILD_FOR_SATA1
+ SetCwMinSata1(PortNum);
+#else
+ SetCwMinSata0(PortNum);
+#endif
+ }
+
+ for (PortNum = 0; PortNum < SataPortCount; PortNum += SataChPerSerdes) {
+ EvenPort = (UINT32)(PcdGet16(PcdSataPortMode) >> (PortNum * 2)) & 3;
+ OddPort = (UINT32)(PcdGet16(PcdSataPortMode) >> ((PortNum+1) * 2)) & 3;
+ SataPhyInit((StartPort + PortNum)/SataChPerSerdes, EvenPort, OddPort);
+ }
+
+ for (PortNum = 0; PortNum < SataPortCount; PortNum++) {
+#ifdef BUILD_FOR_SATA1
+ SetPrdSingleSata1(PortNum);
+#else
+ SetPrdSingleSata0(PortNum);
+#endif
+ }
+
+ //
+ // Reset SATA controller
+ //
+ ResetSataController(AhciBaseAddr);
+
+ //
+ // Set SATA capabilities
+ //
+ SetSataCapabilities(AhciBaseAddr);
+
+ //
+ // Set and intialize the Sata ports
+ //
+ InitializeSataPorts(AhciBaseAddr);
+
+ //
+ // Emulate a PCI configuration for this device
+ //
+ Status = PciEmulationEntryPoint(AhciBaseAddr);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciEmulation.c b/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciEmulation.c new file mode 100644 index 0000000..137a486 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciEmulation.c @@ -0,0 +1,442 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+#include "SataRegisters.h"
+
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ PCI_DEVICE_PATH PciDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_IO_DEVICE_PATH;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_PCI_IO_DEVICE_PATH DevicePath;
+ EFI_PCI_IO_PROTOCOL PciIoProtocol;
+ PCI_TYPE00 *ConfigSpace;
+ PCI_ROOT_BRIDGE RootBridge;
+ UINTN Segment;
+} EFI_PCI_IO_PRIVATE_DATA;
+
+#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
+#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
+
+EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
+{
+ {
+ { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },
+ EISA_PNP_ID(0x0A03), // HID
+ 0 // UID
+ },
+ {
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },
+ 0,
+ 0
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }
+};
+
+
+EFI_STATUS
+PciIoPollMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoPollIo (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMemRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoMemWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoIoRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoIoWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoPciRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ Count,
+ TRUE,
+ (PTR)(UINTN)Buffer,
+ TRUE,
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)
+ );
+}
+
+EFI_STATUS
+PciIoPciWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Count,
+ TRUE,
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
+ TRUE,
+ (PTR)(UINTN)Buffer
+ );
+}
+
+EFI_STATUS
+PciIoCopyMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ *DeviceAddress = (EFI_PHYSICAL_ADDRESS) HostAddress;
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoUnmap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+PciIoAllocateBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ )
+{
+ EFI_PHYSICAL_ADDRESS Memory;
+ EFI_STATUS Status;
+
+ if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+ // Check this
+ return EFI_UNSUPPORTED;
+ }
+ Status = gBS->AllocatePages(AllocateAnyPages, MemoryType, Pages, &Memory);
+ if (Status == EFI_SUCCESS)
+ *HostAddress = (VOID *)Memory;
+ return Status;
+}
+
+
+EFI_STATUS
+PciIoFreeBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
+ )
+{
+ return gBS->FreePages((EFI_PHYSICAL_ADDRESS)HostAddress, Pages);
+}
+
+
+EFI_STATUS
+PciIoFlush (
+ IN EFI_PCI_IO_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoGetLocation (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ OUT UINTN *SegmentNumber,
+ OUT UINTN *BusNumber,
+ OUT UINTN *DeviceNumber,
+ OUT UINTN *FunctionNumber
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ if (SegmentNumber != NULL) {
+ *SegmentNumber = Private->Segment;
+ }
+
+ if (BusNumber != NULL) {
+ *BusNumber = 0xff;
+ }
+
+ if (DeviceNumber != NULL) {
+ *DeviceNumber = 0;
+ }
+
+ if (FunctionNumber != NULL) {
+ *FunctionNumber = 0;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
+ IN UINT64 Attributes,
+ OUT UINT64 *Result OPTIONAL
+ )
+{
+ switch (Operation) {
+ case EfiPciIoAttributeOperationGet:
+ case EfiPciIoAttributeOperationSupported:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ // We are not a real PCI device so just say things we kind of do
+ *Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;
+ break;
+
+ case EfiPciIoAttributeOperationSet:
+ case EfiPciIoAttributeOperationEnable:
+ case EfiPciIoAttributeOperationDisable:
+ // Since we are not a real PCI device no enable/set or disable operations exist.
+ return EFI_SUCCESS;
+
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ };
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoGetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports, OPTIONAL
+ OUT VOID **Resources OPTIONAL
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoSetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_PCI_IO_PROTOCOL PciIoTemplate =
+{
+ PciIoPollMem,
+ PciIoPollIo,
+ { PciIoMemRead, PciIoMemWrite },
+ { PciIoIoRead, PciIoIoWrite },
+ { PciIoPciRead, PciIoPciWrite },
+ PciIoCopyMem,
+ PciIoMap,
+ PciIoUnmap,
+ PciIoAllocateBuffer,
+ PciIoFreeBuffer,
+ PciIoFlush,
+ PciIoGetLocation,
+ PciIoAttributes,
+ PciIoGetBarAttributes,
+ PciIoSetBarAttributes,
+ 0,
+ 0
+};
+
+EFI_STATUS
+PciEmulationEntryPoint (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+
+ // Create a private structure
+ Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));
+ if (Private == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+
+ Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
+ Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
+ Private->RootBridge.MemoryStart = AhciBaseAddr; // Get the SATA capability register base
+ Private->Segment = 0; // Default to segment zero
+
+ // Total size of the SATA registers.
+ Private->RootBridge.MemorySize = 1024;
+
+ // Create fake PCI config space.
+ Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));
+ if (Private->ConfigSpace == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ FreePool(Private);
+ return Status;
+ }
+
+ // Configure PCI config space
+ Private->ConfigSpace->Hdr.VendorId = 0x3530;
+ Private->ConfigSpace->Hdr.DeviceId = 0x3530;
+ Private->ConfigSpace->Hdr.ClassCode[0] = PCI_IF_APIC_CONTROLLER2;
+ Private->ConfigSpace->Hdr.ClassCode[1] = PCI_CLASS_MASS_STORAGE_SATADPA;
+ Private->ConfigSpace->Hdr.ClassCode[2] = PCI_CLASS_MASS_STORAGE;
+ Private->ConfigSpace->Device.Bar[EFI_AHCI_BAR_INDEX] = Private->RootBridge.MemoryStart;
+
+ Handle = NULL;
+
+ // Unique device path.
+ CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));
+ Private->DevicePath.AcpiDevicePath.UID = 1;
+
+ // Copy protocol structure
+ CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));
+
+ Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
+ &gEfiPciIoProtocolGuid, &Private->PciIoProtocol,
+ &gEfiDevicePathProtocolGuid, &Private->DevicePath,
+ NULL);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));
+ }
+
+ return Status;
+}
+
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciEmulation.h b/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciEmulation.h new file mode 100644 index 0000000..067aea2 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciEmulation.h @@ -0,0 +1,289 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCI_ROOT_BRIDGE_H_
+#define _PCI_ROOT_BRIDGE_H_
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DmaLib.h>
+
+#include <Protocol/EmbeddedExternalDevice.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#include <IndustryStandard/Pci22.h>
+#include <IndustryStandard/Pci30.h>
+#include <IndustryStandard/Acpi.h>
+
+
+
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL
+
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+
+#define ACPI_CONFIG_IO 0
+#define ACPI_CONFIG_MMIO 1
+#define ACPI_CONFIG_BUS 2
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
+ EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
+} ACPI_CONFIG_INFO;
+
+
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
+
+ UINT8 StartBus;
+ UINT8 EndBus;
+ UINT16 Type;
+ UINT32 MemoryStart;
+ UINT32 MemorySize;
+ UINTN IoOffset;
+ UINT32 IoStart;
+ UINT32 IoSize;
+ UINT64 PciAttributes;
+
+ ACPI_CONFIG_INFO *Config;
+
+} PCI_ROOT_BRIDGE;
+
+
+#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
+
+
+typedef union {
+ UINT8 volatile *buf;
+ UINT8 volatile *ui8;
+ UINT16 volatile *ui16;
+ UINT32 volatile *ui32;
+ UINT64 volatile *ui64;
+ UINTN volatile ui;
+} PTR;
+
+
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollIo (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoCopyMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoUnmap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoAllocateBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFreeBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ OUT VOID *HostAddress
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFlush (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoGetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT UINT64 *Supported,
+ OUT UINT64 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoSetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN OUT UINT64 *ResourceBase,
+ IN OUT UINT64 *ResourceLength
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoConfiguration (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
+ );
+
+//
+// Private Function Prototypes
+//
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINTN Count,
+ IN BOOLEAN InStrideFlag,
+ IN PTR In,
+ IN BOOLEAN OutStrideFlag,
+ OUT PTR Out
+ );
+
+BOOLEAN
+PciIoMemAddressValid (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Address
+ );
+
+EFI_STATUS
+PciEmulationEntryPoint (
+ EFI_PHYSICAL_ADDRESS AhciBaseAddr
+ );
+
+#endif
+
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciRootBridgeIo.c b/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciRootBridgeIo.c new file mode 100644 index 0000000..9fcb402 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/PciRootBridgeIo.c @@ -0,0 +1,307 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+
+BOOLEAN
+PciRootBridgeMemAddressValid (
+ IN PCI_ROOT_BRIDGE *Private,
+ IN UINT64 Address
+ )
+{
+ if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+EFI_STATUS
+PciRootBridgeIoMemRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINTN Count,
+ IN BOOLEAN InStrideFlag,
+ IN PTR In,
+ IN BOOLEAN OutStrideFlag,
+ OUT PTR Out
+ )
+{
+ UINTN Stride;
+ UINTN InStride;
+ UINTN OutStride;
+
+
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Stride = (UINTN)1 << Width;
+ InStride = InStrideFlag ? Stride : 0;
+ OutStride = OutStrideFlag ? Stride : 0;
+
+ //
+ // Loop for each iteration and move the data
+ //
+ switch (Width) {
+ case EfiPciWidthUint8:
+ for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
+ *In.ui8 = *Out.ui8;
+ }
+ break;
+ case EfiPciWidthUint16:
+ for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
+ *In.ui16 = *Out.ui16;
+ }
+ break;
+ case EfiPciWidthUint32:
+ for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
+ *In.ui32 = *Out.ui32;
+ }
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciRootBridgeIoPciRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN BOOLEAN Write,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+ UINTN AlignMask;
+ PTR In;
+ PTR Out;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ AlignMask = (1 << (Width & 0x03)) - 1;
+ if (Address & AlignMask) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ In.buf = Buffer;
+ Out.buf = (VOID *)(UINTN) Address;
+
+ switch (Width) {
+ case EfiPciWidthUint8:
+ case EfiPciWidthUint16:
+ case EfiPciWidthUint32:
+ case EfiPciWidthUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
+
+ case EfiPciWidthFifoUint8:
+ case EfiPciWidthFifoUint16:
+ case EfiPciWidthFifoUint32:
+ case EfiPciWidthFifoUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
+
+ case EfiPciWidthFillUint8:
+ case EfiPciWidthFillUint16:
+ case EfiPciWidthFillUint32:
+ case EfiPciWidthFillUint64:
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
+
+ default:
+ break;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+ UINTN AlignMask;
+ PTR In;
+ PTR Out;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ AlignMask = (1 << (Width & 0x03)) - 1;
+ if (Address & AlignMask) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ In.buf = (VOID *)(UINTN) Address;
+ Out.buf = Buffer;
+
+ switch (Width) {
+ case EfiPciWidthUint8:
+ case EfiPciWidthUint16:
+ case EfiPciWidthUint32:
+ case EfiPciWidthUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
+
+ case EfiPciWidthFifoUint8:
+ case EfiPciWidthFifoUint16:
+ case EfiPciWidthFifoUint32:
+ case EfiPciWidthFifoUint64:
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
+
+ case EfiPciWidthFillUint8:
+ case EfiPciWidthFillUint16:
+ case EfiPciWidthFillUint32:
+ case EfiPciWidthFillUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
+
+ default:
+ break;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
+}
+
+
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataController.c b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataController.c new file mode 100644 index 0000000..93d940c --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataController.c @@ -0,0 +1,1027 @@ +/** @file
+ This driver module produces IDE_CONTROLLER_INIT protocol for Sata Controllers.
+
+ Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SataController.h"
+
+///
+/// EFI_DRIVER_BINDING_PROTOCOL instance
+///
+EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding = {
+ SataControllerSupported,
+ SataControllerStart,
+ SataControllerStop,
+ 0xa,
+ NULL,
+ NULL
+};
+
+/**
+ Read AHCI Operation register.
+
+ @param PciIo The PCI IO protocol instance.
+ @param Offset The operation register offset.
+
+ @return The register content read.
+
+**/
+UINT32
+EFIAPI
+AhciReadReg (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset
+ )
+{
+ UINT32 Data;
+
+ ASSERT (PciIo != NULL);
+
+ Data = 0;
+
+ PciIo->Mem.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ AHCI_BAR_INDEX,
+ (UINT64) Offset,
+ 1,
+ &Data
+ );
+
+ return Data;
+}
+
+/**
+ Write AHCI Operation register.
+
+ @param PciIo The PCI IO protocol instance.
+ @param Offset The operation register offset.
+ @param Data The data used to write down.
+
+**/
+VOID
+EFIAPI
+AhciWriteReg (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ )
+{
+ ASSERT (PciIo != NULL);
+
+ PciIo->Mem.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ AHCI_BAR_INDEX,
+ (UINT64) Offset,
+ 1,
+ &Data
+ );
+
+ return;
+}
+
+/**
+ This function is used to calculate the best PIO mode supported by specific IDE device
+
+ @param IdentifyData The identify data of specific IDE device.
+ @param DisPioMode Disqualified PIO modes collection.
+ @param SelectedMode Available PIO modes collection.
+
+ @retval EFI_SUCCESS Best PIO modes are returned.
+ @retval EFI_UNSUPPORTED The device doesn't support PIO mode,
+ or all supported modes have been disqualified.
+**/
+EFI_STATUS
+CalculateBestPioMode (
+ IN EFI_IDENTIFY_DATA *IdentifyData,
+ IN UINT16 *DisPioMode OPTIONAL,
+ OUT UINT16 *SelectedMode
+ )
+{
+ UINT16 PioMode;
+ UINT16 AdvancedPioMode;
+ UINT16 Temp;
+ UINT16 Index;
+ UINT16 MinimumPioCycleTime;
+
+ Temp = 0xff;
+
+DEBUG ((EFI_D_INFO, "CalculateBestPioMode()\n"));
+
+ PioMode = (UINT8) (((ATA5_IDENTIFY_DATA *) (&(IdentifyData->AtaData)))->pio_cycle_timing >> 8);
+
+ //
+ // See whether Identify Data word 64 - 70 are valid
+ //
+ if ((IdentifyData->AtaData.field_validity & 0x02) == 0x02) {
+
+ AdvancedPioMode = IdentifyData->AtaData.advanced_pio_modes;
+ DEBUG ((EFI_D_INFO, "CalculateBestPioMode: AdvancedPioMode = %x\n", AdvancedPioMode));
+
+ for (Index = 0; Index < 8; Index++) {
+ if ((AdvancedPioMode & 0x01) != 0) {
+ Temp = Index;
+ }
+
+ AdvancedPioMode >>= 1;
+ }
+
+ //
+ // If Temp is modified, mean the advanced_pio_modes is not zero;
+ // if Temp is not modified, mean there is no advanced PIO mode supported,
+ // the best PIO Mode is the value in pio_cycle_timing.
+ //
+ if (Temp != 0xff) {
+ AdvancedPioMode = (UINT16) (Temp + 3);
+ } else {
+ AdvancedPioMode = PioMode;
+ }
+
+ //
+ // Limit the PIO mode to at most PIO4.
+ //
+ PioMode = (UINT16) MIN (AdvancedPioMode, 4);
+
+ MinimumPioCycleTime = IdentifyData->AtaData.min_pio_cycle_time_with_flow_control;
+
+ if (MinimumPioCycleTime <= 120) {
+ PioMode = (UINT16) MIN (4, PioMode);
+ } else if (MinimumPioCycleTime <= 180) {
+ PioMode = (UINT16) MIN (3, PioMode);
+ } else if (MinimumPioCycleTime <= 240) {
+ PioMode = (UINT16) MIN (2, PioMode);
+ } else {
+ PioMode = 0;
+ }
+
+ //
+ // Degrade the PIO mode if the mode has been disqualified
+ //
+ if (DisPioMode != NULL) {
+ if (*DisPioMode < 2) {
+ return EFI_UNSUPPORTED; // no mode below ATA_PIO_MODE_BELOW_2
+ }
+
+ if (PioMode >= *DisPioMode) {
+ PioMode = (UINT16) (*DisPioMode - 1);
+ }
+ }
+
+ if (PioMode < 2) {
+ *SelectedMode = 1; // ATA_PIO_MODE_BELOW_2;
+ } else {
+ *SelectedMode = PioMode; // ATA_PIO_MODE_2 to ATA_PIO_MODE_4;
+ }
+
+ } else {
+ //
+ // Identify Data word 64 - 70 are not valid
+ // Degrade the PIO mode if the mode has been disqualified
+ //
+ if (DisPioMode != NULL) {
+ if (*DisPioMode < 2) {
+ return EFI_UNSUPPORTED; // no mode below ATA_PIO_MODE_BELOW_2
+ }
+
+ if (PioMode == *DisPioMode) {
+ PioMode--;
+ }
+ }
+
+ if (PioMode < 2) {
+ *SelectedMode = 1; // ATA_PIO_MODE_BELOW_2;
+ } else {
+ *SelectedMode = 2; // ATA_PIO_MODE_2;
+ }
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is used to calculate the best UDMA mode supported by specific IDE device
+
+ @param IdentifyData The identify data of specific IDE device.
+ @param DisUDmaMode Disqualified UDMA modes collection.
+ @param SelectedMode Available UDMA modes collection.
+
+ @retval EFI_SUCCESS Best UDMA modes are returned.
+ @retval EFI_UNSUPPORTED The device doesn't support UDMA mode,
+ or all supported modes have been disqualified.
+**/
+EFI_STATUS
+CalculateBestUdmaMode (
+ IN EFI_IDENTIFY_DATA *IdentifyData,
+ IN UINT16 *DisUDmaMode OPTIONAL,
+ OUT UINT16 *SelectedMode
+ )
+{
+ UINT16 TempMode;
+ UINT16 DeviceUDmaMode;
+
+ DeviceUDmaMode = 0;
+
+DEBUG ((EFI_D_INFO, "CalculateBestUdmaMode()\n"));
+ //
+ // Check whether the WORD 88 (supported UltraDMA by drive) is valid
+ //
+ if ((IdentifyData->AtaData.field_validity & 0x04) == 0x00) {
+ return EFI_UNSUPPORTED;
+ }
+
+ DeviceUDmaMode = IdentifyData->AtaData.ultra_dma_mode;
+ DEBUG ((EFI_D_INFO, "CalculateBestUdmaMode: DeviceUDmaMode = %x\n", DeviceUDmaMode));
+ DeviceUDmaMode &= 0x3f;
+ TempMode = 0; // initialize it to UDMA-0
+
+ while ((DeviceUDmaMode >>= 1) != 0) {
+ TempMode++;
+ }
+
+ //
+ // Degrade the UDMA mode if the mode has been disqualified
+ //
+ if (DisUDmaMode != NULL) {
+ if (*DisUDmaMode == 0) {
+ *SelectedMode = 0;
+ return EFI_UNSUPPORTED; // no mode below ATA_UDMA_MODE_0
+ }
+
+ if (TempMode >= *DisUDmaMode) {
+ TempMode = (UINT16) (*DisUDmaMode - 1);
+ }
+ }
+
+ //
+ // Possible returned mode is between ATA_UDMA_MODE_0 and ATA_UDMA_MODE_5
+ //
+ *SelectedMode = TempMode;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The Entry Point of module. It follows the standard UEFI driver model.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeSataControllerDriver (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+DEBUG ((EFI_D_INFO, "InitializeSataControllerDriver()\n"));
+ //
+ // Initialize the SATA controller
+ //
+ Status = InitializeSataController();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install driver model protocol(s).
+ //
+ Status = EfiLibInstallDriverBindingComponentName2 (
+ ImageHandle,
+ SystemTable,
+ &gSataControllerDriverBinding,
+ ImageHandle,
+ &gSataControllerComponentName,
+ &gSataControllerComponentName2
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Supported function of Driver Binding protocol for this driver.
+ Test to see if this driver supports ControllerHandle.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to test.
+ @param RemainingDevicePath A pointer to the device path.
+ it should be ignored by device driver.
+
+ @retval EFI_SUCCESS This driver supports this device.
+ @retval EFI_ALREADY_STARTED This driver is already running on this device.
+ @retval other This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+SataControllerSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 PciData;
+
+//DEBUG ((EFI_D_INFO, "SataControllerSupported()\n"));
+ //
+ // Attempt to open PCI I/O Protocol
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Now further check the PCI header: Base Class (offset 0x0B) and
+ // Sub Class (offset 0x0A). This controller should be an SATA controller
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_CLASSCODE_OFFSET,
+ sizeof (PciData.Hdr.ClassCode),
+ PciData.Hdr.ClassCode
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (IS_PCI_IDE (&PciData) || IS_PCI_SATADPA (&PciData)) {
+ return EFI_SUCCESS;
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ This routine is called right after the .Supported() called and
+ Start this driver on ControllerHandle.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to bind driver to.
+ @param RemainingDevicePath A pointer to the device path.
+ it should be ignored by device driver.
+
+ @retval EFI_SUCCESS This driver is added to this device.
+ @retval EFI_ALREADY_STARTED This driver is already running on this device.
+ @retval other Some error occurs when binding this driver to this device.
+
+**/
+EFI_STATUS
+EFIAPI
+SataControllerStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 PciData;
+ EFI_SATA_CONTROLLER_PRIVATE_DATA *SataPrivateData;
+ UINT32 Data32;
+ UINTN ChannelDeviceCount;
+
+ DEBUG ((EFI_D_INFO, "SataControllerStart START\n"));
+
+ SataPrivateData = NULL;
+
+ //
+ // Now test and open PCI I/O Protocol
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "SataControllerStart error return status = %r\n", Status));
+ return Status;
+ }
+
+ //
+ // Allocate Sata Private Data structure
+ //
+ SataPrivateData = AllocateZeroPool (sizeof (EFI_SATA_CONTROLLER_PRIVATE_DATA));
+ if (SataPrivateData == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Done;
+ }
+
+ //
+ // Initialize Sata Private Data
+ //
+ SataPrivateData->Signature = SATA_CONTROLLER_SIGNATURE;
+ SataPrivateData->PciIo = PciIo;
+ SataPrivateData->IdeInit.GetChannelInfo = IdeInitGetChannelInfo;
+ SataPrivateData->IdeInit.NotifyPhase = IdeInitNotifyPhase;
+ SataPrivateData->IdeInit.SubmitData = IdeInitSubmitData;
+ SataPrivateData->IdeInit.DisqualifyMode = IdeInitDisqualifyMode;
+ SataPrivateData->IdeInit.CalculateMode = IdeInitCalculateMode;
+ SataPrivateData->IdeInit.SetTiming = IdeInitSetTiming;
+ SataPrivateData->IdeInit.EnumAll = SATA_ENUMER_ALL;
+
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_CLASSCODE_OFFSET,
+ sizeof (PciData.Hdr.ClassCode),
+ PciData.Hdr.ClassCode
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (IS_PCI_IDE (&PciData)) {
+ SataPrivateData->IdeInit.ChannelCount = IDE_MAX_CHANNEL;
+ SataPrivateData->DeviceCount = IDE_MAX_DEVICES;
+ } else if (IS_PCI_SATADPA (&PciData)) {
+ //
+ // Read Host Capability Register(CAP) to get Number of Ports(NPS) and Supports Port Multiplier(SPM)
+ // NPS is 0's based value indicating the maximum number of ports supported by the HBA silicon.
+ // A maximum of 32 ports can be supported. A value of '0h', indicating one port, is the minimum requirement.
+ //
+ Data32 = AhciReadReg (PciIo, R_AHCI_CAP);
+ SataPrivateData->IdeInit.ChannelCount = (UINT8) ((Data32 & B_AHCI_CAP_NPS) + 1);
+ SataPrivateData->DeviceCount = AHCI_MAX_DEVICES;
+ if ((Data32 & B_AHCI_CAP_SPM) == B_AHCI_CAP_SPM) {
+ SataPrivateData->DeviceCount = AHCI_MULTI_MAX_DEVICES;
+ }
+ }
+
+ ChannelDeviceCount = (UINTN) (SataPrivateData->IdeInit.ChannelCount) * (UINTN) (SataPrivateData->DeviceCount);
+ DEBUG ((EFI_D_INFO, "ChannelDeviceCount %d\n", ChannelDeviceCount));
+ SataPrivateData->DisqulifiedModes = AllocateZeroPool ((sizeof (EFI_ATA_COLLECTIVE_MODE)) * ChannelDeviceCount);
+ if (SataPrivateData->DisqulifiedModes == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Done;
+ }
+
+ SataPrivateData->IdentifyData = AllocateZeroPool ((sizeof (EFI_IDENTIFY_DATA)) * ChannelDeviceCount);
+ if (SataPrivateData->IdentifyData == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Done;
+ }
+
+ SataPrivateData->IdentifyValid = AllocateZeroPool ((sizeof (BOOLEAN)) * ChannelDeviceCount);
+ if (SataPrivateData->IdentifyValid == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto Done;
+ }
+
+ //
+ // Install IDE Controller Init Protocol to this instance
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ &(SataPrivateData->IdeInit),
+ NULL
+ );
+
+Done:
+ if (EFI_ERROR (Status)) {
+
+ gBS->CloseProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+ if (SataPrivateData != NULL) {
+ if (SataPrivateData->DisqulifiedModes != NULL) {
+ FreePool (SataPrivateData->DisqulifiedModes);
+ }
+ if (SataPrivateData->IdentifyData != NULL) {
+ FreePool (SataPrivateData->IdentifyData);
+ }
+ if (SataPrivateData->IdentifyValid != NULL) {
+ FreePool (SataPrivateData->IdentifyValid);
+ }
+ FreePool (SataPrivateData);
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "SataControllerStart END status = %r\n", Status));
+
+ return Status;
+}
+
+/**
+ Stop this driver on ControllerHandle.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to stop driver on.
+ @param NumberOfChildren Not used.
+ @param ChildHandleBuffer Not used.
+
+ @retval EFI_SUCCESS This driver is removed from this device.
+ @retval other Some error occurs when removing this driver from this device.
+
+**/
+EFI_STATUS
+EFIAPI
+SataControllerStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ )
+{
+ EFI_STATUS Status;
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
+ EFI_SATA_CONTROLLER_PRIVATE_DATA *SataPrivateData;
+
+DEBUG ((EFI_D_INFO, "SataControllerStop()\n"));
+ //
+ // Open the produced protocol
+ //
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ (VOID **) &IdeInit,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ SataPrivateData = SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS (IdeInit);
+ ASSERT (SataPrivateData != NULL);
+
+ //
+ // Uninstall the IDE Controller Init Protocol from this instance
+ //
+ Status = gBS->UninstallMultipleProtocolInterfaces (
+ Controller,
+ &gEfiIdeControllerInitProtocolGuid,
+ &(SataPrivateData->IdeInit),
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (SataPrivateData != NULL) {
+ if (SataPrivateData->DisqulifiedModes != NULL) {
+ FreePool (SataPrivateData->DisqulifiedModes);
+ }
+ if (SataPrivateData->IdentifyData != NULL) {
+ FreePool (SataPrivateData->IdentifyData);
+ }
+ if (SataPrivateData->IdentifyValid != NULL) {
+ FreePool (SataPrivateData->IdentifyValid);
+ }
+ FreePool (SataPrivateData);
+ }
+
+ //
+ // Close protocols opened by Sata Controller driver
+ //
+ return gBS->CloseProtocol (
+ Controller,
+ &gEfiPciIoProtocolGuid,
+ This->DriverBindingHandle,
+ Controller
+ );
+}
+
+//
+// Interface functions of IDE_CONTROLLER_INIT protocol
+//
+/**
+ Returns the information about the specified IDE channel.
+
+ This function can be used to obtain information about a particular IDE channel.
+ The driver entity uses this information during the enumeration process.
+
+ If Enabled is set to FALSE, the driver entity will not scan the channel. Note
+ that it will not prevent an operating system driver from scanning the channel.
+
+ For most of today's controllers, MaxDevices will either be 1 or 2. For SATA
+ controllers, this value will always be 1. SATA configurations can contain SATA
+ port multipliers. SATA port multipliers behave like SATA bridges and can support
+ up to 16 devices on the other side. If a SATA port out of the IDE controller
+ is connected to a port multiplier, MaxDevices will be set to the number of SATA
+ devices that the port multiplier supports. Because today's port multipliers
+ support up to fifteen SATA devices, this number can be as large as fifteen. The IDE
+ bus driver is required to scan for the presence of port multipliers behind an SATA
+ controller and enumerate up to MaxDevices number of devices behind the port
+ multiplier.
+
+ In this context, the devices behind a port multiplier constitute a channel.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[out] Enabled TRUE if this channel is enabled. Disabled channels
+ are not scanned to see if any devices are present.
+ @param[out] MaxDevices The maximum number of IDE devices that the bus driver
+ can expect on this channel. For the ATA/ATAPI
+ specification, version 6, this number will either be
+ one or two. For Serial ATA (SATA) configurations with a
+ port multiplier, this number can be as large as fifteen.
+
+ @retval EFI_SUCCESS Information was returned without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitGetChannelInfo (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ OUT BOOLEAN *Enabled,
+ OUT UINT8 *MaxDevices
+ )
+{
+ EFI_SATA_CONTROLLER_PRIVATE_DATA *SataPrivateData;
+ SataPrivateData = SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS (This);
+ ASSERT (SataPrivateData != NULL);
+
+DEBUG ((EFI_D_INFO, "IdeInitGetChannelInfo()\n"));
+ if (Channel < This->ChannelCount) {
+ *Enabled = TRUE;
+ *MaxDevices = SataPrivateData->DeviceCount;
+ return EFI_SUCCESS;
+ }
+
+ *Enabled = FALSE;
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ The notifications from the driver entity that it is about to enter a certain
+ phase of the IDE channel enumeration process.
+
+ This function can be used to notify the IDE controller driver to perform
+ specific actions, including any chipset-specific initialization, so that the
+ chipset is ready to enter the next phase. Seven notification points are defined
+ at this time.
+
+ More synchronization points may be added as required in the future.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Phase The phase during enumeration.
+ @param[in] Channel Zero-based channel number.
+
+ @retval EFI_SUCCESS The notification was accepted without any errors.
+ @retval EFI_UNSUPPORTED Phase is not supported.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_NOT_READY This phase cannot be entered at this time; for
+ example, an attempt was made to enter a Phase
+ without having entered one or more previous
+ Phase.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitNotifyPhase (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
+ IN UINT8 Channel
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Submits the device information to the IDE controller driver.
+
+ This function is used by the driver entity to pass detailed information about
+ a particular device to the IDE controller driver. The driver entity obtains
+ this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData
+ is the pointer to the response data buffer. The IdentifyData buffer is owned
+ by the driver entity, and the IDE controller driver must make a local copy
+ of the entire buffer or parts of the buffer as needed. The original IdentifyData
+ buffer pointer may not be valid when
+
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point.
+
+ The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to
+ compute the optimum mode for the device. These fields are not limited to the
+ timing information. For example, an implementation of the IDE controller driver
+ may examine the vendor and type/mode field to match known bad drives.
+
+ The driver entity may submit drive information in any order, as long as it
+ submits information for all the devices belonging to the enumeration group
+ before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device
+ in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ should be called with IdentifyData set to NULL. The IDE controller driver may
+ not have any other mechanism to know whether a device is present or not. Therefore,
+ setting IdentifyData to NULL does not constitute an error condition.
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a
+ given (Channel, Device) pair.
+
+ @param[in] This A pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[in] Device Zero-based device number on the Channel.
+ @param[in] IdentifyData The device's response to the ATA IDENTIFY_DEVICE command.
+
+ @retval EFI_SUCCESS The information was accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitSubmitData (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_IDENTIFY_DATA *IdentifyData
+ )
+{
+ EFI_SATA_CONTROLLER_PRIVATE_DATA *SataPrivateData;
+ SataPrivateData = SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS (This);
+ ASSERT (SataPrivateData != NULL);
+
+DEBUG ((EFI_D_INFO, "IdeInitSubmitData()\n"));
+ if ((Channel >= This->ChannelCount) || (Device >= SataPrivateData->DeviceCount)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Make a local copy of device's IdentifyData and mark the valid flag
+ //
+ if (IdentifyData != NULL) {
+ CopyMem (
+ &(SataPrivateData->IdentifyData[Channel * Device]),
+ IdentifyData,
+ sizeof (EFI_IDENTIFY_DATA)
+ );
+
+ SataPrivateData->IdentifyValid[Channel * Device] = TRUE;
+ } else {
+ SataPrivateData->IdentifyValid[Channel * Device] = FALSE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disqualifies specific modes for an IDE device.
+
+ This function allows the driver entity or other drivers (such as platform
+ drivers) to reject certain timing modes and request the IDE controller driver
+ to recalculate modes. This function allows the driver entity and the IDE
+ controller driver to negotiate the timings on a per-device basis. This function
+ is useful in the case of drives that lie about their capabilities. An example
+ is when the IDE device fails to accept the timing modes that are calculated
+ by the IDE controller driver based on the response to the Identify Drive command.
+
+ If the driver entity does not want to limit the ATA timing modes and leave that
+ decision to the IDE controller driver, it can either not call this function for
+ the given device or call this function and set the Valid flag to FALSE for all
+ modes that are listed in EFI_ATA_COLLECTIVE_MODE.
+
+ The driver entity may disqualify modes for a device in any order and any number
+ of times.
+
+ This function can be called multiple times to invalidate multiple modes of the
+ same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI
+ specification for more information on PIO modes.
+
+ For Serial ATA (SATA) controllers, this member function can be used to disqualify
+ a higher transfer rate mode on a given channel. For example, a platform driver
+ may inform the IDE controller driver to not use second-generation (Gen2) speeds
+ for a certain SATA drive.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel The zero-based channel number.
+ @param[in] Device The zero-based device number on the Channel.
+ @param[in] BadModes The modes that the device does not support and that
+ should be disqualified.
+
+ @retval EFI_SUCCESS The modes were accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_INVALID_PARAMETER IdentifyData is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitDisqualifyMode (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *BadModes
+ )
+{
+ EFI_SATA_CONTROLLER_PRIVATE_DATA *SataPrivateData;
+ SataPrivateData = SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS (This);
+ ASSERT (SataPrivateData != NULL);
+
+DEBUG ((EFI_D_INFO, "IdeInitDisqualifyMode()\n"));
+
+ if ((Channel >= This->ChannelCount) || (BadModes == NULL) || (Device >= SataPrivateData->DeviceCount)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Record the disqualified modes per channel per device. From ATA/ATAPI spec,
+ // if a mode is not supported, the modes higher than it is also not supported.
+ //
+ CopyMem (
+ &(SataPrivateData->DisqulifiedModes[Channel * Device]),
+ BadModes,
+ sizeof (EFI_ATA_COLLECTIVE_MODE)
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the information about the optimum modes for the specified IDE device.
+
+ This function is used by the driver entity to obtain the optimum ATA modes for
+ a specific device. The IDE controller driver takes into account the following
+ while calculating the mode:
+ - The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ - The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()
+
+ The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ for all the devices that belong to an enumeration group before calling
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group.
+
+ The IDE controller driver will use controller- and possibly platform-specific
+ algorithms to arrive at SupportedModes. The IDE controller may base its
+ decision on user preferences and other considerations as well. This function
+ may be called multiple times because the driver entity may renegotiate the mode
+ with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode().
+
+ The driver entity may collect timing information for various devices in any
+ order. The driver entity is responsible for making sure that all the dependencies
+ are satisfied. For example, the SupportedModes information for device A that
+ was previously returned may become stale after a call to
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B.
+
+ The buffer SupportedModes is allocated by the callee because the caller does
+ not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE
+ is defined in a way that allows for future extensibility and can be of variable
+ length. This memory pool should be deallocated by the caller when it is no
+ longer necessary.
+
+ The IDE controller driver for a Serial ATA (SATA) controller can use this
+ member function to force a lower speed (first-generation [Gen1] speeds on a
+ second-generation [Gen2]-capable hardware). The IDE controller driver can
+ also allow the driver entity to stay with the speed that has been negotiated
+ by the physical layer.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel A zero-based channel number.
+ @param[in] Device A zero-based device number on the Channel.
+ @param[out] SupportedModes The optimum modes for the device.
+
+ @retval EFI_SUCCESS SupportedModes was returned.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_INVALID_PARAMETER SupportedModes is NULL.
+ @retval EFI_NOT_READY Modes cannot be calculated due to a lack of
+ data. This error may happen if
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData()
+ were not called for at least one drive in the
+ same enumeration group.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitCalculateMode (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
+ )
+{
+ EFI_SATA_CONTROLLER_PRIVATE_DATA *SataPrivateData;
+ EFI_IDENTIFY_DATA *IdentifyData;
+ BOOLEAN IdentifyValid;
+ EFI_ATA_COLLECTIVE_MODE *DisqulifiedModes;
+ UINT16 SelectedMode;
+ EFI_STATUS Status;
+
+DEBUG ((EFI_D_INFO, "IdeInitCalculateMode()\n"));
+ SataPrivateData = SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS (This);
+ ASSERT (SataPrivateData != NULL);
+
+ if ((Channel >= This->ChannelCount) || (SupportedModes == NULL) || (Device >= SataPrivateData->DeviceCount)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *SupportedModes = AllocateZeroPool (sizeof (EFI_ATA_COLLECTIVE_MODE));
+ if (*SupportedModes == NULL) {
+ ASSERT (*SupportedModes != NULL);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ IdentifyData = &(SataPrivateData->IdentifyData[Channel * Device]);
+ IdentifyValid = SataPrivateData->IdentifyValid[Channel * Device];
+ DisqulifiedModes = &(SataPrivateData->DisqulifiedModes[Channel * Device]);
+
+ //
+ // Make sure we've got the valid identify data of the device from SubmitData()
+ //
+ if (!IdentifyValid) {
+ FreePool (*SupportedModes);
+ return EFI_NOT_READY;
+ }
+
+ Status = CalculateBestPioMode (
+ IdentifyData,
+ (DisqulifiedModes->PioMode.Valid ? ((UINT16 *) &(DisqulifiedModes->PioMode.Mode)) : NULL),
+ &SelectedMode
+ );
+ if (!EFI_ERROR (Status)) {
+ (*SupportedModes)->PioMode.Valid = TRUE;
+ (*SupportedModes)->PioMode.Mode = SelectedMode;
+
+ } else {
+ (*SupportedModes)->PioMode.Valid = FALSE;
+ }
+ DEBUG ((EFI_D_INFO, "IdeInitCalculateMode: PioMode = %x\n", (*SupportedModes)->PioMode.Mode));
+
+ Status = CalculateBestUdmaMode (
+ IdentifyData,
+ (DisqulifiedModes->UdmaMode.Valid ? ((UINT16 *) &(DisqulifiedModes->UdmaMode.Mode)) : NULL),
+ &SelectedMode
+ );
+
+ if (!EFI_ERROR (Status)) {
+ (*SupportedModes)->UdmaMode.Valid = TRUE;
+ (*SupportedModes)->UdmaMode.Mode = SelectedMode;
+
+ } else {
+ (*SupportedModes)->UdmaMode.Valid = FALSE;
+ }
+ DEBUG ((EFI_D_INFO, "IdeInitCalculateMode: UdmaMode = %x\n", (*SupportedModes)->UdmaMode.Mode));
+
+ //
+ // The modes other than PIO and UDMA are not supported
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ Commands the IDE controller driver to program the IDE controller hardware
+ so that the specified device can operate at the specified mode.
+
+ This function is used by the driver entity to instruct the IDE controller
+ driver to program the IDE controller hardware to the specified modes. This
+ function can be called only once for a particular device. For a Serial ATA
+ (SATA) Advanced Host Controller Interface (AHCI) controller, no controller-
+ specific programming may be required.
+
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[in] Device Zero-based device number on the Channel.
+ @param[in] Modes The modes to set.
+
+ @retval EFI_SUCCESS The command was accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_NOT_READY Modes cannot be set at this time due to lack of data.
+ @retval EFI_DEVICE_ERROR Modes cannot be set due to hardware failure.
+ The driver entity should not use this device.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitSetTiming (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *Modes
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataController.h b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataController.h new file mode 100644 index 0000000..cb9b84b --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataController.h @@ -0,0 +1,555 @@ +/** @file
+ Header file for Sata Controller driver.
+
+ Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SATA_CONTROLLER_H_
+#define _SATA_CONTROLLER_H_
+
+#include <Uefi.h>
+#include <Protocol/ComponentName.h>
+#include <Protocol/DriverBinding.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/IdeControllerInit.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Pci.h>
+
+//
+// Global Variables definitions
+//
+extern EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2;
+
+#define AHCI_BAR_INDEX 0x05
+#define R_AHCI_CAP 0x0
+#define B_AHCI_CAP_NPS (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) // Number of Ports
+#define B_AHCI_CAP_SPM BIT17 // Supports Port Multiplier
+
+///
+/// AHCI each channel can have up to 1 device
+///
+#define AHCI_MAX_DEVICES 0x01
+
+///
+/// AHCI each channel can have 15 devices in the presence of a multiplier
+///
+#define AHCI_MULTI_MAX_DEVICES 0x0F
+
+///
+/// IDE supports 2 channel max
+///
+#define IDE_MAX_CHANNEL 0x02
+
+///
+/// IDE supports 2 devices max
+///
+#define IDE_MAX_DEVICES 0x02
+
+#define SATA_ENUMER_ALL FALSE
+
+//
+// Sata Controller driver private data structure
+//
+
+#define SATA_CONTROLLER_SIGNATURE SIGNATURE_32('S','A','T','A')
+
+typedef struct _EFI_SATA_CONTROLLER_PRIVATE_DATA {
+ //
+ // Standard signature used to identify Sata Controller private data
+ //
+ UINT32 Signature;
+
+ //
+ // Protocol instance of IDE_CONTROLLER_INIT produced by this driver
+ //
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL IdeInit;
+
+ //
+ // Copy of protocol pointers used by this driver
+ //
+ EFI_PCI_IO_PROTOCOL *PciIo;
+
+ //
+ // The number of devices that are supported by this channel
+ //
+ UINT8 DeviceCount;
+
+ //
+ // The highest disqulified mode for each attached device,
+ // From ATA/ATAPI spec, if a mode is not supported,
+ // the modes higher than it is also not supported
+ //
+ EFI_ATA_COLLECTIVE_MODE *DisqulifiedModes;
+
+ //
+ // A copy of EFI_IDENTIFY_DATA data for each attached SATA device and its flag
+ //
+ EFI_IDENTIFY_DATA *IdentifyData;
+ BOOLEAN *IdentifyValid;
+} EFI_SATA_CONTROLLER_PRIVATE_DATA;
+
+#define SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_SATA_CONTROLLER_PRIVATE_DATA, IdeInit, SATA_CONTROLLER_SIGNATURE)
+
+/**
+ Initialize the Sata controller hardware.
+
+ @retval EFI_SUCCESS This driver is removed from this device.
+ @retval other Some error occurs when removing this driver from this device.
+**/
+EFI_STATUS
+InitializeSataController (
+ VOID
+ );
+
+//
+// Driver binding functions declaration
+//
+/**
+ Supported function of Driver Binding protocol for this driver.
+ Test to see if this driver supports ControllerHandle.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to test.
+ @param RemainingDevicePath A pointer to the device path. Should be ignored by
+ device driver.
+
+ @retval EFI_SUCCESS This driver supports this device.
+ @retval EFI_ALREADY_STARTED This driver is already running on this device.
+ @retval other This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+SataControllerSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+;
+
+/**
+ This routine is called right after the .Supported() called and
+ Start this driver on ControllerHandle.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to bind driver to.
+ @param RemainingDevicePath A pointer to the device path. Should be ignored by
+ device driver.
+
+ @retval EFI_SUCCESS This driver is added to this device.
+ @retval EFI_ALREADY_STARTED This driver is already running on this device.
+ @retval other Some error occurs when binding this driver to this device.
+
+**/
+EFI_STATUS
+EFIAPI
+SataControllerStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+;
+
+/**
+ Stop this driver on ControllerHandle.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to stop driver on.
+ @param NumberOfChildren Not used.
+ @param ChildHandleBuffer Not used.
+
+ @retval EFI_SUCCESS This driver is removed from this device.
+ @retval other Some error occurs when removing this driver from this device.
+
+**/
+EFI_STATUS
+EFIAPI
+SataControllerStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ )
+;
+
+//
+// IDE controller init functions declaration
+//
+/**
+ Returns the information about the specified IDE channel.
+
+ This function can be used to obtain information about a particular IDE channel.
+ The driver entity uses this information during the enumeration process.
+
+ If Enabled is set to FALSE, the driver entity will not scan the channel. Note
+ that it will not prevent an operating system driver from scanning the channel.
+
+ For most of today's controllers, MaxDevices will either be 1 or 2. For SATA
+ controllers, this value will always be 1. SATA configurations can contain SATA
+ port multipliers. SATA port multipliers behave like SATA bridges and can support
+ up to 16 devices on the other side. If a SATA port out of the IDE controller
+ is connected to a port multiplier, MaxDevices will be set to the number of SATA
+ devices that the port multiplier supports. Because today's port multipliers
+ support up to fifteen SATA devices, this number can be as large as fifteen. The IDE
+ bus driver is required to scan for the presence of port multipliers behind an SATA
+ controller and enumerate up to MaxDevices number of devices behind the port
+ multiplier.
+
+ In this context, the devices behind a port multiplier constitute a channel.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[out] Enabled TRUE if this channel is enabled. Disabled channels
+ are not scanned to see if any devices are present.
+ @param[out] MaxDevices The maximum number of IDE devices that the bus driver
+ can expect on this channel. For the ATA/ATAPI
+ specification, version 6, this number will either be
+ one or two. For Serial ATA (SATA) configurations with a
+ port multiplier, this number can be as large as fifteen.
+
+ @retval EFI_SUCCESS Information was returned without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitGetChannelInfo (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ OUT BOOLEAN *Enabled,
+ OUT UINT8 *MaxDevices
+ )
+;
+
+/**
+ The notifications from the driver entity that it is about to enter a certain
+ phase of the IDE channel enumeration process.
+
+ This function can be used to notify the IDE controller driver to perform
+ specific actions, including any chipset-specific initialization, so that the
+ chipset is ready to enter the next phase. Seven notification points are defined
+ at this time.
+
+ More synchronization points may be added as required in the future.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Phase The phase during enumeration.
+ @param[in] Channel Zero-based channel number.
+
+ @retval EFI_SUCCESS The notification was accepted without any errors.
+ @retval EFI_UNSUPPORTED Phase is not supported.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_NOT_READY This phase cannot be entered at this time; for
+ example, an attempt was made to enter a Phase
+ without having entered one or more previous
+ Phase.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitNotifyPhase (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
+ IN UINT8 Channel
+ )
+;
+
+/**
+ Submits the device information to the IDE controller driver.
+
+ This function is used by the driver entity to pass detailed information about
+ a particular device to the IDE controller driver. The driver entity obtains
+ this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData
+ is the pointer to the response data buffer. The IdentifyData buffer is owned
+ by the driver entity, and the IDE controller driver must make a local copy
+ of the entire buffer or parts of the buffer as needed. The original IdentifyData
+ buffer pointer may not be valid when
+
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or
+ - EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point.
+
+ The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to
+ compute the optimum mode for the device. These fields are not limited to the
+ timing information. For example, an implementation of the IDE controller driver
+ may examine the vendor and type/mode field to match known bad drives.
+
+ The driver entity may submit drive information in any order, as long as it
+ submits information for all the devices belonging to the enumeration group
+ before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device
+ in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ should be called with IdentifyData set to NULL. The IDE controller driver may
+ not have any other mechanism to know whether a device is present or not. Therefore,
+ setting IdentifyData to NULL does not constitute an error condition.
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a
+ given (Channel, Device) pair.
+
+ @param[in] This A pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[in] Device Zero-based device number on the Channel.
+ @param[in] IdentifyData The device's response to the ATA IDENTIFY_DEVICE command.
+
+ @retval EFI_SUCCESS The information was accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitSubmitData (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_IDENTIFY_DATA *IdentifyData
+ )
+;
+
+/**
+ Disqualifies specific modes for an IDE device.
+
+ This function allows the driver entity or other drivers (such as platform
+ drivers) to reject certain timing modes and request the IDE controller driver
+ to recalculate modes. This function allows the driver entity and the IDE
+ controller driver to negotiate the timings on a per-device basis. This function
+ is useful in the case of drives that lie about their capabilities. An example
+ is when the IDE device fails to accept the timing modes that are calculated
+ by the IDE controller driver based on the response to the Identify Drive command.
+
+ If the driver entity does not want to limit the ATA timing modes and leave that
+ decision to the IDE controller driver, it can either not call this function for
+ the given device or call this function and set the Valid flag to FALSE for all
+ modes that are listed in EFI_ATA_COLLECTIVE_MODE.
+
+ The driver entity may disqualify modes for a device in any order and any number
+ of times.
+
+ This function can be called multiple times to invalidate multiple modes of the
+ same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI
+ specification for more information on PIO modes.
+
+ For Serial ATA (SATA) controllers, this member function can be used to disqualify
+ a higher transfer rate mode on a given channel. For example, a platform driver
+ may inform the IDE controller driver to not use second-generation (Gen2) speeds
+ for a certain SATA drive.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel The zero-based channel number.
+ @param[in] Device The zero-based device number on the Channel.
+ @param[in] BadModes The modes that the device does not support and that
+ should be disqualified.
+
+ @retval EFI_SUCCESS The modes were accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_INVALID_PARAMETER IdentifyData is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitDisqualifyMode (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *BadModes
+ )
+;
+
+/**
+ Returns the information about the optimum modes for the specified IDE device.
+
+ This function is used by the driver entity to obtain the optimum ATA modes for
+ a specific device. The IDE controller driver takes into account the following
+ while calculating the mode:
+ - The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ - The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()
+
+ The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ for all the devices that belong to an enumeration group before calling
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group.
+
+ The IDE controller driver will use controller- and possibly platform-specific
+ algorithms to arrive at SupportedModes. The IDE controller may base its
+ decision on user preferences and other considerations as well. This function
+ may be called multiple times because the driver entity may renegotiate the mode
+ with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode().
+
+ The driver entity may collect timing information for various devices in any
+ order. The driver entity is responsible for making sure that all the dependencies
+ are satisfied. For example, the SupportedModes information for device A that
+ was previously returned may become stale after a call to
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B.
+
+ The buffer SupportedModes is allocated by the callee because the caller does
+ not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE
+ is defined in a way that allows for future extensibility and can be of variable
+ length. This memory pool should be deallocated by the caller when it is no
+ longer necessary.
+
+ The IDE controller driver for a Serial ATA (SATA) controller can use this
+ member function to force a lower speed (first-generation [Gen1] speeds on a
+ second-generation [Gen2]-capable hardware). The IDE controller driver can
+ also allow the driver entity to stay with the speed that has been negotiated
+ by the physical layer.
+
+ @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel A zero-based channel number.
+ @param[in] Device A zero-based device number on the Channel.
+ @param[out] SupportedModes The optimum modes for the device.
+
+ @retval EFI_SUCCESS SupportedModes was returned.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_INVALID_PARAMETER SupportedModes is NULL.
+ @retval EFI_NOT_READY Modes cannot be calculated due to a lack of
+ data. This error may happen if
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+ and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData()
+ were not called for at least one drive in the
+ same enumeration group.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitCalculateMode (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
+ )
+;
+
+/**
+ Commands the IDE controller driver to program the IDE controller hardware
+ so that the specified device can operate at the specified mode.
+
+ This function is used by the driver entity to instruct the IDE controller
+ driver to program the IDE controller hardware to the specified modes. This
+ function can be called only once for a particular device. For a Serial ATA
+ (SATA) Advanced Host Controller Interface (AHCI) controller, no controller-
+ specific programming may be required.
+
+ @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
+ @param[in] Channel Zero-based channel number.
+ @param[in] Device Zero-based device number on the Channel.
+ @param[in] Modes The modes to set.
+
+ @retval EFI_SUCCESS The command was accepted without any errors.
+ @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
+ @retval EFI_INVALID_PARAMETER Device is invalid.
+ @retval EFI_NOT_READY Modes cannot be set at this time due to lack of data.
+ @retval EFI_DEVICE_ERROR Modes cannot be set due to hardware failure.
+ The driver entity should not use this device.
+
+**/
+EFI_STATUS
+EFIAPI
+IdeInitSetTiming (
+ IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
+ IN UINT8 Channel,
+ IN UINT8 Device,
+ IN EFI_ATA_COLLECTIVE_MODE *Modes
+ )
+;
+
+//
+// Forward reference declaration
+//
+/**
+ Retrieves a Unicode string that is the user readable name of the UEFI Driver.
+
+ @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param Language A pointer to a three character ISO 639-2 language identifier.
+ This is the language of the driver name that that the caller
+ is requesting, and it must match one of the languages specified
+ in SupportedLanguages. The number of languages supported by a
+ driver is up to the driver writer.
+ @param DriverName A pointer to the Unicode string to return. This Unicode string
+ is the name of the driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by This
+ and the language specified by Language was returned
+ in DriverName.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+**/
+EFI_STATUS
+EFIAPI
+SataControllerComponentNameGetDriverName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ )
+;
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by an UEFI Driver.
+
+ @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+ @param ControllerHandle The handle of a controller that the driver specified by
+ This is managing. This handle specifies the controller
+ whose name is to be returned.
+ @param OPTIONAL ChildHandle The handle of the child controller to retrieve the name
+ of. This is an optional parameter that may be NULL. It
+ will be NULL for device drivers. It will also be NULL
+ for a bus drivers that wish to retrieve the name of the
+ bus controller. It will not be NULL for a bus driver
+ that wishes to retrieve the name of a child controller.
+ @param Language A pointer to a three character ISO 639-2 language
+ identifier. This is the language of the controller name
+ that that the caller is requesting, and it must match one
+ of the languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up to the
+ driver writer.
+ @param ControllerName A pointer to the Unicode string to return. This Unicode
+ string is the name of the controller specified by
+ ControllerHandle and ChildHandle in the language
+ specified by Language from the point of view of the
+ driver specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in the
+ language specified by Language for the driver
+ specified by This was returned in DriverName.
+ @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+ @retval EFI_UNSUPPORTED The driver specified by This does not support the
+ language specified by Language.
+**/
+EFI_STATUS
+EFIAPI
+SataControllerComponentNameGetControllerName (
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ )
+;
+
+#endif
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataControllerDxe.inf b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataControllerDxe.inf new file mode 100644 index 0000000..383ef90 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataControllerDxe.inf @@ -0,0 +1,85 @@ +## @file
+#
+# Component description file for the Sata Controller driver.
+#
+# Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SataController
+ FILE_GUID = 1c6d1ed1-22ec-4b16-9179-e5cdbf7ddf8d
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeSataControllerDriver
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ ComponentName.c
+ SataController.c
+ SataController.h
+ PciEmulation.c
+ PciEmulation.h
+ PciRootBridgeIo.c
+ SataRegisters.h
+ InitController.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ DebugLib
+ UefiLib
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ IoLib
+ AmdSataInit
+
+[Protocols]
+ gEfiPciIoProtocolGuid
+ gEfiIdeControllerInitProtocolGuid
+
+[Pcd]
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes
+
+ gAmdStyxTokenSpaceGuid.PcdSataCtrlAxiSlvPort
+ gAmdStyxTokenSpaceGuid.PcdSataPortCount
+ gAmdStyxTokenSpaceGuid.PcdSataPi
+ gAmdStyxTokenSpaceGuid.PcdSataPortMode
+ gAmdStyxTokenSpaceGuid.PcdSataSmpsSupport
+ gAmdStyxTokenSpaceGuid.PcdSataSssSupport
+ gAmdStyxTokenSpaceGuid.PcdSataPortCpd
+ gAmdStyxTokenSpaceGuid.PcdSataPortMpsp
+ gAmdStyxTokenSpaceGuid.PcdSata1CtrlAxiSlvPort
+ gAmdStyxTokenSpaceGuid.PcdSata1PortCount
+
+[Depex]
+ TRUE
+
diff --git a/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataRegisters.h b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataRegisters.h new file mode 100644 index 0000000..ff78f4a --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataRegisters.h @@ -0,0 +1,180 @@ +/** @file
+ Header file for AHCI mode of ATA host controller.
+
+ Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SATA_REGISTERS_H__
+#define __SATA_REGISTERS_H__
+
+#define EFI_AHCI_BAR_INDEX 0x05
+
+#define EFI_AHCI_CAPABILITY_OFFSET 0x0000
+#define EFI_AHCI_CAP_SSS BIT27
+#define EFI_AHCI_CAP_SMPS BIT28
+#define EFI_AHCI_CAP_S64A BIT31
+#define EFI_AHCI_GHC_OFFSET 0x0004
+#define EFI_AHCI_GHC_RESET BIT0
+#define EFI_AHCI_GHC_IE BIT1
+#define EFI_AHCI_GHC_ENABLE BIT31
+#define EFI_AHCI_IS_OFFSET 0x0008
+#define EFI_AHCI_PI_OFFSET 0x000C
+
+#define EFI_AHCI_MAX_PORTS 32
+
+//
+// Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
+//
+#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10
+//
+// Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
+//
+#define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
+//
+// Refer SATA1.0a spec, the bus reset time should be less than 1s.
+//
+#define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
+
+#define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
+#define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
+#define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
+#define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
+
+//
+// Each PRDT entry can point to a memory block up to 4M byte
+//
+#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
+
+#define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
+#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
+#define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
+#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
+#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
+#define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
+#define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
+#define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
+#define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
+#define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
+#define EFI_AHCI_FIS_BIST_LENGTH 12
+#define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
+#define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
+#define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
+#define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
+
+#define EFI_AHCI_D2H_FIS_OFFSET 0x40
+#define EFI_AHCI_DMA_FIS_OFFSET 0x00
+#define EFI_AHCI_PIO_FIS_OFFSET 0x20
+#define EFI_AHCI_SDB_FIS_OFFSET 0x58
+#define EFI_AHCI_FIS_TYPE_MASK 0xFF
+#define EFI_AHCI_U_FIS_OFFSET 0x60
+
+//
+// Port register
+//
+#define EFI_AHCI_PORT_START 0x0100
+#define EFI_AHCI_PORT_REG_WIDTH 0x0080
+#define EFI_AHCI_PORT_CLB 0x0000
+#define EFI_AHCI_PORT_CLBU 0x0004
+#define EFI_AHCI_PORT_FB 0x0008
+#define EFI_AHCI_PORT_FBU 0x000C
+#define EFI_AHCI_PORT_IS 0x0010
+#define EFI_AHCI_PORT_IS_DHRS BIT0
+#define EFI_AHCI_PORT_IS_PSS BIT1
+#define EFI_AHCI_PORT_IS_SSS BIT2
+#define EFI_AHCI_PORT_IS_SDBS BIT3
+#define EFI_AHCI_PORT_IS_UFS BIT4
+#define EFI_AHCI_PORT_IS_DPS BIT5
+#define EFI_AHCI_PORT_IS_PCS BIT6
+#define EFI_AHCI_PORT_IS_DIS BIT7
+#define EFI_AHCI_PORT_IS_PRCS BIT22
+#define EFI_AHCI_PORT_IS_IPMS BIT23
+#define EFI_AHCI_PORT_IS_OFS BIT24
+#define EFI_AHCI_PORT_IS_INFS BIT26
+#define EFI_AHCI_PORT_IS_IFS BIT27
+#define EFI_AHCI_PORT_IS_HBDS BIT28
+#define EFI_AHCI_PORT_IS_HBFS BIT29
+#define EFI_AHCI_PORT_IS_TFES BIT30
+#define EFI_AHCI_PORT_IS_CPDS BIT31
+#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
+#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
+
+#define EFI_AHCI_PORT_OFFSET(PortNum) \
+ (EFI_AHCI_PORT_START + ((PortNum) * EFI_AHCI_PORT_REG_WIDTH))
+
+#define EFI_AHCI_PORT_IE 0x0014
+#define EFI_AHCI_PORT_CMD 0x0018
+#define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
+#define EFI_AHCI_PORT_CMD_ST BIT0
+#define EFI_AHCI_PORT_CMD_SUD BIT1
+#define EFI_AHCI_PORT_CMD_POD BIT2
+#define EFI_AHCI_PORT_CMD_CLO BIT3
+#define EFI_AHCI_PORT_CMD_CR BIT15
+#define EFI_AHCI_PORT_CMD_FRE BIT4
+#define EFI_AHCI_PORT_CMD_FR BIT14
+#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
+#define EFI_AHCI_PORT_CMD_PMA BIT17
+#define EFI_AHCI_PORT_CMD_HPCP BIT18
+#define EFI_AHCI_PORT_CMD_MPSP BIT19
+#define EFI_AHCI_PORT_CMD_CPD BIT20
+#define EFI_AHCI_PORT_CMD_ESP BIT21
+#define EFI_AHCI_PORT_CMD_ATAPI BIT24
+#define EFI_AHCI_PORT_CMD_DLAE BIT25
+#define EFI_AHCI_PORT_CMD_ALPE BIT26
+#define EFI_AHCI_PORT_CMD_ASP BIT27
+#define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
+#define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
+#define EFI_AHCI_PORT_TFD 0x0020
+#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
+#define EFI_AHCI_PORT_TFD_BSY BIT7
+#define EFI_AHCI_PORT_TFD_DRQ BIT3
+#define EFI_AHCI_PORT_TFD_ERR BIT0
+#define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
+#define EFI_AHCI_PORT_SIG 0x0024
+#define EFI_AHCI_PORT_SSTS 0x0028
+#define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
+#define EFI_AHCI_PORT_SSTS_DET 0x0001
+#define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
+#define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
+#define EFI_AHCI_PORT_SCTL 0x002C
+#define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
+#define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
+#define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
+#define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
+#define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
+#define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
+#define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
+#define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
+#define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
+#define EFI_AHCI_PORT_SERR 0x0030
+#define EFI_AHCI_PORT_SERR_RDIE BIT0
+#define EFI_AHCI_PORT_SERR_RCE BIT1
+#define EFI_AHCI_PORT_SERR_TDIE BIT8
+#define EFI_AHCI_PORT_SERR_PCDIE BIT9
+#define EFI_AHCI_PORT_SERR_PE BIT10
+#define EFI_AHCI_PORT_SERR_IE BIT11
+#define EFI_AHCI_PORT_SERR_PRC BIT16
+#define EFI_AHCI_PORT_SERR_PIE BIT17
+#define EFI_AHCI_PORT_SERR_CW BIT18
+#define EFI_AHCI_PORT_SERR_BDE BIT19
+#define EFI_AHCI_PORT_SERR_DE BIT20
+#define EFI_AHCI_PORT_SERR_CRCE BIT21
+#define EFI_AHCI_PORT_SERR_HE BIT22
+#define EFI_AHCI_PORT_SERR_LSE BIT23
+#define EFI_AHCI_PORT_SERR_TSTE BIT24
+#define EFI_AHCI_PORT_SERR_UFT BIT25
+#define EFI_AHCI_PORT_SERR_EX BIT26
+#define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
+#define EFI_AHCI_PORT_SACT 0x0034
+#define EFI_AHCI_PORT_CI 0x0038
+#define EFI_AHCI_PORT_SNTF 0x003C
+
+#endif
diff --git a/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c new file mode 100644 index 0000000..be6cf9e --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.c @@ -0,0 +1,189 @@ +/** @file
+
+ This driver produces an EFI_RNG_PROTOCOL instance for the AMD Seattle CCP
+
+ Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+
+#include <Protocol/Rng.h>
+
+#define CCP_TRNG_OFFSET 0xc
+#define CCP_TNRG_RETRIES 5
+
+STATIC EFI_PHYSICAL_ADDRESS mCcpRngOutputReg;
+
+STATIC EFI_HANDLE mHandle;
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL
+ instance.
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of
+ RNGAlgorithmList.
+ On output with a return code of
+ EFI_SUCCESS, the size in bytes of the
+ data returned in RNGAlgorithmList. On
+ output with a return code of
+ EFI_BUFFER_TOO_SMALL, the size of
+ RNGAlgorithmList required to obtain the
+ list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled
+ by the driver with one EFI_RNG_ALGORITHM
+ element for each supported RNG algorithm.
+ The list must not change across multiple
+ calls to the same driver. The first
+ algorithm in the list is the default
+ algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned
+ successfully.
+ @retval EFI_UNSUPPORTED The services is not supported by this
+ driver.
+ @retval EFI_DEVICE_ERROR The list of algorithms could not be
+ retrieved due to a hardware or firmware
+ error.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are
+ incorrect.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small
+ to hold the result.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+StyxRngGetInfo (
+ IN EFI_RNG_PROTOCOL *This,
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ )
+{
+ if (This == NULL || RNGAlgorithmListSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) {
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ if (RNGAlgorithmList == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Produces and returns an RNG value using either the default or specified RNG
+ algorithm.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL
+ instance.
+ @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that
+ identifies the RNG algorithm to use. May
+ be NULL in which case the function will
+ use its default RNG algorithm.
+ @param[in] RNGValueLength The length in bytes of the memory buffer
+ pointed to by RNGValue. The driver shall
+ return exactly this numbers of bytes.
+ @param[out] RNGValue A caller-allocated memory buffer filled
+ by the driver with the resulting RNG
+ value.
+
+ @retval EFI_SUCCESS The RNG value was returned successfully.
+ @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm
+ is not supported by this driver.
+ @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due
+ to a hardware or firmware error.
+ @retval EFI_NOT_READY There is not enough random data available
+ to satisfy the length requested by
+ RNGValueLength.
+ @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is
+ zero.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+StyxRngGetRNG (
+ IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
+ IN UINTN RNGValueLength,
+ OUT UINT8 *RNGValue
+ )
+{
+ UINT32 Val;
+ UINT32 Retries;
+ UINT32 Loop;
+
+ if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // We only support the raw algorithm, so reject requests for anything else
+ //
+ if (RNGAlgorithm != NULL &&
+ !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ do {
+ Retries = CCP_TNRG_RETRIES;
+ do {
+ Val = MmioRead32 (mCcpRngOutputReg);
+ } while (!Val && Retries-- > 0);
+
+ if (!Val) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ for (Loop = 0; Loop < 4 && RNGValueLength > 0; Loop++, RNGValueLength--) {
+ *RNGValue++ = (UINT8)Val;
+ Val >>= 8;
+ }
+ } while (RNGValueLength > 0);
+
+ return EFI_SUCCESS;
+}
+
+STATIC EFI_RNG_PROTOCOL mStyxRngProtocol = {
+ StyxRngGetInfo,
+ StyxRngGetRNG
+};
+
+//
+// Entry point of this driver.
+//
+EFI_STATUS
+EFIAPI
+StyxRngEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ mCcpRngOutputReg = PcdGet64 (PcdCCPBase) + CCP_TRNG_OFFSET;
+
+ return SystemTable->BootServices->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiRngProtocolGuid, &mStyxRngProtocol,
+ NULL
+ );
+}
diff --git a/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf new file mode 100644 index 0000000..0f4fe7c --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf @@ -0,0 +1,47 @@ +## @file
+# This driver produces an EFI_RNG_PROTOCOL instance for the AMD Seattle CCP
+#
+# Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = StyxRngDxe
+ FILE_GUID = 58E26F0D-CBAC-4BBA-B70F-18221415665A
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = StyxRngEntryPoint
+
+[Sources]
+ StyxRngDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ IoLib
+ PcdLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gAmdModulePkgTokenSpaceGuid.PcdCCPBase
+
+[Protocols]
+ gEfiRngProtocolGuid ## PRODUCES
+
+[Guids]
+ gEfiRngAlgorithmRaw
+
+[Depex]
+ TRUE
diff --git a/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c new file mode 100644 index 0000000..03fd9e8 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.c @@ -0,0 +1,501 @@ +/** @file
+
+ FV block I/O protocol driver for Styx SPI flash exposed via ISCP
+
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <Protocol/AmdIscpDxeProtocol.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#define SPI_BASE (FixedPcdGet64 (PcdFdBaseAddress))
+#define BLOCK_SIZE (FixedPcdGet32 (PcdFlashNvStorageBlockSize))
+
+STATIC AMD_ISCP_DXE_PROTOCOL *mIscpDxeProtocol;
+STATIC EFI_HANDLE mStyxSpiFvHandle;
+
+STATIC EFI_EVENT mVirtualAddressChangeEvent;
+
+STATIC UINT64 mNvStorageBase;
+STATIC UINT64 mNvStorageLbaOffset;
+
+STATIC CONST UINT64 mNvStorageSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+
+/**
+ Notification function of EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE.
+
+ This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
+ It convers pointer to new virtual address.
+
+ @param Event Event whose notification function is being invoked.
+ @param Context Pointer to the notification function's context.
+
+**/
+STATIC
+VOID
+EFIAPI
+VariableClassAddressChangeEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID **)&mIscpDxeProtocol);
+ EfiConvertPointer (0x0, (VOID **)&mNvStorageBase);
+}
+
+/**
+ The GetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the
+ attributes and current settings are
+ returned. Type EFI_FVB_ATTRIBUTES_2 is defined
+ in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were
+ returned.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ *Attributes = EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP | // Writes may be enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY; // After erasure all bits take this value (i.e. '1')
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The SetAttributes() function sets configurable firmware volume
+ attributes and returns the new settings of the firmware volume.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to
+ EFI_FVB_ATTRIBUTES_2 that contains the
+ desired firmware volume settings. On
+ successful return, it contains the new
+ settings of the firmware volume. Type
+ EFI_FVB_ATTRIBUTES_2 is defined in
+ EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in
+ conflict with the capabilities
+ as declared in the firmware
+ volume header.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeSetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ return EFI_SUCCESS; // ignore for now
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_UNSUPPORTED The firmware volume is not memory mapped.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ *Address = (EFI_PHYSICAL_ADDRESS)mNvStorageBase;
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block for which to return the size.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ )
+{
+ *BlockSize = BLOCK_SIZE;
+ *NumberOfBlocks = mNvStorageSize / BLOCK_SIZE - (UINTN)Lba;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index
+ from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN. At entry, *NumBytes
+ contains the total size of the buffer. At
+ exit, *NumBytes contains the total number of
+ bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will
+ be used to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully,
+ and contents are in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA
+ boundary. On output, NumBytes
+ contains the total number of bytes
+ returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not
+ functioning correctly and could
+ not be read.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ )
+{
+ VOID *Base;
+
+ if (Offset + *NumBytes > BLOCK_SIZE) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ Base = (VOID *)mNvStorageBase + Lba * BLOCK_SIZE + Offset;
+
+ //
+ // Copy the data from the in-memory image
+ //
+ CopyMem (Buffer, Base, *NumBytes);
+
+ DEBUG_CODE_BEGIN ();
+ EFI_STATUS Status;
+
+ if (!EfiAtRuntime ()) {
+ Lba += mNvStorageLbaOffset;
+ Status = mIscpDxeProtocol->AmdExecuteLoadFvBlockDxe (mIscpDxeProtocol,
+ Lba * BLOCK_SIZE + Offset, Buffer, *NumBytes);
+ ASSERT_EFI_ERROR (Status);
+
+ ASSERT (CompareMem (Base, Buffer, *NumBytes) == 0);
+ }
+ DEBUG_CODE_END ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN. At entry, *NumBytes
+ contains the total size of the buffer. At
+ exit, *NumBytes contains the total number of
+ bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an
+ LBA boundary. On output, NumBytes
+ contains the total number of bytes
+ actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning
+ and could not be written.
+
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ VOID *Base;
+
+ if (Offset + *NumBytes > BLOCK_SIZE) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ Base = (VOID *)mNvStorageBase + Lba * BLOCK_SIZE + Offset;
+
+ Lba += mNvStorageLbaOffset;
+ Status = mIscpDxeProtocol->AmdExecuteUpdateFvBlockDxe (mIscpDxeProtocol,
+ Lba * BLOCK_SIZE + Offset, Buffer, *NumBytes);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Copy the data we just wrote to the in-memory copy of the
+ // firmware volume
+ //
+ CopyMem (Base, Buffer, *NumBytes);
+ }
+ return Status;
+}
+
+/**
+ Erases and initializes a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks to
+ erase.
+
+ The list is terminated with an
+ EFI_LBA_LIST_TERMINATOR. For example, the
+ following indicates that two ranges of blocks
+ (5-7 and 10-11) are to be erased: EraseBlocks
+ (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS The erase request successfully
+ completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the
+ WriteDisabled state.
+ @retval EFI_DEVICE_ERROR The block device is not functioning
+ correctly and could not be written.
+ The firmware device may have been
+ partially erased.
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed
+ in the variable argument list do
+ not exist in the firmware volume.
+
+**/
+STATIC
+EFI_STATUS
+StyxSpiFvDxeErase (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ )
+{
+ VA_LIST Args;
+ EFI_LBA Start;
+ UINTN Length;
+ EFI_STATUS Status;
+
+ VA_START (Args, This);
+
+ for (Start = VA_ARG (Args, EFI_LBA);
+ Start != EFI_LBA_LIST_TERMINATOR;
+ Start = VA_ARG (Args, EFI_LBA)) {
+ Start += mNvStorageLbaOffset;
+ Length = VA_ARG (Args, UINTN);
+ Status = mIscpDxeProtocol->AmdExecuteEraseFvBlockDxe (mIscpDxeProtocol,
+ (Start + mNvStorageLbaOffset) * BLOCK_SIZE,
+ Length * BLOCK_SIZE);
+ if (!EFI_ERROR (Status)) {
+ SetMem64 ((VOID *)mNvStorageBase + Start * BLOCK_SIZE,
+ Length * BLOCK_SIZE, ~0UL);
+ }
+ }
+
+ VA_END (Args);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mStyxSpiFvProtocol = {
+ StyxSpiFvDxeGetAttributes,
+ StyxSpiFvDxeSetAttributes,
+ StyxSpiFvDxeGetPhysicalAddress,
+ StyxSpiFvDxeGetBlockSize,
+ StyxSpiFvDxeRead,
+ StyxSpiFvDxeWrite,
+ StyxSpiFvDxeErase
+};
+
+EFI_STATUS
+EFIAPI
+StyxSpiFvDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ mNvStorageBase = PcdGet64 (PcdFlashNvStorageVariableBase64);
+ mNvStorageLbaOffset = (FixedPcdGet64 (PcdFlashNvStorageOriginalBase) -
+ SPI_BASE) / BLOCK_SIZE;
+
+ DEBUG ((EFI_D_INFO,
+ "%a: Using NV store FV in-memory copy at 0x%lx, LBA offset == 0x%lx\n",
+ __FUNCTION__, mNvStorageBase, mNvStorageLbaOffset));
+
+ Status = gBS->LocateProtocol (&gAmdIscpDxeProtocolGuid, NULL,
+ (VOID **)&mIscpDxeProtocol);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
+ VariableClassAddressChangeEvent, NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mVirtualAddressChangeEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return gBS->InstallMultipleProtocolInterfaces (&mStyxSpiFvHandle,
+ &gEfiFirmwareVolumeBlockProtocolGuid, &mStyxSpiFvProtocol,
+ NULL);
+}
diff --git a/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf new file mode 100644 index 0000000..2c1f243 --- /dev/null +++ b/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf @@ -0,0 +1,63 @@ +#/** @file
+#
+# Component description file for StyxSpiFvDxe module
+#
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = StyxSpiFvDxe
+ FILE_GUID = F549FC67-C4A6-4E92-B9BA-297E1F82A1A8
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = StyxSpiFvDxeInitialize
+
+[Sources]
+ StyxSpiFvDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ UefiLib
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeLib
+ DxeServicesTableLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageBlockSize
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+
+[Protocols]
+ gAmdIscpDxeProtocolGuid ## CONSUMES
+ gEfiFirmwareVolumeBlockProtocolGuid ## PRODUCES
+
+[Depex]
+ gAmdIscpDxeProtocolGuid
diff --git a/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c new file mode 100644 index 0000000..d8b70f5 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.c @@ -0,0 +1,77 @@ +/** @file
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <AmdStyxHelperLib.h>
+
+#include <PiDxe.h>
+#include <Library/HobLib.h>
+
+extern EFI_SYSTEM_TABLE *gST;
+
+#pragma pack(push, 1)
+typedef struct {
+ UINT32 MpId;
+ UINT32 PmuSpi;
+} PMU_INFO;
+
+PMU_INFO mPmuInfo[] = {
+ {0x000, 7},
+ {0x001, 8},
+ {0x100, 9},
+ {0x101, 10},
+ {0x200, 11},
+ {0x201, 12},
+ {0x300, 13},
+ {0x301, 14}
+};
+#pragma pack(pop)
+
+#define MAX_CPUS sizeof(mPmuInfo) / sizeof(PMU_INFO)
+
+EFI_STATUS
+AmdStyxGetPmuSpiFromMpId (
+ UINT32 MpId,
+ UINT32 *PmuSpi
+ )
+{
+ UINT32 i;
+
+ for (i = 0; i < MAX_CPUS; ++i) {
+ if (mPmuInfo[ i ].MpId == MpId) {
+ *PmuSpi = mPmuInfo[ i ].PmuSpi;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+ARM_CORE_INFO *
+AmdStyxGetArmCoreInfoTable (
+ OUT UINTN *NumEntries
+ )
+{
+ EFI_HOB_GUID_TYPE *Hob;
+
+ ASSERT (NumEntries != NULL);
+
+ Hob = GetFirstGuidHob (&gAmdStyxMpCoreInfoGuid);
+ if (Hob == NULL) {
+ return NULL;
+ }
+
+ *NumEntries = GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (ARM_CORE_INFO);
+
+ return GET_GUID_HOB_DATA (Hob);
+}
diff --git a/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf new file mode 100644 index 0000000..17681d9 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxHelperLib/AmdStyxHelperLib.inf @@ -0,0 +1,37 @@ +#/** @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxHelperLib
+ FILE_GUID = a2a9afbb-6776-4585-8a81-f82f98b4ea53
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = AmdStyxHelperLib
+
+[Sources.common]
+ AmdStyxHelperLib.c
+
+[LibraryClasses]
+ HobLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S new file mode 100644 index 0000000..0f9822a --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AArch64/Helper.S @@ -0,0 +1,107 @@ +#/**
+#
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.S
+#
+#**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
+
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)
+
+PrimaryCoreMpid: .word 0x0
+PrimaryCoreBoot: .word 0x0
+
+//VOID
+//ArmPlatformPeiBootAction (
+// VOID
+// );
+ASM_PFX(ArmPlatformPeiBootAction):
+ // Save the primary CPU MPID
+ ldr x1, =PrimaryCoreBoot
+ ldrh w0, [x1]
+ cmp wzr, w0
+ b.ne 1f
+ mrs x0, mpidr_el1
+ ldr x1, =PrimaryCoreMpid
+ str w0, [x1]
+ mov w0, 1
+ ldr x1, =PrimaryCoreBoot
+ str w0, [x1]
+1:
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ ldr x0, =PrimaryCoreMpid
+ ldrh w0, [x0]
+ ret
+
+# IN None
+# OUT x0 = number of cores present in the system
+ASM_PFX(ArmGetCpuCountPerCluster):
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, x0)
+ ldrh w0, [x0]
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)
+ ldrh w1, [x1]
+ and x0, x0, x1
+
+ ldr x1, =PrimaryCoreMpid
+ ldrh w1, [x1]
+
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #7
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf new file mode 100644 index 0000000..c6e42e4 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf @@ -0,0 +1,76 @@ +#/* @file
+#
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+#/**
+# Derived from:
+# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxLib
+ FILE_GUID = 256ee872-5a3e-4b6e-afd6-63c49ba3d7ba
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ ArmLib
+ HobLib
+ DebugLib
+
+[Sources.common]
+ Styx.c
+ StyxMem.c
+
+[Sources.AARCH64]
+ AArch64/Helper.S | GCC
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid ## CONSUMER
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
+
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize
+
+[Depex]
+ gAmdStyxPlatInitPpiGuid
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf new file mode 100644 index 0000000..fefd3ee --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf @@ -0,0 +1,67 @@ +#/* @file
+#
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+#/**
+# Derived from:
+# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxLibSec
+ FILE_GUID = 2228e985-60ae-406e-bdf0-410c6750c7d2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ ArmLib
+ HobLib
+ DebugLib
+
+[Sources.common]
+ Styx.c
+
+[Sources.AARCH64]
+ AArch64/Helper.S | GCC
+
+[Guids]
+ gAmdStyxMpCoreInfoGuid ## CONSUMER
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/Styx.c b/Platforms/AMD/Styx/Library/AmdStyxLib/Styx.c new file mode 100644 index 0000000..f17a960 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/Styx.c @@ -0,0 +1,164 @@ +/** @file
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Guid/ArmMpCoreInfo.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+
+
+extern EFI_GUID gAmdStyxMpCoreInfoGuid;
+
+
+UINTN
+ArmGetCpuCountPerCluster (
+ VOID
+ );
+
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ if (!ArmPlatformIsPrimaryCore (MpId)) {
+ return RETURN_SUCCESS;
+ }
+
+ // XXX Place holder XXX ...
+
+ return RETURN_SUCCESS;
+}
+
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+ // Nothing to do here
+}
+
+
+//
+// Return list of cores in the system
+//
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *ArmCoreCount,
+ OUT ARM_CORE_INFO **ArmCoreInfoTable
+ )
+{
+ EFI_PEI_HOB_POINTERS Hob;
+
+ if (ArmIsMpCore()) {
+ // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
+ for (Hob.Raw = GetHobList (); !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {
+ // Check for Correct HOB type
+ if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
+ // Check for correct GUID type
+ if (CompareGuid(&(Hob.Guid->Name), &gAmdStyxMpCoreInfoGuid)) {
+ *ArmCoreInfoTable = (ARM_CORE_INFO *) GET_GUID_HOB_DATA(Hob);
+ *ArmCoreCount = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);
+ return EFI_SUCCESS;
+ }
+ }
+ }
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ if (ArmIsMpCore()) {
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+ } else {
+ *PpiListSize = 0;
+ *PpiList = NULL;
+ }
+}
+
+
diff --git a/Platforms/AMD/Styx/Library/AmdStyxLib/StyxMem.c b/Platforms/AMD/Styx/Library/AmdStyxLib/StyxMem.c new file mode 100644 index 0000000..3b82132 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxLib/StyxMem.c @@ -0,0 +1,118 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+
+#if !defined(MDEPKG_NDEBUG)
+
+static const char *tblAttrDesc[] =
+{
+ "UNCACHED_UNBUFFERED ",
+ "NONSECURE_UNCACHED_UNBUFFERED",
+ "WRITE_BACK ",
+ "NONSECURE_WRITE_BACK ",
+ "WRITE_THROUGH ",
+ "NONSECURE_WRITE_THROUGH ",
+ "DEVICE ",
+ "NONSECURE_DEVICE "
+};
+#endif
+
+#define LOG_MEM(desc) DEBUG ((EFI_D_ERROR, desc, VirtualMemoryTable[Index].PhysicalBase, \
+ ( VirtualMemoryTable[Index].PhysicalBase+VirtualMemoryTable[Index].Length - 1), \
+ VirtualMemoryTable[Index].Length, tblAttrDesc[VirtualMemoryTable[Index].Attributes]));
+
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ ASSERT(VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;
+ } else {
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+ }
+
+ DEBUG ((EFI_D_ERROR, " Memory Map\n------------------------------------------------------------------------\n"));
+ DEBUG ((EFI_D_ERROR, "Description : START - END [ SIZE ] { ATTR }\n"));
+
+ // 0xE000_0000 - 0xEFFF_FFFF: Mapped I/O space
+ VirtualMemoryTable[Index].PhysicalBase = 0xE0000000UL;
+ VirtualMemoryTable[Index].VirtualBase = 0xE0000000UL;
+ VirtualMemoryTable[Index].Length = SIZE_256MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("I/O Space [Platform MMIO] : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // 0xF000_0000 - 0xFFFF_FFFF: PCI config space
+ VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000UL;
+ VirtualMemoryTable[Index].VirtualBase = 0xF0000000UL;
+ VirtualMemoryTable[Index].Length = SIZE_256MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("I/O Space [PCI config space] : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // DRAM
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+ LOG_MEM ("DRAM : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c new file mode 100644 index 0000000..8d8c76a --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c @@ -0,0 +1,196 @@ +/** @file
+ PCI Host Bridge Library instance for AMD Seattle SOC
+
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <PiDxe.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A08), // PCI Express
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ UINTN *Count
+ )
+{
+ PCI_ROOT_BRIDGE *RootBridge;
+
+ *Count = 1;
+ RootBridge = AllocateZeroPool (*Count * sizeof *RootBridge);
+
+ RootBridge->Segment = 0;
+
+ RootBridge->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
+ RootBridge->Attributes = RootBridge->Supports;
+
+ RootBridge->DmaAbove4G = TRUE;
+
+ RootBridge->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE ;
+
+ RootBridge->Bus.Base = PcdGet32 (PcdPciBusMin);
+ RootBridge->Bus.Limit = PcdGet32 (PcdPciBusMax);
+ RootBridge->Io.Base = PcdGet64 (PcdPciIoBase);
+ RootBridge->Io.Limit = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1;
+ RootBridge->Mem.Base = PcdGet32 (PcdPciMmio32Base);
+ RootBridge->Mem.Limit = PcdGet32 (PcdPciMmio32Base) + PcdGet32 (PcdPciMmio32Size) - 1;
+ RootBridge->MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);
+ RootBridge->MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) + PcdGet64 (PcdPciMmio64Size) - 1;
+
+ //
+ // No separate ranges for prefetchable and non-prefetchable BARs
+ //
+ RootBridge->PMem.Base = MAX_UINT64;
+ RootBridge->PMem.Limit = 0;
+ RootBridge->PMemAbove4G.Base = MAX_UINT64;
+ RootBridge->PMemAbove4G.Limit = 0;
+
+ ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0);
+ ASSERT (FixedPcdGet64 (PcdPciMmio64Translation) == 0);
+
+ RootBridge->NoExtendedConfigSpace = FALSE;
+
+ RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
+
+ return RootBridge;
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+ FreePool (Bridges);
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+ sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+ )
+ );
+ DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf new file mode 100644 index 0000000..3fdaf14 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf @@ -0,0 +1,55 @@ +## @file
+# PCI Host Bridge Library instance for AMD Seattle SOC
+#
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxPciHostBridgeLib
+ FILE_GUID = 05E7AB83-EF8D-482D-80F8-905B73377A15
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ AmdStyxPciHostBridgeLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ DevicePathLib
+ MemoryAllocationLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+ gArmTokenSpaceGuid.PcdPciMmio64Translation
diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/GicV3.S b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/GicV3.S new file mode 100644 index 0000000..617a6ff --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/GicV3.S @@ -0,0 +1,73 @@ +//
+// Copyright (c) 2013-2014, ARM Limited. All rights reserved.<BR>
+// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//**
+// Derived from:
+// ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S
+//
+//**
+
+
+#include <AsmMacroIoLibV8.h>
+
+// Register definitions used by GCC for GICv3 access.
+// These are defined by ARMCC, so keep them in the GCC specific code for now.
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(InitializeGicV3)
+
+/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */
+ASM_PFX(InitializeGicV3):
+ // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup
+ // to allow Linux to use GICv3 if it chooses.
+
+ // In order to setup NS side we need to enable it first.
+ mrs x0, scr_el3
+ orr x0, x0, #1
+ msr scr_el3, x0
+
+ // Enable SRE at EL3 and ICC_SRE_EL2 access
+ mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE
+ mrs x1, ICC_SRE_EL3
+ orr x1, x1, x0
+ msr ICC_SRE_EL3, x1
+ isb
+
+ // Enable SRE at EL2 and ICC_SRE_EL1 access..
+ mrs x1, ICC_SRE_EL2
+ orr x1, x1, x0
+ msr ICC_SRE_EL2, x1
+ isb
+
+ // Configure CPU interface
+ msr ICC_CTLR_EL3, xzr
+ isb
+ msr ICC_CTLR_EL1, xzr
+ isb
+
+ // The MemoryMap view and Register view may not be consistent, So Set PMR again.
+ mov w1, #1 << 7 // allow NS access to GICC_PMR
+ msr ICC_PMR_EL1, x1
+ isb
+
+ // Remove the SCR.NS bit
+ mrs x0, scr_el3
+ bic x0, x0, #1
+ msr scr_el3, x0
+ ret
diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/StyxBoot.S b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/StyxBoot.S new file mode 100644 index 0000000..c9e3163 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AArch64/StyxBoot.S @@ -0,0 +1,182 @@ +//
+// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.<BR>
+// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//**
+// Derived from:
+// ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/RTSMBoot.S
+//
+//**
+
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <AutoGen.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)
+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
+GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite)
+GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead)
+
+/**
+ Call at the beginning of the platform boot up
+
+ This function allows the firmware platform to do extra actions at the early
+ stage of the platform power up.
+
+ Note: This function must be implemented in assembler as there is no stack set up yet
+
+**/
+ASM_PFX(ArmPlatformSecBootAction):
+ /*
+ * Cortex-A57 Errata
+ */
+ // Enable CPUECTLR.SMPEN for SMP
+ mrs x13, s3_1_c15_c2_1 // Read CPUECTLR
+ bfi x13, x1, #6, #1 // Set bit 6; SMPEN: Allow PE to receive IC and TLB operations broadcast from others
+ msr s3_1_c15_c2_1, x13
+ isb
+
+ /*
+ * NIC400 initialization.
+ *
+ * Setting all registers to unsecure.
+ */
+ movz x1, #0xFFFF, LSL #16
+ movk x1, #0xFFFF
+
+ // NIC400 Bot VDD
+ movz x0, #0xE1B0, LSL #16
+ movk x0, #0x0008
+ str w1, [x0]
+ movk x0, #0x000C
+ str w1, [x0]
+ movk x0, #0x0010
+ str w1, [x0]
+ movk x0, #0x0014
+ str w1, [x0]
+ movk x0, #0x0018
+ str w1, [x0]
+ movk x0, #0x0020
+ str w1, [x0]
+ movk x0, #0x0024
+ str w1, [x0]
+ movk x0, #0x0028
+ str w1, [x0]
+ movk x0, #0x002C
+ str w1, [x0]
+ movk x0, #0x0030
+ str w1, [x0]
+ movk x0, #0x0038
+ str w1, [x0]
+ movk x0, #0x001C
+ str w1, [x0]
+
+ // NIC400 Top VDD
+ movz x0, #0xE1C0, LSL #16
+ movk x0, #0x0010
+ str w1, [x0]
+ movk x0, #0x0014
+ str w1, [x0]
+ movk x0, #0x0018
+ str w1, [x0]
+
+ // NIC400 TOP VDDN
+ movz x0, #0xE1D0, LSL #16
+ movk x0, #0x0008
+ str w1, [x0]
+ movk x0, #0x000C
+ str w1, [x0]
+ movk x0, #0x0010
+ str w1, [x0]
+ movk x0, #0x0014
+ str w1, [x0]
+ movk x0, #0x0018
+ str w1, [x0]
+ movk x0, #0x0020
+ str w1, [x0]
+ movk x0, #0x0024
+ str w1, [x0]
+ movk x0, #0x002C
+ str w1, [x0]
+ movk x0, #0x0030
+ str w1, [x0]
+
+# 0000_1111_0111_1111_0000_0001_0000_0001 (0x0F7F0101):
+# |||| |||| |||| |||| |||| |||| |||| ||||
+# |||| |||| |||| |||| |||| |||| |||| |||+- 0: CLIENTPD (1)
+# |||| |||| |||| |||| |||| |||| |||| ||+-- 1: GFRE (0)
+# |||| |||| |||| |||| |||| |||| |||| |+--- 2: GFIE (0)
+# |||| |||| |||| |||| |||| |||| |||| +---- 3: Reserved (0)
+# |||| |||| |||| |||| |||| |||| ||||
+# |||| |||| |||| |||| |||| |||| |||+ ----- 4: GCFGFRE (0)
+# |||| |||| |||| |||| |||| |||| ||+- ----- 5: GCFGFIE (0)
+# |||| |||| |||| |||| |||| |||| ++-- ----- 6-7: Reserved (0)
+# |||| |||| |||| |||| |||| ||||
+# |||| |||| |||| |||| |||| |||| ---- ----- 8: STALLD (1)
+# |||| |||| |||| |||| |||| ||+- ---- ----- 9: GSE (0)
+# |||| |||| |||| |||| |||| |+-- ---- ----- 10: USFCFG (0)
+# |||| |||| |||| |||| |||| +--- ---- ----- 11: VMIDPNE (0)
+# |||| |||| |||| |||| ||||
+# |||| |||| |||| |||| |||+ ---- ---- ----- 12: PTM (0)
+# |||| |||| |||| |||| ||+- ---- ---- ----- 13: FB (0)
+# |||| |||| |||| |||| ++-- ---- ---- ----- 14-15: BSU (0)
+# |||| |||| |||| ||||
+# |||| |||| |||| ++++ ---- ---- ---- ----- 16-19: MEMATTR (F)
+# |||| |||| ||||
+# |||| |||| |||+ ---- ---- ---- ---- ----- 20: MTCFG (1)
+# |||| |||| ||+- ---- ---- ---- ---- ----- 21: SMCFCFG (1)
+# |||| |||| ++-- ---- ---- ---- ---- ----- 22-23: SHCFG (1)
+# |||| ||||
+# |||| ||++ ---- ---- ---- ---- ---- ----- 24-25: RACFG (3)
+# |||| ++-- ---- ---- ---- ---- ---- ----- 26-27: WACFG (3)
+# ||||
+# ||++ ---- ---- ---- ---- ---- ---- ----- 28-29: NSCFG (0)
+# ++-- ---- ---- ---- ---- ---- ---- ----- 30-31: Reserved (0)
+
+ // Workaround for A0, force the memory attributes
+ ldr x0, =0xE0200000 // SMMU_SCR0
+ ldr w1, =0x0F7F0101
+ str w1, [x0, #0]
+
+ ldr x0, =0xE0200400 // SMMU_NSCR0
+ ldr w1, =0x0F7F0101
+ str w1, [x0, #0]
+ ret
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformSecBootMemoryInit):
+ // The SMC does not need to be initialized for RTSM
+ ret
+
+/* Write the flag register used to start Secondary cores */
+ASM_PFX(ArmSecMpCoreSecondariesWrite):
+ // Write to the CPU Mailbox
+ ret
+
+/* Read the flag register used to start Secondary cores */
+ASM_PFX(ArmSecMpCoreSecondariesRead):
+ // Return the value from the CPU Mailbox
+ mov x0, #0
+ ret
+
diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf new file mode 100644 index 0000000..9f08237 --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf @@ -0,0 +1,50 @@ +#/* @file
+#
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+#/**
+# Derived from:
+# ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxSecLib
+ FILE_GUID = af95afa9-fc3f-47b4-9237-d024305cd2e2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformSecLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ SerialPortLib
+
+[Sources.common]
+ StyxSec.c
+
+[Sources.AARCH64]
+ AArch64/StyxBoot.S | GCC
+ AArch64/GicV3.S | GCC
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
diff --git a/Platforms/AMD/Styx/Library/AmdStyxSecLib/StyxSec.c b/Platforms/AMD/Styx/Library/AmdStyxSecLib/StyxSec.c new file mode 100644 index 0000000..e5ff4ed --- /dev/null +++ b/Platforms/AMD/Styx/Library/AmdStyxSecLib/StyxSec.c @@ -0,0 +1,96 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
+
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Drivers/PL310L2Cache.h>
+#include <Drivers/SP804Timer.h>
+
+
+// Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet
+VOID
+InitializeGicV3 (
+ VOID
+ );
+
+/**
+ Initialize the Secure peripherals and memory regions
+
+ If Trustzone is supported by your platform then this function makes the required initialization
+ of the secure peripherals and memory regions.
+
+**/
+VOID
+ArmPlatformSecTrustzoneInit (
+ IN UINTN MpId
+ )
+{
+ // No TZPC or TZASC on RTSM to initialize
+}
+
+/**
+ Initialize controllers that must setup at the early stage
+
+ Some peripherals must be initialized in Secure World.
+ For example, some L2x0 requires to be initialized in Secure World
+
+**/
+RETURN_STATUS
+ArmPlatformSecInitialize (
+ IN UINTN MpId
+ )
+{
+ UINT32 Identification;
+
+ // If it is not the primary core then there is nothing to do
+ if (!ArmPlatformIsPrimaryCore (MpId)) {
+ return RETURN_SUCCESS;
+ }
+
+ // Read the GIC Identification Register
+ Identification = MmioRead32 (FixedPcdGet64(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIIDR);
+
+ // Check if we are GICv3
+ if (ARM_GIC_ICCIIDR_GET_ARCH_VERSION(Identification) >= 0x3) {
+ InitializeGicV3 ();
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Call before jumping to Normal World
+
+ This function allows the firmware platform to do extra actions before
+ jumping to the Normal World
+
+**/
+VOID
+ArmPlatformSecExtraAction (
+ IN UINTN MpId,
+ OUT UINTN* JumpAddress
+ )
+{
+ *JumpAddress = PcdGet64(PcdFvBaseAddress);
+}
diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c new file mode 100644 index 0000000..13388c1 --- /dev/null +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -0,0 +1,186 @@ +/** @file
+
+ Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016 AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.c
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+VOID
+InitMmu (
+ VOID
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+ // Note: Because we called PeiServicesInstallPeiMemory() before to call
+ // InitMmu() the MMU Page Table resides in DRAM (even at the top
+ // of DRAM as it is the first permanent memory allocation)
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Failed to enable MMU\n"));
+ }
+}
+
+STATIC
+VOID
+MoveNvStoreImage (
+ VOID
+ )
+{
+ VOID *OldBase, *NewBase;
+ UINTN Size;
+
+ //
+ // Move the in-memory image of the NV store firmware volume to a dynamically
+ // allocated buffer. This gets rid of the annoying static memory reservation
+ // at the base of memory where all other UEFI allocations are near the top.
+ //
+ OldBase = (VOID *)FixedPcdGet64 (PcdFlashNvStorageOriginalBase);
+
+ Size = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+ NewBase = AllocateAlignedRuntimePages (EFI_SIZE_TO_PAGES (Size), SIZE_64KB);
+ ASSERT (NewBase != NULL);
+
+ CopyMem (NewBase, OldBase, Size);
+
+ DEBUG ((EFI_D_INFO, "%a: Relocating NV store FV from %p to %p\n",
+ __FUNCTION__, OldBase, NewBase));
+
+ PcdSet64 (PcdFlashNvStorageVariableBase64, (UINT64)NewBase);
+
+ PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, (UINT64)NewBase +
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize));
+
+ PcdSet64 (PcdFlashNvStorageFtwSpareBase64, (UINT64)NewBase +
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize));
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ UINT64 Base, Size;
+
+ // Ensure PcdSystemMemorySize has been set
+ ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);
+
+ //
+ // Now, the permanent memory has been installed, we can call AllocatePages()
+ //
+
+ Base = PcdGet64 (PcdSystemMemoryBase);
+ Size = PcdGet64 (PcdSystemMemorySize);
+ if (FixedPcdGetBool (PcdTrustedFWSupport)) {
+
+ //
+ // For now, we assume that the trusted firmware region is at the base of
+ // system memory, since that is much easier to deal with.
+ //
+ ASSERT (Base == PcdGet64 (PcdTrustedFWMemoryBase));
+
+ Base += PcdGet64 (PcdTrustedFWMemorySize);
+ Size -= PcdGet64 (PcdTrustedFWMemorySize);
+
+ // Reserved Trusted Firmware region
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ( EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED ),
+ PcdGet64 (PcdTrustedFWMemoryBase),
+ PcdGet64 (PcdTrustedFWMemorySize)
+ );
+
+ BuildMemoryAllocationHob (
+ PcdGet64 (PcdTrustedFWMemoryBase),
+ PcdGet64 (PcdTrustedFWMemorySize),
+ EfiReservedMemoryType
+ );
+ }
+
+ // Declare system memory
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ( EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED ),
+ Base,
+ Size
+ );
+
+ // Build Memory Allocation Hob
+ InitMmu ();
+
+ // Optional feature that helps prevent EFI memory map fragmentation.
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+ BuildMemoryTypeInformationHob ();
+ }
+
+ MoveNvStoreImage ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf new file mode 100644 index 0000000..42f755b --- /dev/null +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -0,0 +1,92 @@ +#/** @file
+#
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#**/
+#/**
+# Derived from:
+# ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxMemoryInitPeiLib
+ FILE_GUID = 25466f78-a75a-4aae-be09-a68a347c3228
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM
+
+[Sources]
+ MemoryInitPeiLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ ArmLib
+ ArmPlatformLib
+ PcdLib
+
+[Ppis]
+ gAmdStyxPlatInitPpiGuid ## CONSUMER
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
+
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize
+
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+
+[Depex]
+ gAmdStyxPlatInitPpiGuid
diff --git a/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c new file mode 100644 index 0000000..1b92624 --- /dev/null +++ b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c @@ -0,0 +1,277 @@ +/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ Derived from:
+ ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Guid/EventGroup.h>
+
+#include <Protocol/AmdIscpDxeProtocol.h>
+#include <Iscp.h>
+
+extern EFI_BOOT_SERVICES *gBS;
+
+AMD_ISCP_DXE_PROTOCOL *mRtcIscpDxeProtocol = NULL;
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
+
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ ISCP_RTC_INFO RtcInfo;
+ EFI_STATUS Status;
+
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (mRtcIscpDxeProtocol == NULL) {
+ DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Fill in Time and Capabilities via data from you RTC
+ //
+ Status = mRtcIscpDxeProtocol->AmdExecuteGetRtc (
+ mRtcIscpDxeProtocol,
+ &RtcInfo
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "RTC: Failed GetRtc() via ISCP - Status = %r \n", Status));
+ return Status;
+ }
+
+ Time->Year = RtcInfo.Year;
+ Time->Month = RtcInfo.Month;
+ Time->Day = RtcInfo.Day;
+ Time->Hour = RtcInfo.Hour;
+ Time->Minute = RtcInfo.Minute;
+ Time->Second = RtcInfo.Second;
+
+ return Status;
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ EFI_STATUS Status;
+ ISCP_RTC_INFO RtcInfo;
+
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Use Time, to set the time in your RTC hardware
+ //
+ RtcInfo.Year = Time->Year;
+ RtcInfo.Month = Time->Month;
+ RtcInfo.Day = Time->Day;
+ RtcInfo.Hour = Time->Hour;
+ RtcInfo.Minute = Time->Minute;
+ RtcInfo.Second = Time->Second;
+
+ if (mRtcIscpDxeProtocol == NULL) {
+ DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = mRtcIscpDxeProtocol->AmdExecuteSetRtc (
+ mRtcIscpDxeProtocol,
+ &RtcInfo
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "RTC: Failed SetRtc() via ISCP - Status = %r \n", Status));
+ return Status;
+ }
+
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ if (!FixedPcdGetBool (PcdIscpSupport)) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Do some initialization if required to turn on the RTC
+ //
+ Status = gBS->LocateProtocol (
+ &gAmdIscpDxeProtocolGuid,
+ NULL,
+ (VOID **)&mRtcIscpDxeProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "RTC: Failed to Locate ISCP DXE Protocol - Status = %r \n", Status));
+ return Status;
+ }
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ LibRtcVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mRtcVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transistions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ if (FixedPcdGetBool (PcdIscpSupport)) {
+ EfiConvertPointer (0x0, (VOID**)&mRtcIscpDxeProtocol);
+ }
+}
+
+
+
diff --git a/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf new file mode 100644 index 0000000..9a66934 --- /dev/null +++ b/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf @@ -0,0 +1,57 @@ +#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxRealTimeClockLib
+ FILE_GUID = fd922639-f4ee-4d2f-955b-804e60df1e68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ RealTimeClockLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ UefiRuntimeLib
+ DxeServicesTableLib
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+ gAmdIscpDxeProtocolGuid ## CONSUMER
+
+[Depex]
+ gAmdIscpDxeProtocolGuid
+
+
+
diff --git a/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.c b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 0000000..90eec09 --- /dev/null +++ b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,113 @@ +/** @file
+ Support ResetSystem Runtime call using PSCI calls
+
+ Note: A similar library is implemented in
+ ArmVirtPkg/Library/ArmVirtualizationPsciResetSystemLib
+ So similar issues might exist in this implementation too.
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ Derived from:
+ ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/EfiResetSystemLib.h>
+#include <Library/ArmSmcLib.h>
+
+#include <IndustryStandard/ArmStdSmc.h>
+
+/**
+ Resets the entire platform.
+
+ @param ResetType The type of reset to perform.
+ @param ResetStatus The status code for the reset.
+ @param DataSize The size, in bytes, of WatchdogData.
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
+ EfiResetShutdown the data buffer starts with a Null-terminated
+ Unicode string, optionally followed by additional binary data.
+
+**/
+EFI_STATUS
+EFIAPI
+LibResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN CHAR16 *ResetData OPTIONAL
+ )
+{
+ ARM_SMC_ARGS ArmSmcArgs;
+
+ if (!FixedPcdGetBool (PcdTrustedFWSupport)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ switch (ResetType) {
+ case EfiResetPlatformSpecific:
+ // Map the platform specific reset as reboot
+ case EfiResetWarm:
+ // Map a warm reset into a cold reset
+ case EfiResetCold:
+ // Send a PSCI 0.2 SYSTEM_RESET command
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
+ break;
+ case EfiResetShutdown:
+ // Send a PSCI 0.2 SYSTEM_OFF command
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmCallSmc (&ArmSmcArgs);
+
+ // We should never be here
+ DEBUG ((EFI_D_ERROR, "%a: PSCI Reset failed\n", __FUNCTION__));
+ CpuDeadLoop ();
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Initialize any infrastructure required for LibResetSystem () to function.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+LibInitializeResetSystem (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+
+ if (FixedPcdGetBool (PcdTrustedFWSupport)) {
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
diff --git a/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 0000000..5af4c9c --- /dev/null +++ b/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,47 @@ +#/** @file
+# Reset System lib using PSCI hypervisor or secure monitor calls
+#
+# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#/**
+# Derived from:
+# ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmdStyxResetSystemLib
+ FILE_GUID = 624f6cc6-c38f-4897-b3b7-8a601701291b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EfiResetSystemLib
+
+[Sources.common]
+ ResetSystemLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+
+[LibraryClasses]
+ PcdLib
+ BaseLib
+ ArmSmcLib
+
+[FixedPcd]
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
diff --git a/Platforms/AMD/Styx/License.txt b/Platforms/AMD/Styx/License.txt new file mode 100644 index 0000000..ff85835 --- /dev/null +++ b/Platforms/AMD/Styx/License.txt @@ -0,0 +1,25 @@ +Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
diff --git a/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin b/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin Binary files differnew file mode 100644 index 0000000..8da3b4f --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb Binary files differnew file mode 100644 index 0000000..0c0468d --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts new file mode 100644 index 0000000..dab3c2c --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -0,0 +1,446 @@ +/* + * DTS file for AMD Seattle (Rev.B) Overdrive Development Board + * + * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * This program and the accompanying materials are licensed and made available + * under the terms and conditions of the BSD License which accompanies this + * distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + * + */ + +/dts-v1/; + +/ { + model = "AMD Seattle (Rev.B) Development Board (Overdrive)"; + compatible = "amd,seattle-overdrive", "amd,seattle"; + interrupt-parent = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + interrupt-controller@e1101000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + reg = <0x0 0xe1110000 0x0 0x1000>, + <0x0 0xe112f000 0x0 0x2000>, + <0x0 0xe1140000 0x0 0x10000>, + <0x0 0xe1160000 0x0 0x10000>; + interrupts = <0x1 0x9 0xf04>; + ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; + linux,phandle = <0x1>; + phandle = <0x1>; + + v2m@e0080000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0x0 0x1000>; + linux,phandle = <0x4>; + phandle = <0x4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x1 0xd 0xff04>, + <0x1 0xe 0xff04>, + <0x1 0xb 0xff04>, + <0x1 0xa 0xff04>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x0 0x7 0x4>, + <0x0 0x8 0x4>, + <0x0 0x9 0x4>, + <0x0 0xa 0x4>, + <0x0 0xb 0x4>, + <0x0 0xc 0x4>, + <0x0 0xd 0x4>, + <0x0 0xe 0x4>; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + /* + * dma-ranges is 40-bit address space containing: + * - GICv2m MSI register is at 0xe0080000 + * - DRAM range [0x8000000000 to 0xffffffffff] + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + clk100mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <100000000>; + clock-output-names = "adl3clk_100mhz"; + }; + + clk375mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <375000000>; + clock-output-names = "ccpclk_375mhz"; + }; + + clk333mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <333000000>; + clock-output-names = "sataclk_333mhz"; + linux,phandle = <0x2>; + phandle = <0x2>; + }; + + clk500mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <500000000>; + clock-output-names = "pcieclk_500mhz"; + }; + + clk500mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <500000000>; + clock-output-names = "dmaclk_500mhz"; + }; + + clk250mhz_4 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "miscclk_250mhz"; + linux,phandle = <0xd>; + phandle = <0xd>; + }; + + clk100mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <100000000>; + clock-output-names = "uartspiclk_100mhz"; + linux,phandle = <0x3>; + phandle = <0x3>; + }; + + sata@e0300000 { + compatible = "snps,dwc-ahci"; + reg = <0x0 0xe0300000 0x0 0xf0000>; + interrupts = <0x0 0x163 0x4>; + clocks = <0x2>; + dma-coherent; + }; + + sata@e0d00000 { + status = "disabled"; + compatible = "snps,dwc-ahci"; + reg = <0x0 0xe0d00000 0x0 0xf0000>; + interrupts = <0x0 0x162 0x4>; + clocks = <0x2>; + dma-coherent; + }; + + i2c@e1000000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xe1000000 0x0 0x1000>; + interrupts = <0x0 0x165 0x4>; + clocks = <0xd>; + }; + + i2c@e0050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xe0050000 0x0 0x1000>; + interrupts = <0x0 0x154 0x4>; + clocks = <0xd>; + }; + + serial@e1010000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xe1010000 0x0 0x1000>; + interrupts = <0x0 0x148 0x4>; + clocks = <0x3 0x3>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp@e1020000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xe1020000 0x0 0x1000>; + spi-controller; + interrupts = <0x0 0x14a 0x4>; + clocks = <0x3>; + clock-names = "apb_pclk"; + }; + + ssp@e1030000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xe1030000 0x0 0x1000>; + spi-controller; + interrupts = <0x0 0x149 0x4>; + clocks = <0x3>; + clock-names = "apb_pclk"; + num-cs = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + sdcard@0 { + compatible = "mmc-spi-slot"; + reg = <0x0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3200 3400>; + pl022,hierarchy = <0x0>; + pl022,interface = <0x0>; + pl022,com-mode = <0x0>; + pl022,rx-level-trig = <0x0>; + pl022,tx-level-trig = <0x0>; + }; + }; + + gpio@e1050000 { /* [0 : 7] */ + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe1050000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <0x0 0x166 0x4>; + clocks = <0x3>; + clock-names = "apb_pclk"; + }; + + gpio@e0020000 { /* [8 : 15] */ + status = "disabled"; + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0020000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <0x0 0x16e 0x4>; + clocks = <0x3>; + clock-names = "apb_pclk"; + }; + + gpio@e0030000 { /* [16 : 23] */ + status = "disabled"; + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0030000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <0x0 0x16d 0x4>; + clocks = <0x3>; + clock-names = "apb_pclk"; + }; + + gpio@e0080000 { /* [24] */ + compatible = "arm,pl061", "arm,primecell"; + #gpio-cells = <0x2>; + reg = <0x0 0xe0080000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <0x2>; + interrupts = <0x0 0x169 0x4>; + clocks = <0x3>; + clock-names = "apb_pclk"; + }; + + ccp: ccp@e0100000 { + compatible = "amd,ccp-seattle-v1a"; + reg = <0x0 0xe0100000 0x0 0x10000>; + interrupts = <0x0 0x3 0x4>; + dma-coherent; + amd,zlib-support = <0x1>; + }; + + pcie: pcie@f0000000 { + compatible = "pci-host-ecam-generic"; + #address-cells = <0x3>; + #size-cells = <0x2>; + #interrupt-cells = <0x1>; + device_type = "pci"; + bus-range = <0x0 0x7f>; + msi-parent = <0x4>; + reg = <0x0 0xf0000000 0x0 0x10000000>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, + <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, + <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, + <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>; + dma-coherent; + dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; + ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ + <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */ + <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */ + }; + + ccn@0xe8000000 { + compatible = "arm,ccn-504"; + reg = <0x0 0xe8000000 0x0 0x1000000>; + interrupts = <0x0 0x17c 0x4>; + }; + + gwdt@e0bb0000 { + status = "disabled"; + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0xe0bb0000 0x0 0x10000 + 0x0 0xe0bc0000 0x0 0x10000>; + reg-names = "refresh", "control"; + interrupts = <0x0 0x151 0x4>; + interrupt-names = "ws0"; + }; + + kcs@e0010000 { + status = "disabled"; + compatible = "ipmi-kcs"; + device_type = "ipmi"; + reg = <0x0 0xe0010000 0 0x8>; + interrupts = <0 389 4>; + interrupt-names = "ipmi_kcs"; + reg-size = <1>; + reg-spacing = <4>; + }; + + clk250mhz_0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk0_dma_250mhz"; + linux,phandle = <0x5>; + phandle = <0x5>; + }; + + clk250mhz_1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk0_ptp_250mhz"; + linux,phandle = <0x6>; + phandle = <0x6>; + }; + + clk250mhz_2 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk1_dma_250mhz"; + linux,phandle = <0x7>; + phandle = <0x7>; + }; + + clk250mhz_3 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <250000000>; + clock-output-names = "xgmacclk1_ptp_250mhz"; + linux,phandle = <0x8>; + phandle = <0x8>; + }; + + phy@e1240800 { + status = "disabled"; + compatible = "amd,xgbe-phy-seattle-v1a"; + reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts = <0x0 0x143 0x4>; + amd,speed-set = <0x0>; + amd,serdes-blwc = <0x1 0x1 0x0>; + amd,serdes-cdr-rate = <0x2 0x2 0x7>; + amd,serdes-pq-skew = <0xa 0xa 0x12>; + amd,serdes-tx-amp = <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; + linux,phandle = <0x9>; + phandle = <0x9>; + }; + + phy@e1240c00 { + status = "disabled"; + compatible = "amd,xgbe-phy-seattle-v1a"; + reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts = <0x0 0x142 0x4>; + amd,speed-set = <0x0>; + amd,serdes-blwc = <0x1 0x1 0x0>; + amd,serdes-cdr-rate = <0x2 0x2 0x7>; + amd,serdes-pq-skew = <0xa 0xa 0x12>; + amd,serdes-tx-amp = <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; + linux,phandle = <0xa>; + phandle = <0xa>; + }; + + xgmac@e0700000 { + status = "disabled"; + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; + interrupts = <0x0 0x145 0x4>, + <0x0 0x15a 0x1>, + <0x0 0x15b 0x1>, + <0x0 0x15c 0x1>, + <0x0 0x15d 0x1>; + amd,per-channel-interrupt; + mac-address = [02 a1 a2 a3 a4 a5]; + clocks = <0x5 0x6>; + clock-names = "dma_clk", "ptp_clk"; + phy-handle = <0x9>; + phy-mode = "xgmii"; + #stream-id-cells = <0x18>; + dma-coherent; + linux,phandle = <0xb>; + phandle = <0xb>; + }; + + xgmac@e0900000 { + status = "disabled"; + compatible = "amd,xgbe-seattle-v1a"; + reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; + interrupts = <0x0 0x144 0x4>, + <0x0 0x155 0x1>, + <0x0 0x156 0x1>, + <0x0 0x157 0x1>, + <0x0 0x158 0x1>; + amd,per-channel-interrupt; + mac-address = [02 b1 b2 b3 b4 b5]; + clocks = <0x7 0x8>; + clock-names = "dma_clk", "ptp_clk"; + phy-handle = <0xa>; + phy-mode = "xgmii"; + #stream-id-cells = <0x18>; + dma-coherent; + linux,phandle = <0xc>; + phandle = <0xc>; + }; + }; + + chosen { + stdout-path = "/smb/serial@e1010000"; + /* Note: + * Linux support for pci-probe-only DT is not + * stable. Disable this for now and let Linux + * take care of the resource assignment. + */ + // linux,pci-probe-only; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + }; +}; + + diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c new file mode 100644 index 0000000..13fc9c1 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/BdsLinuxFdt.c @@ -0,0 +1,763 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.<BR>
+* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+
+ Derived from:
+ ArmPkg/Library/BdsLib/BdsLinuxFdt.c
+
+**/
+
+#include <Library/PcdLib.h>
+#include <libfdt.h>
+
+#include <Library/BdsLib/BdsInternal.h>
+
+#include <Guid/ArmMpCoreInfo.h>
+#include <Protocol/AmdMpCoreInfo.h>
+
+#define LINUX_FDT_MAX_OFFSET (PcdGet64 (PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))
+
+
+// Additional size that could be used for FDT entries added by the UEFI OS Loader
+// Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes)
+// + system memory region (20bytes) + mp_core entries (200 bytes)
+#define FDT_ADDITIONAL_ENTRIES_SIZE 0x300
+
+
+EFI_STATUS
+GetSystemMemoryResources (
+ IN LIST_ENTRY *ResourceList
+ );
+
+VOID
+DebugDumpFdt (
+ IN VOID* FdtBlob
+ );
+
+#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1))
+#define PALIGN(p, a) ((void *)(ALIGN((unsigned long)(p), (a))))
+#define GET_CELL(p) (p += 4, *((const UINT32 *)(p-4)))
+
+//
+// PMU interrupts per core
+//
+#pragma pack(push, 1)
+typedef struct {
+ UINT32 Flag; // 0 == SPI
+ UINT32 IntId; // GSIV == IntId+32
+ UINT32 Type; // 4 == Level-Sensitive, Active-High
+} PMU_INTERRUPT;
+#pragma pack(pop)
+
+#define PMU_INT_FLAG_SPI 0
+#define PMU_INT_TYPE_HIGH_LEVEL 4
+
+
+typedef struct {
+ UINTN Base;
+ UINTN Size;
+} FdtRegion;
+
+
+STATIC
+UINTN
+cpu_to_fdtn (UINTN x) {
+ if (sizeof (UINTN) == sizeof (UINT32)) {
+ return cpu_to_fdt32 (x);
+ } else {
+ return cpu_to_fdt64 (x);
+ }
+}
+
+
+STATIC
+BOOLEAN
+ClusterInRange(
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN ClusterId,
+ IN UINTN LowIndex,
+ IN UINTN HighIndex
+ )
+{
+ do {
+ if (ClusterId == ArmCoreInfoTable[LowIndex].ClusterId)
+ return TRUE;
+ } while (++LowIndex <= HighIndex);
+
+ return FALSE;
+}
+
+
+STATIC
+UINTN
+NumberOfCoresInCluster(
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN NumberOfEntries,
+ IN UINTN ClusterId
+ )
+{
+ UINTN Index, Cores;
+
+ Cores = 0;
+ for (Index = 0; Index < NumberOfEntries; ++Index) {
+ if (ClusterId == ArmCoreInfoTable[Index].ClusterId)
+ ++Cores;
+ }
+
+ return Cores;
+}
+
+
+STATIC
+UINTN
+NumberOfClustersInTable(
+ IN ARM_CORE_INFO *ArmCoreInfoTable,
+ IN UINTN NumberOfEntries
+ )
+{
+ UINTN Index, Cores, Clusters, ClusterId;
+
+ Index = 0;
+ Clusters = 0;
+ Cores = NumberOfEntries;
+ while (Cores) {
+ ++Clusters;
+ ClusterId = ArmCoreInfoTable[Index].ClusterId;
+ Cores -= NumberOfCoresInCluster (ArmCoreInfoTable,
+ NumberOfEntries,
+ ClusterId);
+ if (Cores) {
+ do {
+ ++Index;
+ } while (ClusterInRange (ArmCoreInfoTable,
+ ArmCoreInfoTable[Index].ClusterId,
+ 0, Index-1));
+ }
+ }
+
+ return Clusters;
+}
+
+
+STATIC
+int
+fdt_alloc_phandle(
+ IN VOID *blob
+ )
+{
+
+ int offset, phandle = 0;
+
+ for (offset = fdt_next_node(blob, -1, NULL); offset >= 0;
+ offset = fdt_next_node(blob, offset, NULL)) {
+ phandle = MAX(phandle, fdt_get_phandle(blob, offset));
+ }
+
+ return phandle + 1;
+}
+
+
+STATIC
+BOOLEAN
+IsLinuxReservedRegion (
+ IN EFI_MEMORY_TYPE MemoryType
+ )
+{
+ switch(MemoryType) {
+ case EfiRuntimeServicesCode:
+ case EfiRuntimeServicesData:
+ case EfiUnusableMemory:
+ case EfiACPIReclaimMemory:
+ case EfiACPIMemoryNVS:
+ case EfiReservedMemoryType:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+STATIC
+VOID
+SetDeviceStatus (
+ IN VOID *fdt,
+ IN CHAR8 *device,
+ IN BOOLEAN enable
+ )
+{
+ int node, subnode, rc;
+
+ node = fdt_subnode_offset (fdt, 0, "smb");
+ if (node >= 0) {
+ subnode = fdt_subnode_offset (fdt, node, device);
+ if (subnode >= 0) {
+ rc = fdt_setprop_string(fdt, subnode, "status", enable ? "ok" : "disabled");
+ if (rc) {
+ DEBUG((EFI_D_ERROR,"%a: Could not set 'status' property for '%a' node\n",
+ __FUNCTION__, device));
+ }
+ }
+ }
+}
+
+#if DO_XGBE
+STATIC
+VOID
+SetMacAddress (
+ IN VOID *fdt,
+ IN CHAR8 *device,
+ IN UINT64 mac_addr
+ )
+{
+ int node, subnode, rc;
+
+ node = fdt_subnode_offset (fdt, 0, "smb");
+ if (node >= 0) {
+ subnode = fdt_subnode_offset (fdt, node, device);
+ if (subnode >= 0) {
+ rc = fdt_setprop(fdt, subnode, "mac-address", (void *)&mac_addr, 6);
+ if (rc) {
+ DEBUG((EFI_D_ERROR,"%a: Could not set 'mac-address' property for '%a' node\n",
+ __FUNCTION__, device));
+ }
+ }
+ }
+}
+#endif
+
+VOID
+SetSocIdStatus (
+ IN VOID *fdt
+ )
+{
+ UINT32 SocId;
+ BOOLEAN IsRevB1;
+
+ SocId = PcdGet32 (PcdSocCpuId);
+ IsRevB1 = (SocId & 0xFF0) && (SocId & 0x00F);
+
+#if DO_SATA1
+ SetDeviceStatus (fdt, "sata@e0d00000", IsRevB1);
+#else
+ SetDeviceStatus (fdt, "sata@e0d00000", FALSE);
+#endif
+ SetDeviceStatus (fdt, "gpio@e0020000", IsRevB1);
+ SetDeviceStatus (fdt, "gpio@e0030000", IsRevB1);
+ SetDeviceStatus (fdt, "gwdt@e0bb0000", IsRevB1);
+#if DO_KCS
+ SetDeviceStatus (fdt, "kcs@e0010000", IsRevB1);
+#else
+ SetDeviceStatus (fdt, "kcs@e0010000", FALSE);
+#endif
+}
+
+VOID
+SetXgbeStatus (
+ IN VOID *fdt
+ )
+{
+#if DO_XGBE
+ SetDeviceStatus (fdt, "xgmac@e0700000", TRUE);
+ SetDeviceStatus (fdt, "phy@e1240800", TRUE);
+ SetDeviceStatus (fdt, "xgmac@e0900000", TRUE);
+ SetDeviceStatus (fdt, "phy@e1240c00", TRUE);
+
+ SetMacAddress (fdt, "xgmac@e0700000", PcdGet64 (PcdEthMacA));
+ SetMacAddress (fdt, "xgmac@e0900000", PcdGet64 (PcdEthMacB));
+#else
+ SetDeviceStatus (fdt, "xgmac@e0700000", FALSE);
+ SetDeviceStatus (fdt, "phy@e1240800", FALSE);
+ SetDeviceStatus (fdt, "xgmac@e0900000", FALSE);
+ SetDeviceStatus (fdt, "phy@e1240c00", FALSE);
+#endif
+}
+
+
+/**
+** Relocate the FDT blob to a more appropriate location for the Linux kernel.
+** This function will allocate memory for the relocated FDT blob.
+**
+** @retval EFI_SUCCESS on success.
+** @retval EFI_OUT_OF_RESOURCES or EFI_INVALID_PARAMETER on failure.
+*/
+STATIC
+EFI_STATUS
+RelocateFdt (
+ EFI_PHYSICAL_ADDRESS OriginalFdt,
+ UINTN OriginalFdtSize,
+ EFI_PHYSICAL_ADDRESS *RelocatedFdt,
+ UINTN *RelocatedFdtSize,
+ EFI_PHYSICAL_ADDRESS *RelocatedFdtAlloc
+ )
+{
+ EFI_STATUS Status;
+ INTN Error;
+ UINT64 FdtAlignment;
+
+ *RelocatedFdtSize = OriginalFdtSize + FDT_ADDITIONAL_ENTRIES_SIZE;
+
+ // If FDT load address needs to be aligned, allocate more space.
+ FdtAlignment = PcdGet32 (PcdArmLinuxFdtAlignment);
+ if (FdtAlignment != 0) {
+ *RelocatedFdtSize += FdtAlignment;
+ }
+
+ // Try below a watermark address.
+ Status = EFI_NOT_FOUND;
+ if (PcdGet32 (PcdArmLinuxFdtMaxOffset) != 0) {
+ *RelocatedFdt = LINUX_FDT_MAX_OFFSET;
+ Status = gBS->AllocatePages (AllocateMaxAddress, EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (*RelocatedFdtSize), RelocatedFdt);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_WARN, "Warning: Failed to load FDT below address 0x%lX (%r). Will try again at a random address anywhere.\n", *RelocatedFdt, Status));
+ }
+ }
+
+ // Try anywhere there is available space.
+ if (EFI_ERROR (Status)) {
+ Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData,
+ EFI_SIZE_TO_PAGES (*RelocatedFdtSize), RelocatedFdt);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return EFI_OUT_OF_RESOURCES;
+ } else {
+ DEBUG ((EFI_D_WARN, "WARNING: Loaded FDT at random address 0x%lX.\nWARNING: There is a risk of accidental overwriting by other code/data.\n", *RelocatedFdt));
+ }
+ }
+
+ *RelocatedFdtAlloc = *RelocatedFdt;
+ if (FdtAlignment != 0) {
+ *RelocatedFdt = ALIGN (*RelocatedFdt, FdtAlignment);
+ }
+
+ // Load the Original FDT tree into the new region
+ Error = fdt_open_into ((VOID*)(UINTN) OriginalFdt,
+ (VOID*)(UINTN)(*RelocatedFdt), *RelocatedFdtSize);
+ if (Error) {
+ DEBUG ((EFI_D_ERROR, "fdt_open_into(): %a\n", fdt_strerror (Error)));
+ gBS->FreePages (*RelocatedFdtAlloc, EFI_SIZE_TO_PAGES (*RelocatedFdtSize));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ DEBUG_CODE_BEGIN();
+ // DebugDumpFdt ((VOID*)(UINTN)(*RelocatedFdt));
+ DEBUG_CODE_END();
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+AmdStyxPrepareFdt (
+ IN CONST CHAR8* CommandLineArguments,
+ IN EFI_PHYSICAL_ADDRESS InitrdImage,
+ IN UINTN InitrdImageSize,
+ IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
+ IN OUT UINTN *FdtBlobSize
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS NewFdtBlobBase;
+ EFI_PHYSICAL_ADDRESS NewFdtBlobAllocation;
+ UINTN NewFdtBlobSize;
+ VOID *fdt;
+ int err;
+ int node;
+ int cpu_node;
+ int lenp;
+ CONST VOID *BootArg;
+ EFI_PHYSICAL_ADDRESS InitrdImageStart;
+ EFI_PHYSICAL_ADDRESS InitrdImageEnd;
+ FdtRegion Region;
+ UINTN Index;
+ CHAR8 Name[10];
+ LIST_ENTRY ResourceList;
+ BDS_SYSTEM_MEMORY_RESOURCE *Resource;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN ArmCoreCount;
+ UINT32 PrimaryClusterId;
+ UINT32 PrimaryCoreId;
+ UINTN MemoryMapSize;
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapPtr;
+ UINTN MapKey;
+ UINTN DescriptorSize;
+ UINT32 DescriptorVersion;
+ UINTN Pages;
+ UINTN OriginalFdtSize;
+ int map_node;
+ int cluster_node;
+ int pmu_node;
+ PMU_INTERRUPT PmuInt;
+ int phandle[NUM_CORES];
+ UINT32 ClusterIndex, CoreIndex;
+ UINT32 ClusterCount, CoresInCluster;
+ UINT32 ClusterId;
+ UINTN MpId, MbAddr;
+ AMD_MP_CORE_INFO_PROTOCOL *AmdMpCoreInfoProtocol;
+
+ //
+ // Sanity checks on the original FDT blob.
+ //
+ err = fdt_check_header ((VOID*)(UINTN)(*FdtBlobBase));
+ if (err != 0) {
+ Print (L"ERROR: Device Tree header not valid (err:%d)\n", err);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // The original FDT blob might have been loaded partially.
+ // Check that it is not the case.
+ OriginalFdtSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(*FdtBlobBase));
+ if (OriginalFdtSize > *FdtBlobSize) {
+ Print (L"ERROR: Incomplete FDT. Only %d/%d bytes have been loaded.\n",
+ *FdtBlobSize, OriginalFdtSize);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Relocate the FDT to its final location.
+ //
+ NewFdtBlobAllocation = 0;
+ Status = RelocateFdt (*FdtBlobBase, OriginalFdtSize,
+ &NewFdtBlobBase, &NewFdtBlobSize, &NewFdtBlobAllocation);
+ if (EFI_ERROR (Status)) {
+ goto FAIL_RELOCATE_FDT;
+ }
+ fdt = (VOID*)(UINTN)NewFdtBlobBase;
+
+ node = fdt_subnode_offset (fdt, 0, "chosen");
+ if (node < 0) {
+ // The 'chosen' node does not exist, create it
+ node = fdt_add_subnode(fdt, 0, "chosen");
+ if (node < 0) {
+ DEBUG((EFI_D_ERROR,"Error on finding 'chosen' node\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+ }
+
+ DEBUG_CODE_BEGIN();
+ BootArg = fdt_getprop(fdt, node, "bootargs", &lenp);
+ if (BootArg != NULL) {
+ DEBUG((EFI_D_ERROR,"BootArg: %a\n",BootArg));
+ }
+ DEBUG_CODE_END();
+
+ //
+ // Set Linux CmdLine
+ //
+ if ((CommandLineArguments != NULL) && (AsciiStrLen (CommandLineArguments) > 0)) {
+ err = fdt_setprop(fdt, node, "bootargs", CommandLineArguments, AsciiStrSize(CommandLineArguments));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'bootarg' (err:%d)\n",err));
+ }
+ }
+
+ //
+ // Set Linux Initrd
+ //
+ if (InitrdImageSize != 0) {
+ InitrdImageStart = cpu_to_fdt64 (InitrdImage);
+ err = fdt_setprop(fdt, node, "linux,initrd-start", &InitrdImageStart, sizeof(EFI_PHYSICAL_ADDRESS));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err));
+ }
+ InitrdImageEnd = cpu_to_fdt64 (InitrdImage + InitrdImageSize);
+ err = fdt_setprop(fdt, node, "linux,initrd-end", &InitrdImageEnd, sizeof(EFI_PHYSICAL_ADDRESS));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'linux,initrd-start' (err:%d)\n",err));
+ }
+ }
+
+ //
+ // Set Physical memory setup if does not exist
+ //
+ node = fdt_subnode_offset(fdt, 0, "memory");
+ if (node < 0) {
+ // The 'memory' node does not exist, create it
+ node = fdt_add_subnode(fdt, 0, "memory");
+ if (node >= 0) {
+ fdt_setprop_string(fdt, node, "name", "memory");
+ fdt_setprop_string(fdt, node, "device_type", "memory");
+
+ GetSystemMemoryResources (&ResourceList);
+ Resource = (BDS_SYSTEM_MEMORY_RESOURCE*)ResourceList.ForwardLink;
+
+ Region.Base = cpu_to_fdtn ((UINTN)Resource->PhysicalStart);
+ Region.Size = cpu_to_fdtn ((UINTN)Resource->ResourceLength);
+
+ err = fdt_setprop(fdt, node, "reg", &Region, sizeof(Region));
+ if (err) {
+ DEBUG((EFI_D_ERROR,"Fail to set new 'memory region' (err:%d)\n",err));
+ }
+ }
+ }
+
+ //
+ // Add the memory regions reserved by the UEFI Firmware
+ //
+
+ // Retrieve the UEFI Memory Map
+ MemoryMap = NULL;
+ MemoryMapSize = 0;
+ Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive
+ // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size.
+ Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+ MemoryMap = AllocatePages (Pages);
+ if (MemoryMap == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FAIL_COMPLETE_FDT;
+ }
+ Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion);
+ }
+
+ // Go through the list and add the reserved region to the Device Tree
+ if (!EFI_ERROR(Status)) {
+ MemoryMapPtr = MemoryMap;
+ for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++) {
+ if (IsLinuxReservedRegion ((EFI_MEMORY_TYPE)MemoryMapPtr->Type)) {
+ DEBUG((DEBUG_VERBOSE, "Reserved region of type %d [0x%lX, 0x%lX]\n",
+ MemoryMapPtr->Type,
+ (UINTN)MemoryMapPtr->PhysicalStart,
+ (UINTN)(MemoryMapPtr->PhysicalStart + MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE)));
+ err = fdt_add_mem_rsv(fdt, MemoryMapPtr->PhysicalStart, MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE);
+ if (err != 0) {
+ Print(L"Warning: Fail to add 'memreserve' (err:%d)\n", err);
+ }
+ }
+ MemoryMapPtr = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + DescriptorSize);
+ }
+ }
+
+ //
+ // Setup Arm Mpcore Info if it is a multi-core or multi-cluster platforms.
+ //
+ // For 'cpus' and 'cpu' device tree nodes bindings, refer to this file
+ // in the kernel documentation:
+ // Documentation/devicetree/bindings/arm/cpus.txt
+ //
+ Status = gBS->LocateProtocol (
+ &gAmdMpCoreInfoProtocolGuid,
+ NULL,
+ (VOID **)&AmdMpCoreInfoProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ // Get pointer to ARM core info table
+ ArmCoreInfoTable = AmdMpCoreInfoProtocol->GetArmCoreInfoTable (&ArmCoreCount);
+ ASSERT (ArmCoreInfoTable != NULL);
+ ASSERT (ArmCoreCount <= NUM_CORES);
+
+ // Get Id from primary CPU
+ MpId = (UINTN) ArmReadMpidr ();
+ PrimaryClusterId = GET_CLUSTER_ID((UINT32) MpId);
+ PrimaryCoreId = GET_CORE_ID((UINT32) MpId);
+
+ // Remove existing 'pmu' node and create a new one
+ pmu_node = fdt_subnode_offset (fdt, 0, "pmu");
+ if (pmu_node >= 0) {
+ fdt_del_node (fdt, pmu_node);
+ }
+ pmu_node = fdt_add_subnode(fdt, 0, "pmu");
+ if (pmu_node >= 0) {
+ // append PMU interrupts
+ for (Index = 0; Index < ArmCoreCount; Index++) {
+ MpId = (UINTN) GET_MPID (ArmCoreInfoTable[Index].ClusterId,
+ ArmCoreInfoTable[Index].CoreId);
+
+ Status = AmdMpCoreInfoProtocol->GetPmuSpiFromMpId (MpId, &PmuInt.IntId);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "FDT: Error getting PMU interrupt for MpId '0x%x'\n", MpId));
+ goto FAIL_COMPLETE_FDT;
+ }
+
+ PmuInt.Flag = cpu_to_fdt32(PMU_INT_FLAG_SPI);
+ PmuInt.IntId = cpu_to_fdt32(PmuInt.IntId);
+ PmuInt.Type = cpu_to_fdt32(PMU_INT_TYPE_HIGH_LEVEL);
+ fdt_appendprop(fdt, pmu_node, "interrupts", &PmuInt, sizeof(PmuInt));
+ }
+ fdt_setprop_string(fdt, pmu_node, "compatible", "arm,armv8-pmuv3");
+ } else {
+ DEBUG((EFI_D_ERROR,"FDT: Error creating 'pmu' node\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+
+ // Remove existing 'psci' node if feature not supported
+ node = fdt_subnode_offset (fdt, 0, "psci");
+ if (node >= 0) {
+ if (!FixedPcdGetBool (PcdPsciOsSupport)) {
+ fdt_del_node (fdt, node);
+ }
+ } else if (FixedPcdGetBool (PcdPsciOsSupport) &&
+ FixedPcdGetBool (PcdTrustedFWSupport)) {
+ // Add 'psci' node if not present
+ node = fdt_add_subnode(fdt, 0, "psci");
+ if (node >= 0) {
+ fdt_setprop_string(fdt, node, "compatible", "arm,psci-0.2");
+ fdt_appendprop_string(fdt, node, "compatible", "arm,psci");
+ fdt_setprop_string(fdt, node, "method", "smc");
+ } else {
+ DEBUG((EFI_D_ERROR,"FDT: Error creating 'psci' node\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+ }
+
+ // Remove existing 'cpus' node and create a new one
+ node = fdt_subnode_offset (fdt, 0, "cpus");
+ if (node >= 0) {
+ fdt_del_node (fdt, node);
+ }
+ node = fdt_add_subnode(fdt, 0, "cpus");
+ if (node >= 0) {
+ // Configure the 'cpus' node
+ fdt_setprop_string(fdt, node, "name", "cpus");
+ fdt_setprop_cell (fdt, node, "#address-cells", sizeof (UINTN) / 4);
+ fdt_setprop_cell(fdt, node, "#size-cells", 0);
+ } else {
+ DEBUG((EFI_D_ERROR,"FDT: Error creating 'cpus' node\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+
+ //
+ // Walk the processor table in reverse order for proper listing in FDT
+ //
+ Index = ArmCoreCount;
+ while (Index--) {
+ // Create 'cpu' node
+ AsciiSPrint (Name, sizeof(Name), "CPU%d", Index);
+ cpu_node = fdt_add_subnode (fdt, node, Name);
+ if (cpu_node < 0) {
+ DEBUG ((EFI_D_ERROR, "FDT: Error on creating '%a' node\n", Name));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+ phandle[Index] = fdt_alloc_phandle(fdt);
+ fdt_setprop_cell (fdt, cpu_node, "phandle", phandle[Index]);
+ fdt_setprop_cell (fdt, cpu_node, "linux,phandle", phandle[Index]);
+
+ if (FixedPcdGetBool (PcdPsciOsSupport) &&
+ FixedPcdGetBool (PcdTrustedFWSupport)) {
+ fdt_setprop_string(fdt, cpu_node, "enable-method", "psci");
+ } else {
+ fdt_setprop_string(fdt, cpu_node, "enable-method", "spin-table");
+ MbAddr = ArmCoreInfoTable[Index].MailboxSetAddress;
+ MbAddr = cpu_to_fdtn (MbAddr);
+ fdt_setprop (fdt, cpu_node, "cpu-release-addr", &MbAddr, sizeof (MbAddr));
+ }
+ MpId = (UINTN) GET_MPID (ArmCoreInfoTable[Index].ClusterId,
+ ArmCoreInfoTable[Index].CoreId);
+ MpId = cpu_to_fdtn (MpId);
+ fdt_setprop (fdt, cpu_node, "reg", &MpId, sizeof (MpId));
+ fdt_setprop_string(fdt, cpu_node, "compatible", "arm,armv8");
+ fdt_setprop_string (fdt, cpu_node, "device_type", "cpu");
+
+ // If it is not the primary core than the cpu should be disabled
+ if (((ArmCoreInfoTable[Index].ClusterId != PrimaryClusterId) ||
+ (ArmCoreInfoTable[Index].CoreId != PrimaryCoreId))) {
+ fdt_setprop_string(fdt, cpu_node, "status", "disabled");
+ }
+ }
+
+ // Remove existing 'cpu-map' node and create a new one
+ map_node = fdt_subnode_offset (fdt, node, "cpu-map");
+ if (map_node >= 0) {
+ fdt_del_node (fdt, map_node);
+ }
+ map_node = fdt_add_subnode(fdt, node, "cpu-map");
+ if (map_node >= 0) {
+ ClusterIndex = ArmCoreCount - 1;
+ ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable,
+ ArmCoreCount);
+ while (ClusterCount--) {
+ // Create 'cluster' node
+ AsciiSPrint (Name, sizeof(Name), "cluster%d", ClusterCount);
+ cluster_node = fdt_add_subnode (fdt, map_node, Name);
+ if (cluster_node < 0) {
+ DEBUG ((EFI_D_ERROR, "FDT: Error creating '%a' node\n", Name));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+
+ ClusterId = ArmCoreInfoTable[ClusterIndex].ClusterId;
+ CoreIndex = ClusterIndex;
+ CoresInCluster = NumberOfCoresInCluster (ArmCoreInfoTable,
+ ArmCoreCount,
+ ClusterId);
+ while (CoresInCluster--) {
+ // Create 'core' node
+ AsciiSPrint (Name, sizeof(Name), "core%d", CoresInCluster);
+ cpu_node = fdt_add_subnode (fdt, cluster_node, Name);
+ if (cpu_node < 0) {
+ DEBUG ((EFI_D_ERROR, "FDT: Error creating '%a' node\n", Name));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+ fdt_setprop_cell (fdt, cpu_node, "cpu", phandle[CoreIndex]);
+
+ // iterate to next core in cluster
+ if (CoresInCluster) {
+ do {
+ --CoreIndex;
+ } while (ClusterId != ArmCoreInfoTable[CoreIndex].ClusterId);
+ }
+ }
+
+ // iterate to next cluster
+ if (ClusterCount) {
+ do {
+ --ClusterIndex;
+ } while (ClusterInRange (ArmCoreInfoTable,
+ ArmCoreInfoTable[ClusterIndex].ClusterId,
+ ClusterIndex + 1,
+ ArmCoreCount - 1));
+ }
+ }
+ } else {
+ DEBUG((EFI_D_ERROR,"FDT: Error creating 'cpu-map' node\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto FAIL_COMPLETE_FDT;
+ }
+
+ SetSocIdStatus (fdt);
+ SetXgbeStatus (fdt);
+
+ DEBUG_CODE_BEGIN();
+ // DebugDumpFdt (fdt);
+ DEBUG_CODE_END();
+
+ // If we succeeded to generate the new Device Tree then free the old Device Tree
+ gBS->FreePages (*FdtBlobBase, EFI_SIZE_TO_PAGES (*FdtBlobSize));
+
+ // Update the real size of the Device Tree
+ fdt_pack ((VOID*)(UINTN)(NewFdtBlobBase));
+
+ *FdtBlobBase = NewFdtBlobBase;
+ *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(NewFdtBlobBase));
+ return EFI_SUCCESS;
+
+FAIL_COMPLETE_FDT:
+ gBS->FreePages (NewFdtBlobAllocation, EFI_SIZE_TO_PAGES (NewFdtBlobSize));
+
+FAIL_RELOCATE_FDT:
+ *FdtBlobSize = (UINTN)fdt_totalsize ((VOID*)(UINTN)(*FdtBlobBase));
+ // Return success even if we failed to update the FDT blob.
+ // The original one is still valid.
+ return EFI_SUCCESS;
+}
+
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.c b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.c new file mode 100644 index 0000000..09d650d --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.c @@ -0,0 +1,274 @@ +/** @file
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "FdtDxe.h"
+
+extern EFI_BOOT_SERVICES *gBS;
+
+EFI_EVENT mFdtReadyToBootEvent;
+
+VOID
+EFIAPI
+FdtReadyToBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+EFI_STATUS
+EFIAPI
+FdtOverrideDevicePath(
+ IN CHAR16 *FdtFileName,
+ OUT EFI_DEVICE_PATH **FdtDevicePath
+ );
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ * FdtDxeEntryPoint
+ *
+ * Description:
+ * Entry point of the FDT Runtime Driver.
+ *
+ * Control flow:
+ * Configure reserved regions.
+ *
+ * Parameters:
+ * @param[in] ImageHandle The firmware allocate handle for the
+ * EFI image.
+ * @param[in] *SystemTable Pointer to the EFI System Table.
+ *
+ * @return EFI_STATUS
+ *
+ *------------------------------------------------------------------------------------
+ **/
+EFI_STATUS
+EFIAPI
+FdtDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_ERROR, "FdtDxe Loaded\n"));
+
+ //
+ // Ready-To-Boot callback
+ //
+ Status = EfiCreateEventReadyToBootEx(
+ TPL_CALLBACK,
+ FdtReadyToBoot,
+ NULL,
+ &mFdtReadyToBootEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ * FdtReadyToBoot
+ *
+ * Description:
+ * Ready-2-Boot Event Callback for EFI_EVENT_SIGNAL_READY_TO_BOOT.
+ *
+ * Control flow:
+ * 1. Read FDT blob
+ * 2. Edit FDT table
+ * 3. Submit FDT to EFI system table
+ *
+ * Parameters:
+ * @param[in] Event EFI_EVENT notification.
+ * @param[in] *Context Pointer to the Event Context.
+ *
+ * @return VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+EFIAPI
+FdtReadyToBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ EFI_STATUS Status;
+ UINT32 AuthenticationStatus;
+ EFI_GUID *FdtGuid = FixedPcdGetPtr(PcdStyxFdt);
+ UINT8 *FdtBlobBase = NULL;
+ UINTN FdtBlobSize = 0;
+ EFI_DEVICE_PATH *FdtDevicePath;
+
+ // Search for FDT blob in EFI partition
+ Status = FdtOverrideDevicePath(L"fdt.dtb", &FdtDevicePath);
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "%a: Loading Override FDT blob...\n", __FUNCTION__));
+
+ FdtBlobBase = (UINT8 *)(UINTN)LINUX_FDT_MAX_OFFSET;
+ Status = BdsLoadImage (FdtDevicePath,
+ AllocateMaxAddress,
+ (EFI_PHYSICAL_ADDRESS *)&FdtBlobBase,
+ &FdtBlobSize);
+ if (!EFI_ERROR (Status) && FdtBlobBase && FdtBlobSize)
+ goto LOAD_FDT_BLOB;
+ else
+ goto LOAD_FDT_ERROR;
+ }
+
+ DEBUG ((EFI_D_ERROR, "%a: Loading Embedded FDT blob...\n", __FUNCTION__));
+ HandleBuffer = NULL;
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &FvProtocol
+ );
+ if (!EFI_ERROR (Status)) {
+ Status = FvProtocol->ReadSection (
+ FvProtocol,
+ FdtGuid,
+ EFI_SECTION_RAW,
+ 0,
+ (VOID **)&FdtBlobBase,
+ &FdtBlobSize,
+ &AuthenticationStatus
+ );
+ if (!EFI_ERROR (Status) && FdtBlobBase && FdtBlobSize)
+ goto LOAD_FDT_BLOB;
+ }
+ }
+
+LOAD_FDT_ERROR:
+ DEBUG ((EFI_D_ERROR, "%a: Error loading FDT blob!\n", __FUNCTION__));
+ goto LOAD_FDT_DONE;
+
+LOAD_FDT_BLOB:
+ Status = AmdStyxPrepareFdt(NULL, 0, 0, (EFI_PHYSICAL_ADDRESS *)&FdtBlobBase, &FdtBlobSize);
+ ASSERT_EFI_ERROR (Status);
+
+ // Install the FDT blob into EFI system configuration table
+ Status = gBS->InstallConfigurationTable (&gFdtTableGuid, (VOID *)FdtBlobBase);
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((EFI_D_ERROR, "%a: FDT ready!\n", __FUNCTION__));
+
+LOAD_FDT_DONE:
+ gBS->CloseEvent (mFdtReadyToBootEvent);
+ return;
+}
+
+/**
+*---------------------------------------------------------------------------------------
+*
+* FdtOverrideDevicePath
+*
+* Description:
+* Looks for a user-provided FDT blob to override the default file built with the UEFI image.
+*
+* Parameters:
+* @param[in] FdtFileName Name of the FDT blob located in the EFI partition.
+* @param[out] FdtDevicePath EFI Device Path of the FDT blob.
+*
+* @return EFI_SUCCESS The function completed successfully.
+* @return EFI_NOT_FOUND The protocol could not be located.
+* @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+*
+*---------------------------------------------------------------------------------------
+**/
+EFI_STATUS
+EFIAPI
+FdtOverrideDevicePath(
+ IN CHAR16 *FdtFileName,
+ OUT EFI_DEVICE_PATH **FdtDevicePath
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *DevPathProtocol;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ EFI_STATUS Status;
+ CHAR16 *DevPathText;
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *VolProtocol;
+ EFI_FILE_PROTOCOL *FileProtocol;
+ EFI_FILE_PROTOCOL *FileHandle;
+ CHAR16 FilePathText[120];
+
+ HandleBuffer = NULL;
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiSimpleFileSystemProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer);
+ if (EFI_ERROR (Status))
+ return Status;
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ DevPathProtocol = NULL;
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiDevicePathProtocolGuid,
+ (VOID **) &DevPathProtocol);
+
+ if (!EFI_ERROR (Status)) {
+ VolProtocol = NULL;
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiSimpleFileSystemProtocolGuid,
+ (VOID **) &VolProtocol);
+
+ if (!EFI_ERROR (Status)) {
+ FileProtocol = NULL;
+ Status = VolProtocol->OpenVolume(VolProtocol, &FileProtocol);
+
+ if (!EFI_ERROR (Status)) {
+ FileHandle = NULL;
+ Status = FileProtocol->Open(FileProtocol,
+ &FileHandle,
+ FdtFileName,
+ EFI_FILE_MODE_READ,
+ 0);
+
+ if (!EFI_ERROR (Status)) {
+ FileProtocol->Close(FileHandle);
+ DevPathText = ConvertDevicePathToText(DevPathProtocol, TRUE, FALSE);
+ StrCpy(FilePathText, DevPathText);
+ StrCat(FilePathText, L"/");
+ StrCat(FilePathText, FdtFileName);
+ *FdtDevicePath = ConvertTextToDevicePath (FilePathText);
+ return EFI_SUCCESS;
+ }
+ }
+ }
+ }
+ }
+
+ return Status;
+}
+
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.h b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.h new file mode 100644 index 0000000..c61b7ec --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.h @@ -0,0 +1,54 @@ +/** @file
+
+ Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __FDT_DXE__H_
+#define __FDT_DXE__H_
+
+#include <Uefi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BdsLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Guid/DxeServices.h>
+#include <Library/DxeServicesTableLib.h>
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/LoadFile.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/DevicePathFromText.h>
+
+#define LINUX_FDT_MAX_OFFSET (PcdGet64 (PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))
+
+VOID
+EFIAPI
+AmdStyxParkSecondaryCores(
+ VOID
+ );
+
+EFI_STATUS
+AmdStyxPrepareFdt (
+ IN CONST CHAR8* CommandLineArguments,
+ IN EFI_PHYSICAL_ADDRESS InitrdImage,
+ IN UINTN InitrdImageSize,
+ IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
+ IN OUT UINTN *FdtBlobSize
+ );
+
+
+#endif // __FDT_DXE__H_
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.inf b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.inf new file mode 100644 index 0000000..43f084d --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.inf @@ -0,0 +1,75 @@ +#/* @file
+#
+# Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FdtDxe
+ FILE_GUID = 17f50855-6484-4b56-814b-1a88702d88e1
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = FdtDxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+#
+
+[Sources.common]
+ FdtDxe.c
+ BdsLinuxFdt.c
+ LinuxLoaderHelper.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AmdModulePkg/AmdModulePkg.dec
+ OpenPlatformPkg/Platforms/AMD/Styx/AmdStyx.dec
+ ShellPkg/ShellPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ DxeServicesTableLib
+ BdsLib
+ FdtLib
+ PcdLib
+ DevicePathLib
+
+[Guids]
+ gEfiEventReadyToBootGuid ## CONSUMED
+ gEfiDxeServicesTableGuid ## CONSUMED
+ gFdtTableGuid ## CONSUMED
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMED
+ gAmdMpCoreInfoProtocolGuid ## CONSUMED
+
+[Pcd]
+ gAmdStyxTokenSpaceGuid.PcdStyxFdt
+ gAmdStyxTokenSpaceGuid.PcdSocCpuId
+ gAmdStyxTokenSpaceGuid.PcdEthMacA
+ gAmdStyxTokenSpaceGuid.PcdEthMacB
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset
+ gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport
+ gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport
+
+[Depex]
+ TRUE
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoader.h b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoader.h new file mode 100644 index 0000000..ff6c72c --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoader.h @@ -0,0 +1,173 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+
+ Derived from:
+ ArmPkg/Library/BdsLib/LinuxLoader.h
+
+**/
+
+#ifndef __LINUX_LOADER_H__
+#define __LINUX_LOADER_H__
+
+#include <Library/BdsLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ShellLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/EfiShellParameters.h>
+#include <Protocol/EfiShell.h>
+
+#include <libfdt.h>
+
+//
+// Definitions
+//
+
+#define MAX_MSG_LEN 80
+
+#define LINUX_UIMAGE_SIGNATURE 0x56190527
+#define LINUX_KERNEL_MAX_OFFSET (SystemMemoryBase + PcdGet32(PcdArmLinuxKernelMaxOffset))
+#define LINUX_ATAG_MAX_OFFSET (SystemMemoryBase + PcdGet32(PcdArmLinuxAtagMaxOffset))
+#define LINUX_FDT_MAX_OFFSET (SystemMemoryBase + PcdGet32(PcdArmLinuxFdtMaxOffset))
+
+#define ARM_FDT_MACHINE_TYPE 0xFFFFFFFF
+
+// Additional size that could be used for FDT entries added by the UEFI OS Loader
+// Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes)
+// + system memory region (20bytes) + mp_core entries (200 bytes)
+#define FDT_ADDITIONAL_ENTRIES_SIZE 0x300
+
+//
+// Global variables
+//
+extern CONST EFI_GUID mLinuxLoaderHiiGuid;
+extern EFI_HANDLE mLinuxLoaderHiiHandle;
+
+//
+// Local Types
+//
+typedef struct _SYSTEM_MEMORY_RESOURCE {
+ LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
+ EFI_PHYSICAL_ADDRESS PhysicalStart;
+ UINT64 ResourceLength;
+} SYSTEM_MEMORY_RESOURCE;
+
+typedef VOID (*LINUX_KERNEL)(UINT32 Zero, UINT32 Arch, UINTN ParametersBase);
+
+//
+// Functions
+//
+EFI_STATUS
+PrintHii (
+ IN CONST CHAR8 *Language OPTIONAL,
+ IN CONST EFI_STRING_ID HiiFormatStringId,
+ ...
+ );
+
+VOID
+PrintHelp (
+ IN CONST CHAR8 *Language OPTIONAL
+ );
+
+EFI_STATUS
+ProcessShellParameters (
+ OUT CHAR16 **KernelPath,
+ OUT CHAR16 **FdtPath,
+ OUT CHAR16 **InitrdPath,
+ OUT CHAR16 **LinuxCommandLine,
+ OUT UINTN *AtagMachineType
+ );
+
+EFI_STATUS
+ProcessAppCommandLine (
+ OUT CHAR16 **KernelTextDevicePath,
+ OUT CHAR16 **FdtTextDevicePath,
+ OUT CHAR16 **InitrdTextDevicePath,
+ OUT CHAR16 **LinuxCommandLine,
+ OUT UINTN *AtagMachineType
+ );
+
+VOID
+PrintPerformance (
+ VOID
+ );
+
+EFI_STATUS
+GetSystemMemoryResources (
+ IN LIST_ENTRY *ResourceList
+ );
+
+EFI_STATUS
+PrepareFdt (
+ IN EFI_PHYSICAL_ADDRESS SystemMemoryBase,
+ IN CONST CHAR8* CommandLineArguments,
+ IN EFI_PHYSICAL_ADDRESS InitrdImage,
+ IN UINTN InitrdImageSize,
+ IN OUT EFI_PHYSICAL_ADDRESS *FdtBlobBase,
+ IN OUT UINTN *FdtBlobSize
+ );
+
+/**
+ Start a Linux kernel from a Device Path
+
+ @param SystemMemoryBase Base of the system memory
+ @param LinuxKernel Device Path to the Linux Kernel
+ @param Parameters Linux kernel arguments
+ @param Fdt Device Path to the Flat Device Tree
+ @param MachineType ARM machine type value
+
+ @retval EFI_SUCCESS All drivers have been connected
+ @retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
+ @retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
+ @retval RETURN_UNSUPPORTED ATAG is not support by this architecture
+
+**/
+EFI_STATUS
+BootLinuxAtag (
+ IN EFI_PHYSICAL_ADDRESS SystemMemoryBase,
+ IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
+ IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
+ IN CONST CHAR8* CommandLineArguments,
+ IN UINTN MachineType
+ );
+
+/**
+ Start a Linux kernel from a Device Path
+
+ @param[in] LinuxKernelDevicePath Device Path to the Linux Kernel
+ @param[in] InitrdDevicePath Device Path to the Initrd
+ @param[in] Arguments Linux kernel arguments
+
+ @retval EFI_SUCCESS All drivers have been connected
+ @retval EFI_NOT_FOUND The Linux kernel Device Path has not been found
+ @retval EFI_OUT_OF_RESOURCES There is not enough resource memory to store the matching results.
+
+**/
+EFI_STATUS
+BootLinuxFdt (
+ IN EFI_PHYSICAL_ADDRESS SystemMemoryBase,
+ IN EFI_DEVICE_PATH_PROTOCOL* LinuxKernelDevicePath,
+ IN EFI_DEVICE_PATH_PROTOCOL* InitrdDevicePath,
+ IN EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath,
+ IN CONST CHAR8* Arguments
+ );
+
+#endif /* __LINUX_LOADER_H__ */
diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoaderHelper.c b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoaderHelper.c new file mode 100644 index 0000000..80dce8d --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/LinuxLoaderHelper.c @@ -0,0 +1,200 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+/**
+
+ Derived from:
+ ArmPkg/Application/LinuxLoader/LinuxLoaderHelper.c
+
+**/
+
+
+#include <PiDxe.h>
+#include <Library/HobLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "LinuxLoader.h"
+
+STATIC CONST CHAR8 *mTokenList[] = {
+ /*"SEC",*/
+ "PEI",
+ "DXE",
+ "BDS",
+ NULL
+};
+
+VOID
+PrintPerformance (
+ VOID
+ )
+{
+ UINTN Key;
+ CONST VOID *Handle;
+ CONST CHAR8 *Token, *Module;
+ UINT64 Start, Stop, TimeStamp;
+ UINT64 Delta, TicksPerSecond, Milliseconds;
+ UINTN Index;
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ BOOLEAN CountUp;
+
+ TicksPerSecond = GetPerformanceCounterProperties (&Start, &Stop);
+ if (Start < Stop) {
+ CountUp = TRUE;
+ } else {
+ CountUp = FALSE;
+ }
+
+ TimeStamp = 0;
+ Key = 0;
+ do {
+ Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop);
+ if (Key != 0) {
+ for (Index = 0; mTokenList[Index] != NULL; Index++) {
+ if (AsciiStriCmp (mTokenList[Index], Token) == 0) {
+ Delta = CountUp ? (Stop - Start) : (Start - Stop);
+ TimeStamp += Delta;
+ Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL);
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "%6a %6ld ms\n", Token, Milliseconds);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ break;
+ }
+ }
+ }
+ } while (Key != 0);
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Total Time = %ld ms\n\n",
+ DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL));
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+}
+
+STATIC
+EFI_STATUS
+InsertSystemMemoryResources (
+ LIST_ENTRY *ResourceList,
+ EFI_HOB_RESOURCE_DESCRIPTOR *ResHob
+ )
+{
+ SYSTEM_MEMORY_RESOURCE *NewResource;
+ LIST_ENTRY *Link;
+ LIST_ENTRY *NextLink;
+ LIST_ENTRY AttachedResources;
+ SYSTEM_MEMORY_RESOURCE *Resource;
+ EFI_PHYSICAL_ADDRESS NewResourceEnd;
+
+ if (IsListEmpty (ResourceList)) {
+ NewResource = AllocateZeroPool (sizeof (SYSTEM_MEMORY_RESOURCE));
+ NewResource->PhysicalStart = ResHob->PhysicalStart;
+ NewResource->ResourceLength = ResHob->ResourceLength;
+ InsertTailList (ResourceList, &NewResource->Link);
+ return EFI_SUCCESS;
+ }
+
+ InitializeListHead (&AttachedResources);
+
+ Link = ResourceList->ForwardLink;
+ ASSERT (Link != NULL);
+ while (Link != ResourceList) {
+ Resource = (SYSTEM_MEMORY_RESOURCE*)Link;
+
+ // Sanity Check. The resources should not overlapped.
+ ASSERT (!((ResHob->PhysicalStart >= Resource->PhysicalStart) && (ResHob->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))));
+ ASSERT (!((ResHob->PhysicalStart + ResHob->ResourceLength - 1 >= Resource->PhysicalStart) &&
+ ((ResHob->PhysicalStart + ResHob->ResourceLength - 1) < (Resource->PhysicalStart + Resource->ResourceLength))));
+
+ // The new resource is attached after this resource descriptor
+ if (ResHob->PhysicalStart == Resource->PhysicalStart + Resource->ResourceLength) {
+ Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
+
+ NextLink = RemoveEntryList (&Resource->Link);
+ InsertTailList (&AttachedResources, &Resource->Link);
+ Link = NextLink;
+ }
+ // The new resource is attached before this resource descriptor
+ else if (ResHob->PhysicalStart + ResHob->ResourceLength == Resource->PhysicalStart) {
+ Resource->PhysicalStart = ResHob->PhysicalStart;
+ Resource->ResourceLength = Resource->ResourceLength + ResHob->ResourceLength;
+
+ NextLink = RemoveEntryList (&Resource->Link);
+ InsertTailList (&AttachedResources, &Resource->Link);
+ Link = NextLink;
+ } else {
+ Link = Link->ForwardLink;
+ }
+ }
+
+ if (!IsListEmpty (&AttachedResources)) {
+ // See if we can merge the attached resource with other resources
+
+ NewResource = (SYSTEM_MEMORY_RESOURCE*)GetFirstNode (&AttachedResources);
+ Link = RemoveEntryList (&NewResource->Link);
+ while (!IsListEmpty (&AttachedResources)) {
+ // Merge resources
+ Resource = (SYSTEM_MEMORY_RESOURCE*)Link;
+
+ // Ensure they overlap each other
+ ASSERT (
+ ((NewResource->PhysicalStart >= Resource->PhysicalStart) && (NewResource->PhysicalStart < (Resource->PhysicalStart + Resource->ResourceLength))) ||
+ (((NewResource->PhysicalStart + NewResource->ResourceLength) >= Resource->PhysicalStart) && ((NewResource->PhysicalStart + NewResource->ResourceLength) < (Resource->PhysicalStart + Resource->ResourceLength)))
+ );
+
+ NewResourceEnd = MAX (NewResource->PhysicalStart + NewResource->ResourceLength, Resource->PhysicalStart + Resource->ResourceLength);
+ NewResource->PhysicalStart = MIN (NewResource->PhysicalStart, Resource->PhysicalStart);
+ NewResource->ResourceLength = NewResourceEnd - NewResource->PhysicalStart;
+
+ Link = RemoveEntryList (Link);
+ }
+ } else {
+ // None of the Resource of the list is attached to this ResHob. Create a new entry for it
+ NewResource = AllocateZeroPool (sizeof (SYSTEM_MEMORY_RESOURCE));
+ NewResource->PhysicalStart = ResHob->PhysicalStart;
+ NewResource->ResourceLength = ResHob->ResourceLength;
+ }
+ InsertTailList (ResourceList, &NewResource->Link);
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetSystemMemoryResources (
+ IN LIST_ENTRY *ResourceList
+ )
+{
+ EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
+
+ InitializeListHead (ResourceList);
+
+ // Find the first System Memory Resource Descriptor
+ ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
+ while ((ResHob != NULL) && (ResHob->ResourceType != EFI_RESOURCE_SYSTEM_MEMORY)) {
+ ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+ }
+
+ // Did not find any
+ if (ResHob == NULL) {
+ return EFI_NOT_FOUND;
+ } else {
+ InsertSystemMemoryResources (ResourceList, ResHob);
+ }
+
+ ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+ while (ResHob != NULL) {
+ if (ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
+ InsertSystemMemoryResources (ResourceList, ResHob);
+ }
+ ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc new file mode 100644 index 0000000..c73bd55 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -0,0 +1,719 @@ +#
+# Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may
+# be found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+
+DEFINE DO_XGBE = 1
+DEFINE NUM_CORES = 8
+DEFINE DO_PSCI = 1
+DEFINE DO_ISCP = 1
+DEFINE DO_KCS = 1
+
+ PLATFORM_NAME = Overdrive
+ PLATFORM_GUID = B2296C02-9DA1-4CD1-BD48-4D4F0F1276EB
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/Overdrive
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ #
+ # Allow dynamic PCDs
+ #
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
+ # 1/123 faster than Stm or Vstm version
+ #BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
+ ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+ # ARM PL011 UART Driver
+ PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+ #
+ # PCI support
+ #
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciHostBridgeLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.inf
+
+ #
+ # Styx specific libraries
+ #
+ AmdSataInit|AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf
+ AmdStyxAcpiLib|OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiTables.inf
+ EfiResetSystemLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf
+ RealTimeClockLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+ ArmPlatformSecLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxSecLib/AmdStyxSecLib.inf
+ ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf
+
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
+ MemoryInitPeiLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[LibraryClasses.AARCH64]
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+###################################################################################################
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process.
+###################################################################################################
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ *_*_*_ASL_FLAGS = -tc -li -l -so
+ *_*_*_ASLPP_FLAGS = -x c -E -P $(ARCHCC_FLAGS)
+ *_*_*_ASLCC_FLAGS = -x c $(ARCHCC_FLAGS)
+
+ GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+ GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64
+
+ GCC:*_*_AARCH64_PLATFORM_FLAGS = -I$(BIN_DIR)/OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml/OUTPUT
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ # All pages are cached by default
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle
+ ## created by ConsplitterDxe. It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD Seattle"
+
+ # Number of configured cores
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES)
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800
+
+ # Declare system memory base
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ #
+ # ARM PrimeCell
+ #
+
+ ## PL011 - Serial Terminal (Atlas UART)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0E1010000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ # serial port is clocked at 100MHz
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|100000000
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0E1010000
+ gAmdStyxTokenSpaceGuid.PcdUartDbgBaudRate|115200
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0xE1110000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000
+
+ #
+ # Bitmask for ports implemented on the SATA controller
+ # (enabling 4 ports by default: 00001111b)
+ #
+ gAmdStyxTokenSpaceGuid.PcdSataPi|0x0F
+
+ # PCIe Support
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
+
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0
+ gArmTokenSpaceGuid.PcdPciBusMax|0xFF
+
+ gArmTokenSpaceGuid.PcdPciIoBase|0x1000
+ gArmTokenSpaceGuid.PcdPciIoSize|0xF000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFFF0000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x40000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x80000000
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
+
+ ## Use PCI emulation for ATA PassThru
+ # gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE
+
+ ## ACPI (no tables < 4GB)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+!if $(DO_PSCI)
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE
+!else
+ gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE
+!endif
+
+!if $(DO_ISCP)
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE
+!else
+ gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE
+!endif
+
+ # SMBIOS 3.0 only
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
+ gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000
+ gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000
+
+!if $(DO_XGBE)
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|TRUE
+
+ gAmdModulePkgTokenSpaceGuid.PcdPort0PhyMode|0
+ gAmdModulePkgTokenSpaceGuid.PcdPort1PhyMode|0
+ gAmdModulePkgTokenSpaceGuid.PcdPort0NetSpeed|1
+ gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1
+
+[PcdsDynamicDefault.common]
+ gAmdStyxTokenSpaceGuid.PcdEthMacA|0x02A1A2A3A4A5
+ gAmdStyxTokenSpaceGuid.PcdEthMacB|0x02B1B2B3B4B5
+
+[PcdsPatchableInModule]
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|TRUE
+ gAmdModulePkgTokenSpaceGuid.PcdXgbeRev|2
+!endif
+
+[PcdsPatchableInModule]
+# PCIe Configuration: x4x4
+ gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1
+ gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE
+
+[PcdsDynamicDefault.common]
+ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0400000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0
+
+[PcdsDynamicExHii.common.DEFAULT]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # PEI Phase modules
+ #
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ AmdModulePkg/Iscp/IscpPei.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ #
+ # Console IO support
+ #
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.inf {
+ <LibraryClasses>
+ # deprecated BdsLib from the ARM BDS
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ }
+
+ #
+ # PCI support
+ #
+ AmdModulePkg/Gionb/Gionb.inf
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+ #
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+ #
+ # AHCI Support
+ #
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataControllerDxe.inf
+
+ #
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!if $(DO_XGBE)
+ #
+ # SNP support
+ #
+ AmdModulePkg/SnpDxe/SnpDxePort0.inf
+ AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+ }
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf new file mode 100644 index 0000000..04894d5 --- /dev/null +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf @@ -0,0 +1,405 @@ +#
+# Copyright (c) 2014 - 2016, AMD Incorporated. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.STYX_ROM]
+BaseAddress = 0x8000C80000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00500000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x500
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+FILE = OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/Binary/PreUefiFirmware.bin
+
+0x00200000|0x00260000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = STYX_EFI
+
+!include OpenPlatformPkg/Platforms/AMD/Styx/Common/Varstore.fdf.inc
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Environment Variables Protocol
+ #
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSpiFvDxe/StyxSpiFvDxe.inf
+
+ #
+ # Iscp support
+ #
+ INF AmdModulePkg/Iscp/IscpDxe.inf
+
+ #
+ # FDT support
+ #
+ INF OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtDxe/FdtDxe.inf
+
+ FILE FREEFORM = PCD(gAmdStyxTokenSpaceGuid.PcdStyxFdt) {
+ SECTION RAW = OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb
+ }
+
+ #
+ # PCI support
+ #
+ INF AmdModulePkg/Gionb/Gionb.inf
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
+ # AHCI Support
+ #
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/SataControllerDxe/SataControllerDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!if $(DO_XGBE)
+ #
+ # SNP support
+ #
+ INF AmdModulePkg/SnpDxe/SnpDxePort0.inf
+ INF AmdModulePkg/SnpDxe/SnpDxePort1.inf
+!endif
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+## Bug https://bugs.linaro.org/show_bug.cgi?id=2239
+# INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ #
+ # Core Info
+ #
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf
+
+ #
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE OpenPlatformPkg/Platforms/AMD/Styx/AcpiTables/AcpiAml.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+ #
+ # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table]
+ #
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+ #
+ # Crypto Accelerator support (RNG only)
+ #
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxRngDxe/StyxRngDxe.inf
+
+[FV.STYX_EFI]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF AmdModulePkg/Iscp/IscpPei.inf
+ INF OpenPlatformPkg/Platforms/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.Binary]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ TE TE Align = Auto |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.Binary]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
+
|