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2015-02-26OP-TEE BenchmarkHEADmasterJames Kung
- Print CNTVCT value for smc call performance measurement - Enable/disable trace performance by CFG_TEE_TRACE_PERFORMANCE option in mk/config.mk - Fix compile warning message issue that will happen when compiling libutee and change log level to 0 - Add new tee implemented property "ext.tee.arm.genericTimerInfo" to get generic timer info for secure system call perforamnce analysis - Rename tee_time_arm_cntpct.c to tee_time_arm_generic_timer.c - Update .travis.yml to test CFG_TEE_TRACE_PERFORMANCE=y and CFG_TEE_TA_LOG_LEVEL=0 - Add new crypto abstraction API for base64 encode/decode function Signed-off-by: James Kung <kong1191@gmail.com> Tested-by: James Kung <kong1191@gmail.com> (QEMU, FVP)
2015-02-26arm32: move some inline assembly into arm32.hJens Wiklander
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
2015-02-26struct tee_ta_ctx: remove rw_data*Jens Wiklander
Removes rw_data and tw_data_usage elements in struct tee_ta_ctx as they are not used any longer. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-02-23arm32: Adds LPAE supportJens Wiklander
Enables use of Large Physical Address Extension (LPAE) with CFG_WITH_LPAE=y To facilitate both the old V7 and the new LPAE translation tables an abstraction layer has been added to avoid direct manipulations of the translation tables. Both V7 and LPAE implementation uses TEX remapping (SCTLR.TRE = 1) and enables access flags (SCTLR.AFE = 1). This is a change in the V7 code base as those bits where 0 before. There are two reason for this change: 1."From the introduction of the Large Physical Address Extension, ARM deprecates any use of the AP[2:0] scheme for defining MMU access permissions. This deprecation applies to software for all ARMv7-A implementations, regardless of whether they include the Large Physical Address Extension." 2. With SCTLR.TRE = 1 and SCTLR.AFE = 1 V7 and LPAE implementations uses the same way of specifying access permissions and memory attributes. Currently only supported on plat-vexpress. Bugfix v7 config: sets NOS bit in TTBRx registers Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP Base model) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2015-02-17[plat-stm] fix/disable cache FullZeroLineWrite supportetienne carriere
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com> Tested-by: Pascal BRAND <pascal.brand@st.com> Reviewed-by: Pascal BRAND <pascal.brand@st.com> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2015-02-12Internal API extension on Cache OperationsPascal Brand
Following extensions are introduced: - TEE_CacheClean() - TEE_CacheFlush() - TEE_CacheInvalidate() Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Signed-off-by: Pascal Brand <pascal.brand@st.com>
2015-02-04Fix user TA trace issueJean-Michel Delorme
Definition of the global "trace_level" variable has been moved from the libutil to a TA file (user_ta_header.c). This allows to initialize it with the correct value/level CFG_TEE_TA_LOG_LEVEL when the TA code is compiled. Same trace level is now applied at all TA code and associated libraries: libutee/libutils/libmpa. Change-Id: Id6bda7f0611f78fe7ad3ee6b61193f4b80aba94d Signed-off-by: Jean-Michel Delorme <jean-michel.delorme@st.com> Reviewed-on: https://gerrit.st.com/22472 Reviewed-by: Emmanuel MICHEL <emmanuel.michel@st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2015-02-02arm32 pager: remove unused functionsJens Wiklander
Removes unused tee_pager_unhide_all_pages() and tee_pager_unmap() Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-01-30core/arm32: support PL310 lockdown at TEE bootetienne carriere
Add routine arm_cl2_lockgit allways() that enable lock on all d/i ways. Add config switch CFG_PL310_LOCKED. If set, at TEE boot, PL310 L2 cache is fully locked and invalidated. Once TZ as booted, NSec inherits from a pre-configured L2 cache, pre-enable, but bypassed as all ways are locked. If NSec wants to benefit from L2 cache, it shall unlock all d/i ways. Default setup: CFG_PL310_LOCKED is not defined. Linux may not integrate the outercache unlock sequence at l2x0 inits. Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Reviewed-on: https://gerrit.st.com/17088 Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com> Tested-by: Pascal BRAND <pascal.brand@st.com> Reviewed-by: Pascal BRAND <pascal.brand@st.com> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2015-01-30[plat-stm] cache_maintenance_l2() performed on given areaPascal Brand
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2015-01-30Refactored version of cache_maintenance_l2() functionsPascal Brand
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Pascal Brand <pascal.brand@st.com>
2015-01-23Disable TEX Remap before enable MMUSY Chiu
- Add write_ats1cpw() and read_par() for page description debug - Clear TEX bit beofre enable MMU Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU) Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2015-01-23sunxi: fix parallel build errorsJerome Forissier
Fixes https://github.com/OP-TEE/optee_os/issues/181. plat-sunxi/link.mk uses CPP to generate its core linker script. Commit a3911433960a ("core: get value of CFG_ variables directly from generated/conf.h") has modified the core CPP flags to include conf.h automatically, so one must make sure that this file exists when the linker script is generated. This is done by adding a dependency on $(conf-file). The vexpress platforms also lack the dependency, but the bug won't show because of other dependencies which cause conf.h to be generated anyways. PLATFORM=stm is fine because it does not use CPP. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2015-01-23SE API: Change configuration to be prefixed with CFG_*SY Chiu
Signed-off-by: SY Chiu <sy.chiu@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
2015-01-23SE API: hide private interfacesSY Chiu
- Split each headers into module.h and module_priv.h, move the methods that is only used internally by SE implementation to module_priv.h, and export module_priv.h to rest of TEE Core - Added new include path to se_api_self_tests.c for which needs to include private headers - Split aid.c and apdu.c from iso7816.c. Originally they have to be wriiten in the same file since they share some private data structures. Now, the private data structure can be shared via private headers. - Split reader.c from manager.c for the same reason above. Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
2015-01-23SE API: implment lubutee and svc handlerSY Chiu
- Implemented tee_se_service - Rename tee_se_reader_handle to tee_se_reader_proxy to avoid confuse with libutee - Implemented SE API(tee_internal_se_api.h) in libutee - Implemented svc handler for SE API - rename protocol.[ch] to iso7816.[ch] - prefix aid_* with "tee_se_" - add an option to enable/disable se_api_self_tests Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
2015-01-23SE API: Session, Protocol and Channel implementationSY Chiu
- Implement Session which maintains the connection between TA and a specific SE Reader - Implement ISO7816 transport layer protocol, and Channel management - Implement Utilities to handle AID(ISO7816-3) and APDU(ISO7816-4) - Brunch of self tests to velidate functionality of each module Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
2015-01-23SE API: SE Manager and Reader implementationSY Chiu
- Introduce an interface for developers to write reader driver (core/include/tee/se/reader/interface.h) - A sample reader driver implementation: PC/SC passthru reader (core/tee/se/reader/passthru_reader) - Currently supported machine is qemu-virt (compile with --with-pcsc-passthru) - A selftest STA is included to test the functionality of SE Reader (core/arch/arm32/sta/se_api_self_tests.c) - To enable SE API, add "WITH_SE_API := y" in your platform config Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)
2015-01-23Introduce a Linux style initcall mechanismSY Chiu
To use it, simply add something like: service_init(server_init_callback); The callback regsitered will be invoked at the end of init_teecore(). Now we have 2 priority service_init and driver_init. The callback regsitered in service level will be invoked first. Signed-off-by: SY Chiu <sy.chiu@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)
2015-01-19SHA-1 ARMv8 crypto extension implementationJens Wiklander
* Adds a ARMv8 crypto extension based SHA-1 implementation for LTC. * Crypto extension based SHA-1 implementation is enabled for plat-vexpress-juno. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2015-01-19SHA-256 ARMv8 crypto extension implementationJens Wiklander
* Adds a ARMv8 crypto extension based SHA-256 implementation for LTC. * Crypto extension based SHA-256 implementation is enabled for plat-vexpress-juno. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-01-19arm32: support for VFP/NEON operations.Jens Wiklander
CFG_WITH_VFP=y enables use of VFP/NEON by context switching VFP state on demand. plat-vexpress: specific initialization of CPACR to allow CP10 and CP11 access to allow usage of VFP/NEON operations. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-01-19plat-vexpress: config nsacrJens Wiklander
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-01-16Add plat-sunxisunny
Initial version support for Allwinner A80 platform. Allwinner A80 is big.little archtecture with 4*A7 + 4*A15, Support Trustzone tech and secureboot inside hardware. plat-sunxi support features: 1.Clone plat-sunxi from plat-vexpress; 2.Secure bootloader reserved 64MB secure DRAM for optee_os; 3.Support SMP secondary cpu secure stage bootup; 4.Add uart driver to core/driver/*; 5.Support GIC driver initialization. The porting work test on Optimus board, with allwinner A80 chip. Signed-off-by: sunny <sunny@allwinnertech.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2015-01-05ta_dev_kit.mk: get platform-specific flags from platform_flags.mkJerome Forissier
Platform-specific flags that apply to user-mode code are moved from from core/arch/$(ARCH)/plat-$(PLATFORM)/conf.mk to a new file: core/arch/$(ARCH)/plat-$(PLATFORM)/platform_flags.mk. This file is used by ta/mk/ta_dev_kit.mk so that the Trusted Applications are built with the same flags used when building the user-mode TEE code. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2015-01-05core: get value of CFG_ variables directly from generated/conf.hJerome Forissier
Add a '-include' preprocessor flag to the command line so that all TEE core files include generated/conf.h automatically. Then, there is no need to define macros via the command line (-DCFG_XYZ=...). This commit also fixes a compile error when CFG_TEE_CORE_EMBED_INTERNAL_TESTS=0. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2014-12-18Align plat-stm and plat-vexpress versions of core_bootcfg.cPascal Brand
Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2014-12-18plat-stm: move memory definition in platform_config.hPascal Brand
Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2014-12-18plat-stm: rename memory definition namePascal Brand
Rename following memory area definition name, according to the one used in vexpress: CFG_DDR_START into DRAM0_BASE CFG_DDR_SIZE into DRAM0_SIZE CFG_DDR1_START into DRAM1_BASE CFG_DDR1_SIZE into DRAM1_SIZE CFG_DDR_ARM_ARMTZ_START into CFG_SHMEM_START CFG_DDR_ARM_ARMTZ_SIZE into CFG_SHMEM_SIZE CFG_DDR_ARMTZ_ONLY_START into TZDRAM_BASE CFG_DDR_ARMTZ_ONLY_SIZE into TZDRAM_SIZE Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2014-12-18plat-stm: make stacks cache line alignedJens Wiklander
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2014-12-18arm32: remove memmap_notinit bookkeepingJens Wiklander
Removes the bookkeeping of whether memory map has been initialized or not using the memmap_notinit variable. Memory map is always initialized before any core_va2pa() or core_pa2va() is performed so the bookkeeping doesn't do much good. The variable was updated with caches disabled while other CPUs might have caches enabled. This can result in unexpected problems. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno) Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-18plat-vexpress: make stacks cache line alignedJens Wiklander
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-16arm32: paging of TEE Core optionally enabledJens Wiklander
plat-vexpress-*: * Optionally enable paging with CFG_WITH_PAGER=y * Uses fake SRAM when paging is enabled * Supports partitioning OP-TEE binary in unpaged, init and pagable areas plat-stm: * Displays an error message if compiled with CFG_WITH_PAGER=y arm32: * Replaces legacy paging support with new paging support * Removes unused tee_pager_unpg.c Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform - Check the code without the pager is not broken).
2014-12-16plat-vexpress: linking supports pagable tee.binJens Wiklander
* Adds scripts to create a pagable tee.bin * Updates link script and link.mk to support pagable tee.bin * Binary format of tee.bin is changed from a raw format to a header followed by the binary data as described by the header. This requires updates in ARM-TF OP-TEE Dispatcher and QEMU virt bios. fvp: * Changes OP-TEE load address to start of TZDRAM_BASE Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-16plat-vexpress: Clean D-cache on reset_primary exitJens Wiklander
Cleans and invalidates D-cache when primary CPU has initialized and is ready to exit to normal world. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-12arm32: clear junk in UL1 tableJens Wiklander
Clears junk in UL1 translation table when setting mapping for a TA in tee_mmu_set_ctx(). Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt)
2014-12-12plat-stm: separate sectionsJens Wiklander
Puts functions and data into separate sections Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2014-12-12plat-vexpress: separate sectionsJens Wiklander
Puts functions and data into separate sections Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt and FVP) Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-12arm32: assembly routines in separate sectionsJens Wiklander
Moves some assembly routines into separate sections. This helps the garbage collecting with the linker when separating what's must be unpaged from the rest of the code. The garbage collector in the linker works on dependencies between sections. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-12tee_mm: remove legacy TEE_MM_POOL_PAGED defineJens Wiklander
Removes the legacy TEE_MM_POOL_PAGED define and unsused code associated with it. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-12plat-vexpress: reorganize boot for pagingJens Wiklander
Reorganizes the boot functions to keep primary and secondary boot path more separated as a preparation for the pager. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-12arm32: move call to teecore_init_ta_ram()Jens Wiklander
Moves call to teecore_init_ta_ram() from init_teecore() to be called directly from platform initialization routines. It's needed later when the pager allocates secure DDR to store that backing pages. We don't want to call init_teecore() until the pager is fully initialized because init_teecore() pulls in many dependencies. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-12plat-vexpress: clean memory configurationJens Wiklander
* Cleans the memory configuration for plat-vexpress to make it easier to add fake and real SRAM. * Uses common functions to check if a buffer intersects or is inside a memory area * Increases number of cores from 4 to 8 for FVP flavor to support Base model better. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-12arm32: make all TLB invalidations inner sharableJens Wiklander
* Makes all TLB invalidations inner sharable * Removes deprecated TLB invalidations Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-11arm32: split and enhance core_init_mmu()Jens Wiklander
* Splits core_init_mmu() into two functions, core_init_mmu_tables() called by primary CPU to create the translation tables and core_init_mmu_regs() called by each CPU to initialize MMU register settings. * Adds option to map certain areas in a level 2 translation table instead of only level 1 mapping. Allocation of the level 2 translation tables is implemented in platform specific code, a weak function is provided in case the platform doesn't implement/need the function. * Adds L2 translation table for STM and Vexpress. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt platform)
2014-12-11arm32: add thread_init_per_cpu()Jens Wiklander
Adds a thread_init_per_cpu() function that should be called instead of thread_init_handlers() by the secondary CPUs. The primary CPU should first call thread_init_handlers() and then thread_init_per_cpu(). Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-11merge tee_pager*.c and tee_pager*.h filesJens Wiklander
* Merges tee_pager_unpg.c and tee_pager.c into tee_pager.c * Merges tee_pager_unpg.h and tee_pager.h into tee_pager.h * Removes some legacy dummy macros * Replaces some while(1) with panic() Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
2014-12-09core/arm32: add traces in case of user TA abortEtienne Carriere
TA manager and TA mmu layer have specific trace handlers for TA aborts: - dumping TA info. - dumping TA mapping info. Generic helper uuid2str(). Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
2014-12-09Cosmetics fixesPascal Brand
Signed-off-by: Pascal Brand <pascal.brand@st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2014-11-28Fix compile errors for core_self_tests.cJens Wiklander
* Fixes compile errors when compiling core_self_tests.c with debug prints * Reduces allocation and alignment sizes in memalign() tests to work with a smaller heap. * Checks that returned buffers has required alignment Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt and FVP) Reviewed-by: Pascal Brand <pascal.brand@linaro.org> Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
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