diff options
| author | SY Chiu <sy.chiu@linaro.org> | 2015-01-14 14:26:06 +0800 |
|---|---|---|
| committer | SY Chiu <sy.chiu@linaro.org> | 2015-01-23 21:24:38 +0800 |
| commit | 090e207477d574978d2e7f5ebf2e27e7f94c122f (patch) | |
| tree | 5daf4064183743ac5c986b0d5838b87b8079b1c9 /core/arch/arm32 | |
| parent | 313ead476a7106eb7b92643086b1a5cff0f3b099 (diff) | |
Disable TEX Remap before enable MMU
- Add write_ats1cpw() and read_par() for page description debug
- Clear TEX bit beofre enable MMU
Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Diffstat (limited to 'core/arch/arm32')
| -rw-r--r-- | core/arch/arm32/include/arm32.h | 17 | ||||
| -rw-r--r-- | core/arch/arm32/mm/core_mmu.c | 9 |
2 files changed, 26 insertions, 0 deletions
diff --git a/core/arch/arm32/include/arm32.h b/core/arch/arm32/include/arm32.h index 583180e..a556451 100644 --- a/core/arch/arm32/include/arm32.h +++ b/core/arch/arm32/include/arm32.h @@ -183,6 +183,23 @@ static inline uint32_t read_ttbr0(void) return ttbr0; } +static inline void write_ats1cpw(uint32_t va) +{ + asm volatile ("mcr p15, 0, %[va], c7, c8, 1" + : : [va] "r" (va) + ); +} + +static inline uint32_t read_par(void) +{ + uint32_t par; + + asm volatile ("mrc p15, 0, %[par], c7, c4, 0" + : [par] "=r" (par) + ); + return par; +} + static inline void write_ttbr1(uint32_t ttbr1) { asm volatile ("mcr p15, 0, %[ttbr1], c2, c0, 1" diff --git a/core/arch/arm32/mm/core_mmu.c b/core/arch/arm32/mm/core_mmu.c index dfdea5c..76b9d3c 100644 --- a/core/arch/arm32/mm/core_mmu.c +++ b/core/arch/arm32/mm/core_mmu.c @@ -343,6 +343,7 @@ void core_init_mmu_tables(void) void core_init_mmu_regs(void) { + uint32_t sctlr; paddr_t ttb_pa = core_mmu_get_main_ttb_pa(); /* @@ -354,6 +355,14 @@ void core_init_mmu_regs(void) DACR_DOMAIN(1, DACR_DOMAIN_PERM_CLIENT)); /* + * Disable TEX Remap + * (This allows TEX field in page table entry take affect) + */ + sctlr = read_sctlr(); + sctlr &= ~SCTLR_TRE; + write_sctlr(sctlr); + + /* * Enable lookups using TTBR0 and TTBR1 with the split of addresses * defined by TEE_MMU_TTBCR_N_VALUE. */ |