diff options
34 files changed, 4 insertions, 240 deletions
diff --git a/core/arch/arm/kernel/cache_helpers_a32.S b/core/arch/arm/kernel/cache_helpers_a32.S index b26f0520..50180dce 100644 --- a/core/arch/arm/kernel/cache_helpers_a32.S +++ b/core/arch/arm/kernel/cache_helpers_a32.S @@ -50,9 +50,7 @@ loop_\reg: * ------------------------------------------ */ FUNC dcache_cleaninv_range , : -UNWIND( .fnstart) do_dcache_maintenance_by_mva dccimvac -UNWIND( .fnend) END_FUNC dcache_cleaninv_range /* ------------------------------------------ @@ -61,9 +59,7 @@ END_FUNC dcache_cleaninv_range * ------------------------------------------ */ FUNC dcache_clean_range , : -UNWIND( .fnstart) do_dcache_maintenance_by_mva dccmvac -UNWIND( .fnend) END_FUNC dcache_clean_range /* ------------------------------------------ @@ -72,9 +68,7 @@ END_FUNC dcache_clean_range * ------------------------------------------ */ FUNC dcache_inv_range , : -UNWIND( .fnstart) do_dcache_maintenance_by_mva dcimvac -UNWIND( .fnend) END_FUNC dcache_inv_range @@ -84,9 +78,7 @@ END_FUNC dcache_inv_range * ------------------------------------------ */ FUNC dcache_clean_range_pou , : -UNWIND( .fnstart) do_dcache_maintenance_by_mva dccmvau -UNWIND( .fnend) END_FUNC dcache_clean_range_pou /* ---------------------------------------------------------------- @@ -115,7 +107,6 @@ END_FUNC dcache_clean_range_pou .endm LOCAL_FUNC do_dcsw_op , : -UNWIND( .fnstart) push {r4-r12,lr} adr r11, dcsw_loop_table // compute cache op based on the operation type add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions @@ -166,7 +157,6 @@ dcsw_loop_table: bx lr write_dccsw r0 bx lr -UNWIND( .fnend) END_FUNC do_dcsw_op /* --------------------------------------------------------------- @@ -178,9 +168,7 @@ END_FUNC do_dcsw_op * --------------------------------------------------------------- */ FUNC dcache_op_louis , : -UNWIND( .fnstart) dcsw_op #CLIDR_LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #CSSELR_LEVEL_SHIFT -UNWIND( .fnend) END_FUNC dcache_op_louis /* --------------------------------------------------------------- @@ -192,9 +180,7 @@ END_FUNC dcache_op_louis * --------------------------------------------------------------- */ FUNC dcache_op_all , : -UNWIND( .fnstart) dcsw_op #CLIDR_LOC_SHIFT, #CLIDR_FIELD_WIDTH, #CSSELR_LEVEL_SHIFT -UNWIND( .fnend) END_FUNC dcache_op_all @@ -219,9 +205,7 @@ END_FUNC dcache_op_all * --------------------------------------------------------------- */ FUNC dcache_op_level1 , : -UNWIND( .fnstart) dcsw_op_level #(1 << CSSELR_LEVEL_SHIFT) -UNWIND( .fnend) END_FUNC dcache_op_level1 /* --------------------------------------------------------------- @@ -233,9 +217,7 @@ END_FUNC dcache_op_level1 * --------------------------------------------------------------- */ FUNC dcache_op_level2 , : -UNWIND( .fnstart) dcsw_op_level #(2 << CSSELR_LEVEL_SHIFT) -UNWIND( .fnend) END_FUNC dcache_op_level2 /* --------------------------------------------------------------- @@ -247,13 +229,10 @@ END_FUNC dcache_op_level2 * --------------------------------------------------------------- */ FUNC dcache_op_level3 , : -UNWIND( .fnstart) dcsw_op_level #(3 << CSSELR_LEVEL_SHIFT) -UNWIND( .fnend) END_FUNC dcache_op_level3 FUNC icache_inv_all , : -UNWIND( .fnstart) /* Invalidate Entire Instruction Cache (and branch predictors) */ write_icialluis @@ -261,7 +240,6 @@ UNWIND( .fnstart) isb /* by the instructions rigth after the isb */ bx lr -UNWIND( .fnend) END_FUNC icache_inv_all /* ------------------------------------------ @@ -270,7 +248,6 @@ END_FUNC icache_inv_all * ------------------------------------------ */ FUNC icache_inv_range , : -UNWIND( .fnstart) icache_line_size r2, r3 add r1, r0, r1 sub r3, r2, #1 @@ -288,5 +265,4 @@ loop_ic_inv: isb bx lr -UNWIND( .fnend) END_FUNC icache_inv_range diff --git a/core/arch/arm/kernel/entry_a32.S b/core/arch/arm/kernel/entry_a32.S index 459488f6..d2988496 100644 --- a/core/arch/arm/kernel/entry_a32.S +++ b/core/arch/arm/kernel/entry_a32.S @@ -33,7 +33,6 @@ panic_boot_file: * void assert_flat_mapped_range(uint32_t vaddr, uint32_t line) */ LOCAL_FUNC __assert_flat_mapped_range , : -UNWIND( .fnstart) UNWIND( .cantunwind) push { r4-r6, lr } mov r4, r0 @@ -56,7 +55,6 @@ UNWIND( .cantunwind) bl __do_panic b . /* should NOT return */ 1: pop { r4-r6, pc } -UNWIND( .fnend) END_FUNC __assert_flat_mapped_range /* panic if mmu is enable and vaddr != paddr (scratch lr) */ @@ -68,9 +66,7 @@ END_FUNC __assert_flat_mapped_range #endif /* CFG_PL310 */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) bx lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early DECLARE_KEEP_PAGER plat_cpu_reset_early .weak plat_cpu_reset_early @@ -221,7 +217,6 @@ END_FUNC reset_vect_table .endm FUNC _start , : -UNWIND( .fnstart) UNWIND( .cantunwind) bootargs_entry @@ -250,7 +245,6 @@ UNWIND( .cantunwind) beq reset_primary b reset_secondary #endif -UNWIND( .fnend) END_FUNC _start DECLARE_KEEP_INIT _start @@ -346,7 +340,6 @@ DECLARE_KEEP_INIT _start #endif LOCAL_FUNC reset_primary , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) /* preserve r4-r7: bootargs */ @@ -588,7 +581,6 @@ shadow_stack_access_ok: smc #0 b . /* SMC should not return */ #endif /* CFG_CORE_FFA */ -UNWIND( .fnend) END_FUNC reset_primary #ifdef CFG_BOOT_SYNC_CPU @@ -610,10 +602,8 @@ LOCAL_DATA cached_mem_end , : END_DATA cached_mem_end LOCAL_FUNC unhandled_cpu , : -UNWIND( .fnstart) wfi b unhandled_cpu -UNWIND( .fnend) END_FUNC unhandled_cpu #ifdef CFG_CORE_ASLR @@ -800,7 +790,6 @@ END_DATA boot_mmu_config #if defined(CFG_WITH_ARM_TRUSTED_FW) FUNC cpu_on_handler , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) mov r4, r0 mov r5, r1 @@ -827,14 +816,12 @@ UNWIND( .cantunwind) #else bx r6 #endif -UNWIND( .fnend) END_FUNC cpu_on_handler DECLARE_KEEP_PAGER cpu_on_handler #else /* defined(CFG_WITH_ARM_TRUSTED_FW) */ LOCAL_FUNC reset_secondary , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) adr r0, reset_vect_table write_vbar r0 @@ -885,7 +872,6 @@ UNWIND( .cantunwind) mov r4, #0 smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC reset_secondary DECLARE_KEEP_PAGER reset_secondary #endif /* defined(CFG_WITH_ARM_TRUSTED_FW) */ diff --git a/core/arch/arm/kernel/misc_a32.S b/core/arch/arm/kernel/misc_a32.S index 0f4fbcb3..3366ea2d 100644 --- a/core/arch/arm/kernel/misc_a32.S +++ b/core/arch/arm/kernel/misc_a32.S @@ -12,15 +12,12 @@ /* size_t __get_core_pos(void); */ FUNC __get_core_pos , : , .identity_map -UNWIND( .fnstart) read_mpidr r0 b get_core_pos_mpidr -UNWIND( .fnend) END_FUNC __get_core_pos /* size_t get_core_pos_mpidr(uint32_t mpidr); */ FUNC get_core_pos_mpidr , : -UNWIND( .fnstart) mov r3, r0 /* @@ -55,7 +52,6 @@ UNWIND( .fnstart) #endif bx lr -UNWIND( .fnend) END_FUNC get_core_pos_mpidr /* Let platforms override this if needed */ @@ -66,7 +62,6 @@ END_FUNC get_core_pos_mpidr * returns cpsr to be set */ LOCAL_FUNC temp_set_mode , : -UNWIND( .fnstart) mov r1, r0 cmp r1, #CPSR_MODE_USR /* update mode: usr -> sys */ moveq r1, #CPSR_MODE_SYS @@ -75,12 +70,10 @@ UNWIND( .fnstart) bic r0, #CPSR_MODE_MASK /* clear mode */ orr r0, r1 /* set expected mode */ bx lr -UNWIND( .fnend) END_FUNC temp_set_mode /* uint32_t read_mode_sp(int cpu_mode) */ FUNC read_mode_sp , : -UNWIND( .fnstart) push {r4, lr} UNWIND( .save {r4, lr}) mrs r4, cpsr /* save cpsr */ @@ -89,12 +82,10 @@ UNWIND( .save {r4, lr}) mov r0, sp /* get the function result */ msr cpsr, r4 /* back to the old mode */ pop {r4, pc} -UNWIND( .fnend) END_FUNC read_mode_sp /* uint32_t read_mode_lr(int cpu_mode) */ FUNC read_mode_lr , : -UNWIND( .fnstart) push {r4, lr} UNWIND( .save {r4, lr}) mrs r4, cpsr /* save cpsr */ @@ -103,5 +94,4 @@ UNWIND( .save {r4, lr}) mov r0, lr /* get the function result */ msr cpsr, r4 /* back to the old mode */ pop {r4, pc} -UNWIND( .fnend) END_FUNC read_mode_lr diff --git a/core/arch/arm/kernel/spin_lock_a32.S b/core/arch/arm/kernel/spin_lock_a32.S index bed57408..ab9c41b0 100644 --- a/core/arch/arm/kernel/spin_lock_a32.S +++ b/core/arch/arm/kernel/spin_lock_a32.S @@ -37,7 +37,6 @@ /* void __cpu_spin_lock(unsigned int *lock) */ FUNC __cpu_spin_lock , : -UNWIND( .fnstart) mov r2, #SPINLOCK_LOCK 1: ldrex r1, [r0] @@ -48,12 +47,10 @@ UNWIND( .fnstart) bne 1b dmb bx lr -UNWIND( .fnend) END_FUNC __cpu_spin_lock /* int __cpu_spin_trylock(unsigned int *lock) - return 0 on success */ FUNC __cpu_spin_trylock , : -UNWIND( .fnstart) mov r2, #SPINLOCK_LOCK mov r1, r0 1: @@ -69,17 +66,14 @@ UNWIND( .fnstart) clrex dmb bx lr -UNWIND( .fnend) END_FUNC __cpu_spin_trylock /* void __cpu_spin_unlock(unsigned int *lock) */ FUNC __cpu_spin_unlock , : -UNWIND( .fnstart) dmb mov r1, #SPINLOCK_UNLOCK str r1, [r0] dsb sev bx lr -UNWIND( .fnend) END_FUNC __cpu_spin_unlock diff --git a/core/arch/arm/kernel/thread_a32.S b/core/arch/arm/kernel/thread_a32.S index abb9d332..3192a87a 100644 --- a/core/arch/arm/kernel/thread_a32.S +++ b/core/arch/arm/kernel/thread_a32.S @@ -28,52 +28,43 @@ .endm FUNC thread_set_abt_sp , : -UNWIND( .fnstart) UNWIND( .cantunwind) mrs r1, cpsr cps #CPSR_MODE_ABT mov sp, r0 msr cpsr, r1 bx lr -UNWIND( .fnend) END_FUNC thread_set_abt_sp FUNC thread_set_und_sp , : -UNWIND( .fnstart) UNWIND( .cantunwind) mrs r1, cpsr cps #CPSR_MODE_UND mov sp, r0 msr cpsr, r1 bx lr -UNWIND( .fnend) END_FUNC thread_set_und_sp FUNC thread_set_irq_sp , : -UNWIND( .fnstart) UNWIND( .cantunwind) mrs r1, cpsr cps #CPSR_MODE_IRQ mov sp, r0 msr cpsr, r1 bx lr -UNWIND( .fnend) END_FUNC thread_set_irq_sp FUNC thread_set_fiq_sp , : -UNWIND( .fnstart) UNWIND( .cantunwind) mrs r1, cpsr cps #CPSR_MODE_FIQ mov sp, r0 msr cpsr, r1 bx lr -UNWIND( .fnend) END_FUNC thread_set_fiq_sp /* void thread_resume(struct thread_ctx_regs *regs) */ FUNC thread_resume , : -UNWIND( .fnstart) UNWIND( .cantunwind) add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */ @@ -101,7 +92,6 @@ UNWIND( .cantunwind) ldm r0, {r0-r12} movsne pc, lr b eret_to_user_mode -UNWIND( .fnend) END_FUNC thread_resume /* @@ -109,7 +99,6 @@ END_FUNC thread_resume * the banked r8-r12 registers, returns original CPSR. */ LOCAL_FUNC thread_save_state_fiq , : -UNWIND( .fnstart) UNWIND( .cantunwind) mov r9, lr @@ -151,7 +140,6 @@ UNWIND( .cantunwind) mov r0, r8 /* Return original CPSR */ bx r9 -UNWIND( .fnend) END_FUNC thread_save_state_fiq /* @@ -159,7 +147,6 @@ END_FUNC thread_save_state_fiq * CPSR. */ FUNC thread_save_state , : -UNWIND( .fnstart) UNWIND( .cantunwind) push {r12, lr} /* @@ -203,7 +190,6 @@ UNWIND( .cantunwind) mov r0, r5 /* Return original CPSR */ bx lr -UNWIND( .fnend) END_FUNC thread_save_state /* @@ -211,18 +197,14 @@ END_FUNC thread_save_state * unsigned long a2, unsigned long a3) */ FUNC thread_smc , : -UNWIND( .fnstart) smc #0 bx lr -UNWIND( .fnend) END_FUNC thread_smc FUNC thread_init_vbar , : -UNWIND( .fnstart) /* Set vector (VBAR) */ write_vbar r0 bx lr -UNWIND( .fnend) END_FUNC thread_init_vbar DECLARE_KEEP_PAGER thread_init_vbar @@ -268,7 +250,6 @@ DECLARE_KEEP_PAGER thread_init_vbar * This function depends on being called with exceptions masked. */ FUNC __thread_enter_user_mode , : -UNWIND( .fnstart) UNWIND( .cantunwind) /* * Save all registers to allow syscall_return() to resume execution @@ -298,7 +279,6 @@ UNWIND( .cantunwind) ldm r0, {r0-r12} b eret_to_user_mode -UNWIND( .fnend) END_FUNC __thread_enter_user_mode /* @@ -307,7 +287,6 @@ END_FUNC __thread_enter_user_mode * See description in thread.h */ FUNC thread_unwind_user_mode , : -UNWIND( .fnstart) UNWIND( .cantunwind) /* Match push {r1, r2, r4, r5} in thread_enter_user_mode() */ pop {r4-r7} @@ -321,7 +300,6 @@ UNWIND( .cantunwind) /* Match push {r4-r12,lr} in thread_enter_user_mode() */ pop {r4-r12,pc} -UNWIND( .fnend) END_FUNC thread_unwind_user_mode .macro maybe_restore_mapping @@ -539,7 +517,6 @@ END_FUNC thread_unwind_user_mode .align 5 FUNC thread_excp_vect , : -UNWIND( .fnstart) UNWIND( .cantunwind) b . /* Reset */ b __thread_und_handler /* Undefined instruction */ @@ -948,7 +925,6 @@ icache_inv_user_range: * thread_excp_vect_end label. */ .pool -UNWIND( .fnend) .global thread_excp_vect_end thread_excp_vect_end: END_FUNC thread_excp_vect diff --git a/core/arch/arm/kernel/thread_optee_smc_a32.S b/core/arch/arm/kernel/thread_optee_smc_a32.S index 90c241f7..b5dfeb98 100644 --- a/core/arch/arm/kernel/thread_optee_smc_a32.S +++ b/core/arch/arm/kernel/thread_optee_smc_a32.S @@ -35,7 +35,6 @@ .endm FUNC vector_std_smc_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc push {r4-r7} @@ -51,11 +50,9 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_std_smc_entry FUNC vector_fast_smc_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc push {r0-r7} @@ -65,11 +62,9 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_fast_smc_entry FUNC vector_fiq_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc /* Secure Monitor received a FIQ and passed control to us. */ @@ -78,12 +73,10 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_fiq_entry #if defined(CFG_WITH_ARM_TRUSTED_FW) LOCAL_FUNC vector_cpu_on_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) bl cpu_on_handler /* When cpu_on_handler() returns mmu is enabled */ @@ -91,11 +84,9 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_cpu_on_entry LOCAL_FUNC vector_cpu_off_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc bl thread_cpu_off_handler @@ -103,11 +94,9 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_cpu_off_entry LOCAL_FUNC vector_cpu_suspend_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc bl thread_cpu_suspend_handler @@ -115,11 +104,9 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_cpu_suspend_entry LOCAL_FUNC vector_cpu_resume_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc bl thread_cpu_resume_handler @@ -127,11 +114,9 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_RESUME_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_cpu_resume_entry LOCAL_FUNC vector_system_off_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc bl thread_system_off_handler @@ -139,11 +124,9 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_system_off_entry LOCAL_FUNC vector_system_reset_entry , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) readjust_pc bl thread_system_reset_handler @@ -151,7 +134,6 @@ UNWIND( .cantunwind) ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC vector_system_reset_entry /* @@ -163,7 +145,6 @@ END_FUNC vector_system_reset_entry * in layout has to be synced with ARM-TF. */ FUNC thread_vector_table , : , .identity_map -UNWIND( .fnstart) UNWIND( .cantunwind) b vector_std_smc_entry b vector_fast_smc_entry @@ -174,13 +155,11 @@ UNWIND( .cantunwind) b vector_fiq_entry b vector_system_off_entry b vector_system_reset_entry -UNWIND( .fnend) END_FUNC thread_vector_table DECLARE_KEEP_PAGER thread_vector_table #endif /*if defined(CFG_WITH_ARM_TRUSTED_FW)*/ FUNC thread_std_smc_entry , : -UNWIND( .fnstart) UNWIND( .cantunwind) bl __thread_std_smc_entry mov r4, r0 /* Save return value for later */ @@ -199,12 +178,10 @@ UNWIND( .cantunwind) mov r4, #0 smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC thread_std_smc_entry /* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ FUNC thread_rpc , : -UNWIND( .fnstart) push {r0, lr} UNWIND( .save {r0, lr}) @@ -241,7 +218,6 @@ UNWIND( .save {r0, lr}) pop {r12, lr} /* Get pointer to rv[] */ stm r12, {r0-r3} /* Store r0-r3 into rv[] */ bx lr -UNWIND( .fnend) END_FUNC thread_rpc DECLARE_KEEP_PAGER thread_rpc diff --git a/core/arch/arm/kernel/thread_spmc_a32.S b/core/arch/arm/kernel/thread_spmc_a32.S index 42525dbc..4be601d1 100644 --- a/core/arch/arm/kernel/thread_spmc_a32.S +++ b/core/arch/arm/kernel/thread_spmc_a32.S @@ -48,7 +48,6 @@ LOCAL_FUNC ffa_msg_send_direct_resp , : END_FUNC ffa_msg_send_direct_resp FUNC thread_std_smc_entry , : -UNWIND( .fnstart) UNWIND( .cantunwind) ror r4, r0, #16 /* Save target info with src and dst swapped */ @@ -69,12 +68,10 @@ UNWIND( .cantunwind) mov r6, #FFA_PARAM_MBZ /* Unused parameter */ mov r7, #FFA_PARAM_MBZ /* Unused parameter */ b ffa_msg_send_direct_resp -UNWIND( .fnend) END_FUNC thread_std_smc_entry /* void thread_rpc(struct thread_rpc_arg *rpc_arg) */ FUNC thread_rpc , : -UNWIND( .fnstart) push {r0, lr} UNWIND( .save {r0, lr}) @@ -112,7 +109,6 @@ UNWIND( .save {r0, lr}) pop {r12, lr} /* Get pointer to rv[] */ stm r12, {r0-r3} /* Store r0-r3 into rv[] */ bx lr -UNWIND( .fnend) END_FUNC thread_rpc DECLARE_KEEP_PAGER thread_rpc diff --git a/core/arch/arm/kernel/tlb_helpers_a32.S b/core/arch/arm/kernel/tlb_helpers_a32.S index ab132610..e65384c9 100644 --- a/core/arch/arm/kernel/tlb_helpers_a32.S +++ b/core/arch/arm/kernel/tlb_helpers_a32.S @@ -9,29 +9,24 @@ /* void tlbi_all(void); */ FUNC tlbi_all , : -UNWIND( .fnstart) dsb ishst /* Sync with table update */ write_tlbiallis /* Invalidate TLBs */ dsb ish /* Sync with tlb invalidation completion */ isb /* Sync execution on tlb update */ bx lr -UNWIND( .fnend) END_FUNC tlbi_all /* void tlbi_mva_allasid(vaddr_t mva); */ FUNC tlbi_mva_allasid , : -UNWIND( .fnstart) dsb ishst /* Sync with table update */ write_tlbimvaais r0 /* Inval TLB by MVA all ASID Inner Sharable */ dsb ish /* Sync with tlb invalidation completion */ isb /* Sync execution on tlb update */ bx lr -UNWIND( .fnend) END_FUNC tlbi_mva_allasid /* void tlbi_asid(unsigned long asid); */ FUNC tlbi_asid , : -UNWIND( .fnstart) dsb ishst /* Sync with table update */ write_tlbiasidis r0 /* Inval unified TLB by ASID Inner Sharable */ orr r0, r0, #1 /* Select the kernel ASID */ @@ -39,5 +34,4 @@ UNWIND( .fnstart) dsb ish /* Sync with tlb invalidation completion */ isb /* Sync execution on tlb update */ bx lr -UNWIND( .fnend) END_FUNC tlbi_asid diff --git a/core/arch/arm/kernel/tz_ssvce_pl310_a32.S b/core/arch/arm/kernel/tz_ssvce_pl310_a32.S index f1d39bd5..b3f85cc1 100644 --- a/core/arch/arm/kernel/tz_ssvce_pl310_a32.S +++ b/core/arch/arm/kernel/tz_ssvce_pl310_a32.S @@ -20,7 +20,6 @@ * lock all L2 caches ways for data and instruction */ FUNC arm_cl2_lockallways , : -UNWIND( .fnstart) add r1, r0, #PL310_DCACHE_LOCKDOWN_BASE ldr r2, [r0, #PL310_AUX_CTRL] tst r2, #PL310_AUX_16WAY_BIT @@ -34,7 +33,6 @@ UNWIND( .fnstart) bne 1b mov pc, lr -UNWIND( .fnend) END_FUNC arm_cl2_lockallways /* @@ -53,7 +51,6 @@ END_FUNC arm_cl2_lockallways * clean & invalidate the whole L2 cache. */ FUNC arm_cl2_cleaninvbyway , : -UNWIND( .fnstart) syncbyway_set_mask r1 str r1, [r0, #PL310_FLUSH_BY_WAY] @@ -87,12 +84,10 @@ loop_cli_sync_done: bne loop_cli_sync_done mov pc, lr -UNWIND( .fnend) END_FUNC arm_cl2_cleaninvbyway /* void arm_cl2_invbyway(vaddr_t base) */ FUNC arm_cl2_invbyway , : -UNWIND( .fnstart) syncbyway_set_mask r1 str r1, [r0, #PL310_INV_BY_WAY] @@ -117,12 +112,10 @@ loop_inv_way_sync_done: bne loop_inv_way_sync_done mov pc, lr -UNWIND( .fnend) END_FUNC arm_cl2_invbyway /* void arm_cl2_cleanbyway(vaddr_t base) */ FUNC arm_cl2_cleanbyway , : -UNWIND( .fnstart) syncbyway_set_mask r1 str r1, [r0, #PL310_CLEAN_BY_WAY] @@ -147,7 +140,6 @@ loop_cl_way_sync_done: bne loop_cl_way_sync_done mov pc, lr -UNWIND( .fnend) END_FUNC arm_cl2_cleanbyway /* @@ -156,7 +148,6 @@ END_FUNC arm_cl2_cleanbyway * pl310value is one of PL310_CLEAN_BY_PA, PL310_INV_BY_PA or PL310_FLUSH_BY_PA */ LOCAL_FUNC _arm_cl2_xxxbypa , : -UNWIND( .fnstart) /* Align start address on PL310 line size */ and r1, #(~(PL310_LINE_SIZE - 1)) #ifdef SCU_BASE @@ -202,7 +193,6 @@ loop_xxx_pa_sync_done: bne loop_xxx_pa_sync_done mov pc, lr -UNWIND( .fnend) END_FUNC _arm_cl2_xxxbypa /* @@ -210,10 +200,8 @@ END_FUNC _arm_cl2_xxxbypa * clean L2 cache by physical address range. */ FUNC arm_cl2_cleanbypa , : -UNWIND( .fnstart) mov r3, #PL310_CLEAN_BY_PA b _arm_cl2_xxxbypa -UNWIND( .fnend) END_FUNC arm_cl2_cleanbypa /* @@ -221,10 +209,8 @@ END_FUNC arm_cl2_cleanbypa * invalidate L2 cache by physical address range. */ FUNC arm_cl2_invbypa , : -UNWIND( .fnstart) mov r3, #PL310_INV_BY_PA b _arm_cl2_xxxbypa -UNWIND( .fnend) END_FUNC arm_cl2_invbypa /* @@ -232,9 +218,7 @@ END_FUNC arm_cl2_invbypa * clean and invalidate L2 cache by physical address range. */ FUNC arm_cl2_cleaninvbypa , : -UNWIND( .fnstart) mov r3, #PL310_FLUSH_BY_PA b _arm_cl2_xxxbypa -UNWIND( .fnend) END_FUNC arm_cl2_cleaninvbypa diff --git a/core/arch/arm/kernel/vfp_a32.S b/core/arch/arm/kernel/vfp_a32.S index ded0125f..00a55e17 100644 --- a/core/arch/arm/kernel/vfp_a32.S +++ b/core/arch/arm/kernel/vfp_a32.S @@ -9,50 +9,38 @@ /* void vfp_save_extension_regs(uint64_t regs[VFP_NUM_REGS]); */ FUNC vfp_save_extension_regs , : -UNWIND( .fnstart) vstm r0!, {d0-d15} vstm r0, {d16-d31} bx lr -UNWIND( .fnend) END_FUNC vfp_save_extension_regs /* void vfp_restore_extension_regs(uint64_t regs[VFP_NUM_REGS]); */ FUNC vfp_restore_extension_regs , : -UNWIND( .fnstart) vldm r0!, {d0-d15} vldm r0, {d16-d31} bx lr -UNWIND( .fnend) END_FUNC vfp_restore_extension_regs /* void vfp_write_fpexc(uint32_t fpexc) */ FUNC vfp_write_fpexc , : -UNWIND( .fnstart) vmsr fpexc, r0 bx lr -UNWIND( .fnend) END_FUNC vfp_write_fpexc /* uint32_t vfp_read_fpexc(void) */ FUNC vfp_read_fpexc , : -UNWIND( .fnstart) vmrs r0, fpexc bx lr -UNWIND( .fnend) END_FUNC vfp_read_fpexc /* void vfp_write_fpscr(uint32_t fpscr) */ FUNC vfp_write_fpscr , : -UNWIND( .fnstart) vmsr fpscr, r0 bx lr -UNWIND( .fnend) END_FUNC vfp_write_fpscr /* uint32_t vfp_read_fpscr(void) */ FUNC vfp_read_fpscr , : -UNWIND( .fnstart) vmrs r0, fpscr bx lr -UNWIND( .fnend) END_FUNC vfp_read_fpscr diff --git a/core/arch/arm/plat-hisilicon/hi3519av100_plat_init.S b/core/arch/arm/plat-hisilicon/hi3519av100_plat_init.S index 8857a01d..bf116453 100644 --- a/core/arch/arm/plat-hisilicon/hi3519av100_plat_init.S +++ b/core/arch/arm/plat-hisilicon/hi3519av100_plat_init.S @@ -33,7 +33,6 @@ * Trap CPU in case of error. */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) /* * Write the CPU Extended Control Register * Set the SMPEN bit, this Cortex-A53 core's register @@ -82,5 +81,4 @@ UNWIND( .fnstart) str r1, [r0] out: bx lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-imx/a7_plat_init.S b/core/arch/arm/plat-imx/a7_plat_init.S index 50c72fee..f96a18ac 100644 --- a/core/arch/arm/plat-imx/a7_plat_init.S +++ b/core/arch/arm/plat-imx/a7_plat_init.S @@ -31,8 +31,6 @@ * Trap CPU in case of error. */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) - /* * DDI: Disable dual issue [bit28=0] * DDVM: Disable Distributed Virtual Memory transactions [bit15=0] @@ -49,13 +47,10 @@ UNWIND( .fnstart) write_nsacr r0 bx lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early FUNC get_core_pos_mpidr , : -UNWIND( .fnstart) /* Drop ClusterId. There is no SoCs with more than 4 A7 Cores. */ and r0, r0, #MPIDR_CPU_MASK bx lr -UNWIND( .fnend) END_FUNC get_core_pos_mpidr diff --git a/core/arch/arm/plat-imx/a9_plat_init.S b/core/arch/arm/plat-imx/a9_plat_init.S index 137fb270..4050684c 100644 --- a/core/arch/arm/plat-imx/a9_plat_init.S +++ b/core/arch/arm/plat-imx/a9_plat_init.S @@ -55,8 +55,6 @@ * Trap CPU in case of error. */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) - /* * Under very rare timing circumstances, transition into streaming * mode might create a data corruption @@ -137,5 +135,4 @@ UNWIND( .fnstart) write_pcr r0 mov pc, lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S b/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S index 1f750030..6894be37 100644 --- a/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S +++ b/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S @@ -552,7 +552,6 @@ .extern iram_tlb_phys_addr FUNC imx7d_low_power_idle, : -UNWIND( .fnstart) push {r0 - r12} /* get necessary info from pm_info */ @@ -727,8 +726,6 @@ wakeup_skip_lpi_flow: /* Restore registers */ bx lr - -UNWIND( .fnend) END_FUNC imx7d_low_power_idle /* @@ -736,7 +733,6 @@ END_FUNC imx7d_low_power_idle * This maybe changed in future. */ FUNC v7_cpu_resume, : -UNWIND( .fnstart) mov r0, #0 @ ; write the cache size selection register to be write_csselr r0 @ ; sure we address the data cache isb @ ; isb to sync the change to the cachesizeid reg @@ -766,5 +762,4 @@ _inv_nextline: blx plat_cpu_reset_early b sm_pm_cpu_resume -UNWIND( .fnend) END_FUNC v7_cpu_resume diff --git a/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S b/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S index 200241fb..06910127 100644 --- a/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S +++ b/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S @@ -455,7 +455,6 @@ .endm FUNC imx7_suspend, : -UNWIND( .fnstart) UNWIND( .cantunwind) push {r4-r12} @@ -656,11 +655,9 @@ dsm_ddr_self_refresh_out: dsm_ddr_retention_out: bx lr -UNWIND( .fnend) END_FUNC imx7_suspend FUNC ca7_cpu_resume, : -UNWIND( .fnstart) UNWIND( .cantunwind) mov r0, #0 @ ; write the cache size selection register to be write_csselr r0 @ ; sure we address the data cache @@ -692,5 +689,4 @@ _inv_nextline: blx plat_cpu_reset_early b sm_pm_cpu_resume -UNWIND( .fnend) END_FUNC ca7_cpu_resume diff --git a/core/arch/arm/plat-ls/plat_init.S b/core/arch/arm/plat-ls/plat_init.S index 64da2bc8..a6350b9c 100644 --- a/core/arch/arm/plat-ls/plat_init.S +++ b/core/arch/arm/plat-ls/plat_init.S @@ -51,8 +51,6 @@ * Trap CPU in case of error. */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) - /* * Disallow NSec to mask FIQ [bit4: FW=0] * Allow NSec to manage Imprecise Abort [bit5: AW=1] @@ -86,5 +84,4 @@ UNWIND( .fnstart) write_nsacr r0 mov pc, lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-rockchip/core_pos_a32.S b/core/arch/arm/plat-rockchip/core_pos_a32.S index e5317214..5994c469 100644 --- a/core/arch/arm/plat-rockchip/core_pos_a32.S +++ b/core/arch/arm/plat-rockchip/core_pos_a32.S @@ -8,13 +8,11 @@ #include <arm32_macros.S> FUNC get_core_pos_mpidr , : -UNWIND( .fnstart) /* * Because mpidr is designed mistake in hardware, ie. core0 is 0xf00, * core1 is 0xf01..., so we need implement the function to correct this. */ and r0, r0, #MPIDR_CPU_MASK bx lr -UNWIND( .fnend) END_FUNC get_core_pos_mpidr diff --git a/core/arch/arm/plat-rockchip/plat_init.S b/core/arch/arm/plat-rockchip/plat_init.S index 6855ee09..fb084afd 100644 --- a/core/arch/arm/plat-rockchip/plat_init.S +++ b/core/arch/arm/plat-rockchip/plat_init.S @@ -8,14 +8,11 @@ #include <arm32_macros.S> FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) /* Enable SMP bit */ read_actlr r0 orr r0, r0, #ACTLR_SMP write_actlr r0 bx lr - -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-rzn1/a7_plat_init.S b/core/arch/arm/plat-rzn1/a7_plat_init.S index 01e35d8f..4f3ae2c3 100644 --- a/core/arch/arm/plat-rzn1/a7_plat_init.S +++ b/core/arch/arm/plat-rzn1/a7_plat_init.S @@ -23,8 +23,6 @@ .code 32 FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) - /* * SCR = 0x00000020 * - FW: Disallow NSec to mask FIQ [bit4=0] @@ -63,5 +61,4 @@ UNWIND( .fnstart) write_nsacr r0 mov pc, lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-stm/tz_a9init.S b/core/arch/arm/plat-stm/tz_a9init.S index c9c84afa..f6b68ba3 100644 --- a/core/arch/arm/plat-stm/tz_a9init.S +++ b/core/arch/arm/plat-stm/tz_a9init.S @@ -26,8 +26,6 @@ * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) */ FUNC arm_cl2_enable , : -UNWIND( .fnstart) - /* Enable PL310 ctrl -> only set lsb bit */ mov r1, #0x1 str r1, [r0, #PL310_CTRL] @@ -40,8 +38,6 @@ UNWIND( .fnstart) write_actlr r0 mov pc, lr - -UNWIND( .fnend) END_FUNC arm_cl2_enable /* @@ -53,8 +49,6 @@ END_FUNC arm_cl2_enable * Trap CPU in case of error. */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) - /* CPSR.A can be modified in any security state. */ mov_imm r0, SCR_AW write_scr r0 @@ -72,7 +66,5 @@ UNWIND( .fnstart) write_pcr r0 mov pc, lr - -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-stm32mp1/reset.S b/core/arch/arm/plat-stm32mp1/reset.S index 3da3593b..8a1ab649 100644 --- a/core/arch/arm/plat-stm32mp1/reset.S +++ b/core/arch/arm/plat-stm32mp1/reset.S @@ -14,7 +14,6 @@ #define STM32MP1_NSACR_PRESERVE_MASK (0xfff << 20) FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) ldr r0, =SCR_SIF write_scr r0 @@ -25,5 +24,4 @@ UNWIND( .fnstart) isb bx lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-sunxi/plat_init.S b/core/arch/arm/plat-sunxi/plat_init.S index 493b98ae..0b347fc2 100644 --- a/core/arch/arm/plat-sunxi/plat_init.S +++ b/core/arch/arm/plat-sunxi/plat_init.S @@ -32,8 +32,6 @@ #include <arm32_macros.S> FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) - /* NSACR configuration */ read_nsacr r0 orr r0, r0, #NSACR_CP10 @@ -47,6 +45,4 @@ UNWIND( .fnstart) write_actlr r0 bx lr - -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/plat-ti/a9_plat_init.S b/core/arch/arm/plat-ti/a9_plat_init.S index 218b2638..087d0b94 100644 --- a/core/arch/arm/plat-ti/a9_plat_init.S +++ b/core/arch/arm/plat-ti/a9_plat_init.S @@ -57,7 +57,6 @@ booted: * Trap CPU in case of error. */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) /* Check if we are resuming */ ldr r3, =booted ldr r2, [r3] @@ -68,11 +67,9 @@ UNWIND( .fnstart) bxeq lr /* Otherwise we are resuming */ b resume_springboard -UNWIND( .fnend) END_FUNC plat_cpu_reset_early LOCAL_FUNC resume_springboard , : -UNWIND( .fnstart) UNWIND( .cantunwind) /* Setup tmp stack */ bl __get_core_pos @@ -112,5 +109,4 @@ after_resume: mov r4, #0 smc #0 b . /* SMC should not return */ -UNWIND( .fnend) END_FUNC resume_springboard diff --git a/core/arch/arm/plat-vexpress/juno_core_pos_a32.S b/core/arch/arm/plat-vexpress/juno_core_pos_a32.S index 41c1efe2..2887172d 100644 --- a/core/arch/arm/plat-vexpress/juno_core_pos_a32.S +++ b/core/arch/arm/plat-vexpress/juno_core_pos_a32.S @@ -9,13 +9,11 @@ /* For Juno number the two A57s as 4 to 5 and A53s as 0 to 3 */ FUNC get_core_pos_mpidr , : -UNWIND( .fnstart) /* Calculate CorePos = ((ClusterId ^ 1) * 4) + CoreId */ and r1, r0, #MPIDR_CPU_MASK and r0, r0, #MPIDR_CLUSTER_MASK eor r0, r0, #(1 << MPIDR_CLUSTER_SHIFT) add r0, r1, r0, LSR #6 bx lr -UNWIND( .fnend) END_FUNC get_core_pos_mpidr diff --git a/core/arch/arm/plat-zynq7k/plat_init.S b/core/arch/arm/plat-zynq7k/plat_init.S index cf6df3c7..86b35dac 100644 --- a/core/arch/arm/plat-zynq7k/plat_init.S +++ b/core/arch/arm/plat-zynq7k/plat_init.S @@ -57,8 +57,6 @@ * Trap CPU in case of error. */ FUNC plat_cpu_reset_early , : -UNWIND( .fnstart) - /* * Disallow NSec to mask FIQ [bit4: FW=0] * Allow NSec to manage Imprecise Abort [bit5: AW=1] @@ -103,5 +101,4 @@ UNWIND( .fnstart) write_pcr r0 mov pc, lr -UNWIND( .fnend) END_FUNC plat_cpu_reset_early diff --git a/core/arch/arm/sm/pm_a32.S b/core/arch/arm/sm/pm_a32.S index 84bdf595..a927b1e7 100644 --- a/core/arch/arm/sm/pm_a32.S +++ b/core/arch/arm/sm/pm_a32.S @@ -23,7 +23,6 @@ * -1 - cpu not suspended. */ FUNC sm_pm_cpu_suspend, : -UNWIND( .fnstart) UNWIND( .cantunwind) push {r4 - r12, lr} mov r5, sp @@ -43,11 +42,9 @@ aborted: mov r0, #(-1) suspend_return: pop {r4 - r12, pc} -UNWIND( .fnend) END_FUNC sm_pm_cpu_suspend FUNC sm_pm_cpu_do_suspend, : -UNWIND( .fnstart) UNWIND( .cantunwind) push {r4 - r11} read_midr r4 @@ -89,11 +86,9 @@ a7_suspend: stmia r0, {r4 - r7} pop {r4 - r11} bx lr -UNWIND( .fnend) END_FUNC sm_pm_cpu_do_suspend FUNC sm_pm_cpu_resume, : -UNWIND( .fnstart) UNWIND( .cantunwind) cpsid aif @@ -121,7 +116,6 @@ UNWIND( .cantunwind) ldr r0, [r0, #THREAD_CORE_LOCAL_SM_PM_CTX_PHYS] /* Need to use r0!, because sm_pm_cpu_do_resume needs it */ ldmia r0!, {sp, pc} -UNWIND( .fnend) END_FUNC sm_pm_cpu_resume /* @@ -145,7 +139,6 @@ _core_pos: * field of struct sm_pm_ctx. */ FUNC sm_pm_cpu_do_resume, : -UNWIND( .fnstart) UNWIND( .cantunwind) read_midr r4 ubfx r5, r4, #4, #12 @@ -199,6 +192,5 @@ a7_resume: isb mov r0, #0 b suspend_return -UNWIND( .fnend) END_FUNC sm_pm_cpu_do_resume diff --git a/core/arch/arm/sm/psci-helper.S b/core/arch/arm/sm/psci-helper.S index 54a52673..feaca88e 100644 --- a/core/arch/arm/sm/psci-helper.S +++ b/core/arch/arm/sm/psci-helper.S @@ -9,27 +9,22 @@ #include <kernel/cache_helpers.h> FUNC psci_disable_smp, : -UNWIND( .fnstart) read_actlr r0 bic r0, r0, #ACTLR_SMP write_actlr r0 isb bx lr -UNWIND( .fnend) END_FUNC psci_disable_smp FUNC psci_enable_smp, : -UNWIND( .fnstart) read_actlr r0 orr r0, r0, #ACTLR_SMP write_actlr r0 isb bx lr -UNWIND( .fnend) END_FUNC psci_enable_smp FUNC psci_armv7_cpu_off, : -UNWIND( .fnstart) push {r12, lr} UNWIND( .save {r12, lr}) @@ -51,5 +46,4 @@ UNWIND( .save {r12, lr}) bl psci_disable_smp pop {r12, pc} -UNWIND( .fnend) END_FUNC psci_armv7_cpu_off diff --git a/core/arch/arm/sm/sm_a32.S b/core/arch/arm/sm/sm_a32.S index 83c35feb..81820f63 100644 --- a/core/arch/arm/sm/sm_a32.S +++ b/core/arch/arm/sm/sm_a32.S @@ -26,7 +26,6 @@ .endm FUNC sm_save_unbanked_regs , : -UNWIND( .fnstart) UNWIND( .cantunwind) /* User mode registers has to be saved from system mode */ cps #CPSR_MODE_SYS @@ -50,7 +49,6 @@ UNWIND( .cantunwind) #endif cps #CPSR_MODE_MON bx lr -UNWIND( .fnend) END_FUNC sm_save_unbanked_regs .macro restore_regs mode @@ -63,7 +61,6 @@ END_FUNC sm_save_unbanked_regs /* Restores the mode specific registers */ FUNC sm_restore_unbanked_regs , : -UNWIND( .fnstart) UNWIND( .cantunwind) /* User mode registers has to be saved from system mode */ cps #CPSR_MODE_SYS @@ -87,7 +84,6 @@ UNWIND( .cantunwind) #endif cps #CPSR_MODE_MON bx lr -UNWIND( .fnend) END_FUNC sm_restore_unbanked_regs /* @@ -98,7 +94,6 @@ END_FUNC sm_restore_unbanked_regs * Async abort has to be masked while using stack_tmp. */ LOCAL_FUNC sm_smc_entry , : -UNWIND( .fnstart) UNWIND( .cantunwind) srsdb sp!, #CPSR_MODE_MON push {r0-r7} @@ -199,7 +194,6 @@ UNWIND( .cantunwind) .sm_exit: pop {r0-r7} rfefd sp! -UNWIND( .fnend) END_FUNC sm_smc_entry /* @@ -210,7 +204,6 @@ END_FUNC sm_smc_entry * from FIQ. */ LOCAL_FUNC sm_fiq_entry , : -UNWIND( .fnstart) UNWIND( .cantunwind) /* FIQ has a +4 offset for lr compared to preferred return address */ sub lr, lr, #4 @@ -250,12 +243,10 @@ UNWIND( .cantunwind) add sp, sp, #(SM_CTX_SEC + SM_SEC_CTX_MON_LR) rfefd sp! -UNWIND( .fnend) END_FUNC sm_fiq_entry .align 5 LOCAL_FUNC sm_vect_table , : -UNWIND( .fnstart) UNWIND( .cantunwind) b . /* Reset */ b . /* Undefined instruction */ @@ -332,12 +323,10 @@ sm_vect_table_bpiall: /* unhandled exception */ b . #endif /*!CFG_CORE_WORKAROUND_SPECTRE_BP*/ -UNWIND( .fnend) END_FUNC sm_vect_table /* void sm_init(vaddr_t stack_pointer); */ FUNC sm_init , : -UNWIND( .fnstart) /* Set monitor stack */ mrs r1, cpsr cps #CPSR_MODE_MON diff --git a/core/arch/arm/tee/arch_svc_a32.S b/core/arch/arm/tee/arch_svc_a32.S index 7f811cb6..7ec381ce 100644 --- a/core/arch/arm/tee/arch_svc_a32.S +++ b/core/arch/arm/tee/arch_svc_a32.S @@ -16,7 +16,6 @@ * Called from user_ta_handle_svc() */ FUNC tee_svc_do_call , : -UNWIND( .fnstart) UNWIND( .cantunwind) push {r5-r9, lr} mov r7, sp @@ -56,7 +55,6 @@ UNWIND( .cantunwind) .Lret: mov sp, r7 pop {r5-r9, pc} -UNWIND( .fnend) END_FUNC tee_svc_do_call /* @@ -86,12 +84,10 @@ END_FUNC tee_svc_do_call * tee_svc_unwind_enter_user_mode(). */ FUNC syscall_sys_return , : -UNWIND( .fnstart) mov r1, #0 /* panic = false */ mov r2, #0 /* panic_code = 0 */ mov r3, r8 /* pointer to struct thread_svc_regs */ b tee_svc_sys_return_helper -UNWIND( .fnend) END_FUNC syscall_sys_return /* @@ -103,11 +99,9 @@ END_FUNC syscall_sys_return * thread_svc_handler() in r8. */ FUNC syscall_panic , : -UNWIND( .fnstart) mov r1, #1 /* panic = true */ mov r2, r0 /* panic_code = 0 */ mov r3, r8 /* pointer to struct thread_svc_regs */ ldr r0, =TEE_ERROR_TARGET_DEAD b tee_svc_sys_return_helper -UNWIND( .fnend) END_FUNC syscall_panic diff --git a/lib/libutee/arch/arm/utee_syscalls_a32.S b/lib/libutee/arch/arm/utee_syscalls_a32.S index a2fe442c..6e621ca6 100644 --- a/lib/libutee/arch/arm/utee_syscalls_a32.S +++ b/lib/libutee/arch/arm/utee_syscalls_a32.S @@ -13,8 +13,6 @@ .macro UTEE_SYSCALL name, scn, num_args FUNC \name , : - -UNWIND( .fnstart) push {r5-r7,lr} UNWIND( .save {r5-r7,lr}) #if defined(CFG_SYSCALL_WRAPPERS_MCOUNT) && !defined(__LDELF__) @@ -43,12 +41,10 @@ UNWIND( .save {r5-r7,lr}) .endif svc #0 pop {r5-r7,pc} -UNWIND( .fnend) END_FUNC \name .endm FUNC _utee_panic, : -UNWIND( .fnstart) push {r0-r11, lr} UNWIND( .save {r0-r11, lr}) mov lr, pc @@ -57,7 +53,6 @@ UNWIND( .save {lr}) mov r1, sp bl __utee_panic /* Not reached */ -UNWIND( .fnend) END_FUNC _utee_panic #include "utee_syscalls_asm.S" diff --git a/lib/libutils/ext/include/asm.S b/lib/libutils/ext/include/asm.S index e91d2794..43222639 100644 --- a/lib/libutils/ext/include/asm.S +++ b/lib/libutils/ext/include/asm.S @@ -3,7 +3,7 @@ * Copyright (c) 2014, STMicroelectronics International N.V. */ -#if defined(CFG_UNWIND) +#if defined(CFG_UNWIND) && defined(__arm__) #define UNWIND(...) __VA_ARGS__ #else #define UNWIND(...) @@ -19,6 +19,7 @@ .type \name , %function .balign 4 \name \colon +UNWIND( .fnstart) .endm .macro DATA name colon @@ -36,6 +37,7 @@ .type \name , %function .balign 4 \name \colon +UNWIND( .fnstart) .endm .macro LOCAL_DATA name colon @@ -48,5 +50,6 @@ .endm .macro END_FUNC name +UNWIND( .fnend) .size \name , .-\name .endm diff --git a/lib/libutils/isoc/arch/arm/arm32_aeabi_divmod_a32.S b/lib/libutils/isoc/arch/arm/arm32_aeabi_divmod_a32.S index 76898ef5..a600c879 100644 --- a/lib/libutils/isoc/arch/arm/arm32_aeabi_divmod_a32.S +++ b/lib/libutils/isoc/arch/arm/arm32_aeabi_divmod_a32.S @@ -10,9 +10,7 @@ * return quotient and remaining the EABI way (regs r0,r1) */ FUNC ret_idivmod_values , : -UNWIND( .fnstart) bx lr -UNWIND( .fnend) END_FUNC ret_idivmod_values /* @@ -20,7 +18,5 @@ END_FUNC ret_idivmod_values * return quotient and remaining the EABI way (regs r0,r1) */ FUNC ret_uidivmod_values , : -UNWIND( .fnstart) bx lr -UNWIND( .fnend) END_FUNC ret_uidivmod_values diff --git a/lib/libutils/isoc/arch/arm/arm32_aeabi_ldivmod_a32.S b/lib/libutils/isoc/arch/arm/arm32_aeabi_ldivmod_a32.S index b9f3408a..2dc50bc9 100644 --- a/lib/libutils/isoc/arch/arm/arm32_aeabi_ldivmod_a32.S +++ b/lib/libutils/isoc/arch/arm/arm32_aeabi_ldivmod_a32.S @@ -9,7 +9,6 @@ * __value_in_regs lldiv_t __aeabi_ldivmod( long long n, long long d) */ FUNC __aeabi_ldivmod , : -UNWIND( .fnstart) push {ip, lr} UNWIND( .save {ip, lr}) push {r0-r3} @@ -18,7 +17,6 @@ UNWIND( .save {r0-r3}) bl __l_divmod pop {r0-r3} pop {ip, pc} -UNWIND( .fnend) END_FUNC __aeabi_ldivmod /* @@ -26,7 +24,6 @@ END_FUNC __aeabi_ldivmod * unsigned long long n, unsigned long long d) */ FUNC __aeabi_uldivmod , : -UNWIND( .fnstart) push {ip, lr} UNWIND( .save {ip, lr}) push {r0-r3} @@ -35,5 +32,4 @@ UNWIND( .save {r0-r3}) bl __ul_divmod pop {r0-r3} pop {ip, pc} -UNWIND( .fnend) END_FUNC __aeabi_uldivmod diff --git a/ta/arch/arm/ta_entry_a32.S b/ta/arch/arm/ta_entry_a32.S index f73e3915..d2f8a69d 100644 --- a/ta/arch/arm/ta_entry_a32.S +++ b/ta/arch/arm/ta_entry_a32.S @@ -16,8 +16,6 @@ * ^ */ FUNC __ta_entry, : -UNWIND( .fnstart) UNWIND( .cantunwind) bl __ta_entry_c -UNWIND( .fnend) END_FUNC __ta_entry |