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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-21 19:53:49 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-21 19:53:49 +0000 |
| commit | 208bbb179720222f412df69505810970bc69a359 (patch) | |
| tree | ba809a666f9a2466dd6e935b3620495099f24231 /test | |
| parent | fdc698b726543ec9a3066a8f98d95161c4b4d9f1 (diff) | |
AMDGPU: Use CopyToReg for interp intrinsic lowering
This doesn't use the default value, so doesn't benefit from the hack
to help optimize it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375450 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll index 37417a9bc36..5d2e10756c3 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll @@ -6,8 +6,8 @@ define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 { ; GFX9-32BANK-LABEL: interp_f16: ; GFX9-32BANK: ; %bb.0: ; %main_body -; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-32BANK-NEXT: s_mov_b32 m0, s2 +; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y ; GFX9-32BANK-NEXT: v_mov_b32_e32 v2, s1 @@ -20,8 +20,8 @@ define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) ; ; GFX8-32BANK-LABEL: interp_f16: ; GFX8-32BANK: ; %bb.0: ; %main_body -; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-32BANK-NEXT: s_mov_b32 m0, s2 +; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y ; GFX8-32BANK-NEXT: v_mov_b32_e32 v2, s1 @@ -119,8 +119,8 @@ main_body: define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 { ; GFX9-32BANK-LABEL: interp_p2_m0_setup: ; GFX9-32BANK: ; %bb.0: ; %main_body -; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-32BANK-NEXT: s_mov_b32 m0, s2 +; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y ; GFX9-32BANK-NEXT: ;;#ASMSTART @@ -136,8 +136,8 @@ define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 in ; ; GFX8-32BANK-LABEL: interp_p2_m0_setup: ; GFX8-32BANK: ; %bb.0: ; %main_body -; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-32BANK-NEXT: s_mov_b32 m0, s2 +; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y ; GFX8-32BANK-NEXT: ;;#ASMSTART |