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Import u-boot DDR init code for imx6ul. Since the u-boot stuff is GPL-2.0+
we can't send it to the ATF repo. Therefore this patch must not be included
in any PR to ATF.
It should probably be a standalone patch in the meta-mbl layer and applied
during building of the i.MX6 ATF binary.
For now just stack it as a patch for the Linaro landing area to host.
Original code from u-boot upstream:
83d290c56fab2d38cd1ab4c4cc7099559c1d5046
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/mx6/ddr.c
https://gitlab.denx.de/u-boot/u-boot/blob/master/include/linux/kernel.h
https://gitlab.denx.de/u-boot/u-boot/blob/master/board/technexion/pico-imx6ul/spl.c
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/include/asm/arch-mx6/mx6-ddr.h
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Othwise below assert happens when loading certificate file that
locates in the end part of FIP.
ASSERT: drivers/io/io_block.c:159
BACKTRACE: START: assert
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I5a94df59cf1b63657bfe336ca064f40acc6a753e
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- Add SD device and add it to io map storage.
- move timer init earlier because SD driver need delay function.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I3b2b8914460fd2ccd97dd7f30cf233b4df4f6eab
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This patch adds in a port for the i.MX6UL Pico PI from Technexion.
Right now only files that really differ from the i.MX7D pico are:
- imx6ul_picopi_bl2_el3_setup.c
- plat/imx/imx6/include/imx_regs.h
- plat/imx/imx6/include/imx_io_mux.h
There may be some more differences as we enable trusted boot but, for now
this initial version differs only very slightly at the clock and mux level.
The higher level FIP logic is unchanged and similarly the HAB failover
works as it does on the i.MX7.
In order to compile up the u-boot ddr intiialization code
1. Populate plat/imx/imx6/common/uboot_ddr_init with patched u-boot files:
arch/arm/mach-imx/mx6/ddr.c
arch/arm/include/asm/arch-mx6/mx6-ddr.h
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
2. Specify BUILD_UBOOT_DRAM_INIT=1 when building
The resulting binary will be dual-license BSD/GPL-2.0+.
See board documentation for further details.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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In order to import u-boot DDR initialization code we will need to provide
some very simple is_imx6ul() type functions.
We can inline those simple functions in a compatibility header licensed BSD
like the rest of ATF.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Pins have individual MUX functions but, it is also the case that different
muxed pins can be assigned to different IP blocks. The processes of
selecting one of an array of pins for a block function is called selecting
the input.
Provide a simple wrapper around pad input selection now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch adds a simple i.MX6 clock setup layer. We turn on all clocks by
default. Later on the runtime OS can switch off/on clocks as necessary.
To begin with though all clocks on makes initial bringup easier and less
error prone.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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When we made the original i.MX7 port the idea of having shared clock
headers seemed like a good one. Adding in the i.MX6 though its clear
there's not much cross-over between the two SoC architectures in this
regard. As a result we can remove imx_clock.h. Do so now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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When we made the original i.MX7 port the idea of having shared io mux
headers seemed like a good one. Adding in the i.MX6 though its clear
there's not much cross-over between the two SoC architectures at the
register location level. As a result imx_io_mux.h is not necessary or
desirable.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Depending on the SoC arch in question we have a variable number of
watchdogs. The number of watchdogs is defined in the imx_regs.h for a given
SoC arch.
This patch incrementally initializes watchdogs depending on the number
given in imx_regs.h.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Previous patches split up the imx7 clock layer into different pieces in
expectation that some of those pieces would be reusable across different
SoC architectures.
When implementing the i.MX6UL clock layer though its obvious that the
clocking structure is quite different between the different SoC
architectures, so, it makes sense to conglomerate the i.MX7 stuff into an
i.MX7 specific set of files.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Doing a port of the i.MX6 its obvious we will need SoC family specific
io_mux definitions.
The first step in that is moving plat/imx/common/include/imx_io_mux.h to
plat/imx/imx7/include/imx_io_mux.h.
The second step will be creating an i.MX6 specific version of it to capture
what we need to do for i.MX6.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch allows a value defined in imx_regs.h to indicate how many
elements ought to be iterated over to configure AIPS blocks.
This way we can have differentiation between i.MX6ULL and i.MX6UL which
contain respectively three and two AIPS blocks.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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In the specification the area is marked as reserved not as AIPS4. Fix the
error by subtracting the definition of AIPS4 now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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In order to make the AIPS configuration code more portable between i.MX6
and i.MX7 we need to define the number of AIPS blocks to work with.
Do that now for i.MX7.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Add FIP_ROM_OFFSET to make it fexiable to be changed in build time.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I0dd65251de6b1280d0784b3cc4bae8a5dcf67fe0
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Sets up AIPSTZ configuration when TEE is on.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch enables Trusted Boot on the i.MX8MM with BL2 doing image
verification from a FIP prior to hand-over to BL31.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Adds bl2 with FIP to the build build required for mbed Linux booting where
we do:
BootROM -> BL2 -> OPTEE -> u-boot
If BUILD_BL2 is specified then BL2 will be built and BL31 will have its
address range modified upwards to accommodate. BL31 must be loaded from a
FIP in this case.
If BUILD_BL2 is not specified then the current BL31 boot flow is unaffected
and u-boot SPL will load and execute BL31 directly.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This is a copy/paste of the WaRP7 code sufficient to compile for i.MX8.
Further changes will be required when extracting elements from a real FIP.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This is a copy/paste of the WaRP7 code sufficient to compile for i.MX8.
Further changes will be required when extracting elements from a real FIP.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Allows for exporting of FIP related methods cleanly in a private header.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Commit 45a95e390859 ("imx: Configure CAAM job rings master ID for i.MX8MQ")
fixes up the job-ring ownership permissions for the i.MX8MQ. This same fix
is applicable and required for the i.MX8MM.
Apply the same fix now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch adds support for handing off to a TEE BL32 prior to handing off
to non-secure u-boot BL33.
It is based on NXP's code from codeaurora.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Commit 2374ab1799be ("Mbed TLS: Remove weak heap implementation") places a
requirement on a platform to provide plat_get_mbedtls_heap().
This commit make that provision for imx7 pico.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Between the older versions of ATF and the never version we are moving to
here, the header paths have changed.
Minor update to fix.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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We need to specify include path with full path.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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In this commit we rebase picopi to latest master branch. We need to
specify some include with full path to avoid FTBFS. Also we start
using MULTI_CONSOLE_API.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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It is possible for OP-TEE to provide a DTB overlay directly to subsequent
boot stages. So we do not need to bundle a DTB in the FIP.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Change name of files and variables from warp7 to picopi
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Copy warp7 folder as it is to start pico-pi development.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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* changes:
imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*
plat: imx8mq: Implement IMX_SIP_GET_SOC_INFO
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Platform defines are already provided by the build system so let's not
duplicate them.
Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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The manual documents that 0x3036006c should contains the soc revision
for imx8mq but this always reports A0. Work around this by parsing the
ROM header and checking if OCOTP register 0x40 is stuck at 0xff0055aa.
Determining this inside TF-A makes life easier for OS, see for example
this linux discussion: https://lkml.org/lkml/2019/5/3/465
The soc revision can also be useful inside TF-A itself, for example for
the non-upstream DDR DVFS "busfreq" feature is affected by 8mq erratas.
The clock for OCOTP block can be disabled by OS so only initialize soc
revision once at boot time.
Change-Id: I9ca3f27840229ce8a28b53870e44da29f63c73aa
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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Remove an assert() that assumes a specific value being passed from
BL2. This value is dependent on BL2 version, so makes this assert()
not portable.
Suggested-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Change-Id: Ife3d934b2fa37fc1c66963dd4eb1afe2ca17d740
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* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platform DRAM2 base
Disable speculative loads only if SSBS is supported
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N1SDP exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ
can be written but does not reflect the value of the CNTFRQ register
in CNTCTLBase frame. This doesn't follow ARM ARM in that the value
updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ.
Hence enable the workaround (applied to Juno) for N1SDP that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.
Change-Id: Id89ee1bca0f25c9d62f8f794f2c4f4e618cdf092
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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The default DRAM2 start address for Arm platforms
is 0x880000000. However, for N1SDP platform this is
0x8080000000.
Fix the DRAM2 start address by initialising
PLAT_ARM_DRAM2_BASE.
Without this fix there is a mismatch of the System
memory region view as seen by the BL31 runtime
firmware (PSCI) versus the view of the OS (which
is based on the description provided by UEFI. In
this case UEFI is correctly describing the DRAM2
start address).
This implicates in secondary cores failing to start
on some Operating Systems if the OS decides to place
the secondary start address in the mismatched region.
Change-Id: I57220e753219353dda429868b4c5e1a69944cc64
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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The default DRAM2 base address for Arm platforms
is 0x880000000. However, on some platforms the
firmware may want to move the start address to
a different value.
To support this introduce PLAT_ARM_DRAM2_BASE that
defaults to 0x880000000; but can be overridden by
a platform (e.g. in platform_def.h).
Change-Id: I0d81195e06070bc98f376444b48ada2db1666e28
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
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Remove duplicated linker symbols, resue the symbols
defined in bl_common.h
Change-Id: I10de450eccc78c09b61a8ae7126bf4f4029fa682
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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For security DMA should be blocked at the SMMU by default
unless explicitly enabled for a device. SMMU is disabled
after reset with all streams bypassing the SMMU, and
abortion of all incoming transactions implements a default
deny policy on reset.
This patch also moves "bl1_platform_setup()" function from
arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and
fvp_ve_bl1_setup.c files.
Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver
Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but
it's also applicable to imx8m.
This fixes U-Boot not printing commit hash on 8m with upstream TF-A.
Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
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