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This patch is necessary to produce the right licensing information during a
bitbake build of ATF including the GPL v2+ code we are importing from
u-boot.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Import u-boot DDR init code for imx6ul. Since the u-boot stuff is GPL-2.0+
we can't send it to the ATF repo. Therefore this patch must not be included
in any PR to ATF.
It should probably be a standalone patch in the meta-mbl layer and applied
during building of the i.MX6 ATF binary.
For now just stack it as a patch for the Linaro landing area to host.
Original code from u-boot upstream:
83d290c56fab2d38cd1ab4c4cc7099559c1d5046
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-imx/mx6/ddr.c
https://gitlab.denx.de/u-boot/u-boot/blob/master/include/linux/kernel.h
https://gitlab.denx.de/u-boot/u-boot/blob/master/board/technexion/pico-imx6ul/spl.c
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/include/asm/arch-mx6/mx6-ddr.h
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Othwise below assert happens when loading certificate file that
locates in the end part of FIP.
ASSERT: drivers/io/io_block.c:159
BACKTRACE: START: assert
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I5a94df59cf1b63657bfe336ca064f40acc6a753e
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- Add SD device and add it to io map storage.
- move timer init earlier because SD driver need delay function.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I3b2b8914460fd2ccd97dd7f30cf233b4df4f6eab
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- Support SD CMD8 because it does not have data operation, while
EMMC CMD8 do.
- Ehence clock divider calculation.
- Support 1bit bus width in driver.
- A delay workaround for imx8 is added, otherwise, cmd6 fails. It may
be due to mmc config from SPL. We shall remove this after removing
SPL.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I0fc22caf85606b91a1591775da0c54d5b5d3eb39
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This patch adds in a port for the i.MX6UL Pico PI from Technexion.
Right now only files that really differ from the i.MX7D pico are:
- imx6ul_picopi_bl2_el3_setup.c
- plat/imx/imx6/include/imx_regs.h
- plat/imx/imx6/include/imx_io_mux.h
There may be some more differences as we enable trusted boot but, for now
this initial version differs only very slightly at the clock and mux level.
The higher level FIP logic is unchanged and similarly the HAB failover
works as it does on the i.MX7.
In order to compile up the u-boot ddr intiialization code
1. Populate plat/imx/imx6/common/uboot_ddr_init with patched u-boot files:
arch/arm/mach-imx/mx6/ddr.c
arch/arm/include/asm/arch-mx6/mx6-ddr.h
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
2. Specify BUILD_UBOOT_DRAM_INIT=1 when building
The resulting binary will be dual-license BSD/GPL-2.0+.
See board documentation for further details.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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In order to import u-boot DDR initialization code we will need to provide
some very simple is_imx6ul() type functions.
We can inline those simple functions in a compatibility header licensed BSD
like the rest of ATF.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Pins have individual MUX functions but, it is also the case that different
muxed pins can be assigned to different IP blocks. The processes of
selecting one of an array of pins for a block function is called selecting
the input.
Provide a simple wrapper around pad input selection now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch adds a simple i.MX6 clock setup layer. We turn on all clocks by
default. Later on the runtime OS can switch off/on clocks as necessary.
To begin with though all clocks on makes initial bringup easier and less
error prone.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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When we made the original i.MX7 port the idea of having shared clock
headers seemed like a good one. Adding in the i.MX6 though its clear
there's not much cross-over between the two SoC architectures in this
regard. As a result we can remove imx_clock.h. Do so now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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When we made the original i.MX7 port the idea of having shared io mux
headers seemed like a good one. Adding in the i.MX6 though its clear
there's not much cross-over between the two SoC architectures at the
register location level. As a result imx_io_mux.h is not necessary or
desirable.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Depending on the SoC arch in question we have a variable number of
watchdogs. The number of watchdogs is defined in the imx_regs.h for a given
SoC arch.
This patch incrementally initializes watchdogs depending on the number
given in imx_regs.h.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Previous patches split up the imx7 clock layer into different pieces in
expectation that some of those pieces would be reusable across different
SoC architectures.
When implementing the i.MX6UL clock layer though its obvious that the
clocking structure is quite different between the different SoC
architectures, so, it makes sense to conglomerate the i.MX7 stuff into an
i.MX7 specific set of files.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Doing a port of the i.MX6 its obvious we will need SoC family specific
io_mux definitions.
The first step in that is moving plat/imx/common/include/imx_io_mux.h to
plat/imx/imx7/include/imx_io_mux.h.
The second step will be creating an i.MX6 specific version of it to capture
what we need to do for i.MX6.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch allows a value defined in imx_regs.h to indicate how many
elements ought to be iterated over to configure AIPS blocks.
This way we can have differentiation between i.MX6ULL and i.MX6UL which
contain respectively three and two AIPS blocks.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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In the specification the area is marked as reserved not as AIPS4. Fix the
error by subtracting the definition of AIPS4 now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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In order to make the AIPS configuration code more portable between i.MX6
and i.MX7 we need to define the number of AIPS blocks to work with.
Do that now for i.MX7.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Add FIP_ROM_OFFSET to make it fexiable to be changed in build time.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: I0dd65251de6b1280d0784b3cc4bae8a5dcf67fe0
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Sets up AIPSTZ configuration when TEE is on.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch enables Trusted Boot on the i.MX8MM with BL2 doing image
verification from a FIP prior to hand-over to BL31.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Adds bl2 with FIP to the build build required for mbed Linux booting where
we do:
BootROM -> BL2 -> OPTEE -> u-boot
If BUILD_BL2 is specified then BL2 will be built and BL31 will have its
address range modified upwards to accommodate. BL31 must be loaded from a
FIP in this case.
If BUILD_BL2 is not specified then the current BL31 boot flow is unaffected
and u-boot SPL will load and execute BL31 directly.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This is a copy/paste of the WaRP7 code sufficient to compile for i.MX8.
Further changes will be required when extracting elements from a real FIP.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This is a copy/paste of the WaRP7 code sufficient to compile for i.MX8.
Further changes will be required when extracting elements from a real FIP.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Allows for exporting of FIP related methods cleanly in a private header.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Commit 45a95e390859 ("imx: Configure CAAM job rings master ID for i.MX8MQ")
fixes up the job-ring ownership permissions for the i.MX8MQ. This same fix
is applicable and required for the i.MX8MM.
Apply the same fix now.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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This patch adds support for handing off to a TEE BL32 prior to handing off
to non-secure u-boot BL33.
It is based on NXP's code from codeaurora.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Commit 2374ab1799be ("Mbed TLS: Remove weak heap implementation") places a
requirement on a platform to provide plat_get_mbedtls_heap().
This commit make that provision for imx7 pico.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Between the older versions of ATF and the never version we are moving to
here, the header paths have changed.
Minor update to fix.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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We need to specify include path with full path.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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In this commit we rebase picopi to latest master branch. We need to
specify some include with full path to avoid FTBFS. Also we start
using MULTI_CONSOLE_API.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
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It is possible for OP-TEE to provide a DTB overlay directly to subsequent
boot stages. So we do not need to bundle a DTB in the FIP.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Change name of files and variables from warp7 to picopi
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Copy warp7 folder as it is to start pico-pi development.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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Change-Id: Ic09e74f22b43fba51ee17cd02b5e1dc5d8e0bb63
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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* changes:
Docs fixes
Update security documentation
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This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.
Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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1) Fix links in "about" page
2) Put back the "contents" page with adjusted links
Change-Id: Id09140b91df5cf0a275149801d05d8cfeeda1c6e
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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1) Replace references to "Arm Trusted Firmware" with "TF-A"
2) Update issue tracker link
Change-Id: I12d827d49f6cc34e46936d7f7ccf44e32b26a0bd
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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* changes:
doc: Use proper note and warning annotations
doc: Refactor contributor acknowledgements
doc: Reorganise images and update links
doc: Set correct syntax highlighting style
doc: Add minimal glossary
doc: Remove per-page contents lists
doc: Make checkpatch ignore rst files
doc: Format security advisory titles and headings
doc: Reformat platform port documents
doc: Normalise section numbering and headings
doc: Reword document titles
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Payload length of the get dram mapping information message is 0.
The mbx_mem->len parameter should be 4, it only contains
message header.
Fixes: b67d202 ("plat/synquacer: enable SCMI support")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: If1cd4c855da2dc5dc4b6da3bea152b8441971de7
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The documentation contains plenty of notes and warnings. Enable
special rendering of these blocks by converting the note prefix
into a .. note:: annotation.
Change-Id: I34e26ca6bf313d335672ab6c2645741900338822
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- Make the list of contributors into an actual list
- Use note syntax for the note
- Remove the Individuals heading since there are none
This file could be considered for removal as it is a legacy
document, as its note explains.
Change-Id: Idf984bc192af7a0ec367a6642ab99ccccf5df1a8
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Change-Id: I679d1499376a524bef1cfc33df995b0a719b5ac8
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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