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2019-04-02meson/gxl: Add support for SHA256 DMA engineRemi Pommarel
In order to configure and boot SCP, BL31 has to compute and send the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC has a DMA facility that could be used to offload SHA-256 computations. This adds basic support of this hardware SHA-256 engine. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
2019-04-01Remove several warnings reported with W=1Ambroise Vincent
Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-18Merge pull request #1894 from jts-arm/e1_midrSoby Mathew
Fix MIDR_EL1 value for Neoverse E1
2019-03-15Fix wrong MIDR_EL1 value for Neoverse E1John Tsichritzis
Change-Id: I75ee39d78c81ecb528a671c0cfadfc2fe7b5d818 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-15Merge pull request #1888 from jts-arm/zeusDimitris Papastamos
Introduce preliminary support for Neoverse Zeus
2019-03-14Introduce preliminary support for Neoverse ZeusJohn Tsichritzis
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-14Apply variant 4 mitigation for Neoverse N1John Tsichritzis
This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-13Cortex-A17: Implement workaround for errata 852421Ambroise Vincent
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13Merge pull request #1882 from ambroise-arm/av/a15-errataSoby Mathew
Apply workarounds for errata of Cortex-A15
2019-03-13Merge pull request #1879 from pbeesley-arm/pb/todo-removalSoby Mathew
Pb/todo removal
2019-03-13Merge pull request #1858 from thloh85-intel/dwmmc_fixesSoby Mathew
drivers: synopsys: Fix synopsys MMC driver
2019-03-13Cortex-A15: Implement workaround for errata 827671Ambroise Vincent
This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-13plat/arm: mhu: make mhu driver genericMasahisa Kojima
MHU doorbell driver requires arm platform specific macro "PLAT_CSS_MHU_BASE". Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm can use generic MHU doorbell driver. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
2019-03-12drivers: Remove TODO from io_storagePaul Beesley
This TODO was added five years ago so I assume that there is not going to be a shutdown API added after all. Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-12drivers: synopsys: Fix synopsys MMC driverTien Hock, Loh
There are some issues with synopsys MMC driver: - CMD8 should not expect data (for SD) - ACMD51 should expect data (Send SCR for SD) - dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is now handled in the dw_prepare function - after the CMD completes, when doing dw_read, we need to invalidate cache and wait for the data transfer to complete - Need to set FIFO threshold, otherwise DMA might never get the interrupt to read or write Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
2019-03-08Merge pull request #1863 from thloh85-intel/mmc_fixesDimitris Papastamos
drivers: mmc: Fix some issues with MMC stack
2019-03-07drivers: mmc: Fix some issues with MMC stackTien Hock, Loh
Some bugs in MMC stack needs to be fixed: - scr cannot be local as this will cause cache issue when invalidating after the read DMA transfer is completed - ACMD41 needs to send voltage information in initialization, otherwise the command is a query, thus will not initialize the controller - when checking device state, retry until the retries counter goes to zero before failing Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
2019-03-04Ensure proper ID register is checked for feature detectionDimitris Papastamos
SSBS support is determined by checking ID_AA64PFR1_EL1 and not ID_AA64PFR0_EL1. Fixes ARM-Software/tf-issues#679 Change-Id: I8ecba13b850995ec6a6ede3c2a1e02e69a3a95db Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2019-03-04Merge pull request #1851 from antonio-nino-diaz-arm/an/pauthAntonio Niño Díaz
Correctly check for support of Address Authentication
2019-03-01Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz
Tegra scatter file support
2019-03-01Merge pull request #1849 from loumay-arm/lm/a73_errataAntonio Niño Díaz
Cortex-A73: Implement workaround for errata 852427
2019-03-01Correctly check for support of Address AuthenticationAntonio Nino Diaz
Check for both IMPLEMENTATION_DEFINED and Architected algorithms of Address Authentication. Change-Id: I209dcc6087172cfef7baf8d09e0454628f02cbd0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-03-01Merge pull request #1845 from ambroise-arm/av/errataAntonio Niño Díaz
Apply workarounds for errata of Cortex-A53, A55 and A57
2019-03-01Merge pull request #1846 from loumay-arm/lm/mpamAntonio Niño Díaz
MPAM: enable MPAM EL2 traps
2019-03-01Merge pull request #1848 from antonio-nino-diaz-arm/an/docsAntonio Niño Díaz
Minor changes to documentation and comments
2019-02-28Minor changes to documentation and commentsAntonio Nino Diaz
Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-28Cortex-A73: Implement workaround for errata 852427Louis Mayencourt
In AArch32, execution of 2 instructions with opposite condition code might lead to either a data corruption or a CPU deadlock. Set the bit 12 of the Diagnostic Register to prevent this. Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-28MPAM: enable MPAM EL2 trapsLouis Mayencourt
Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2 traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an MPAM-unaware-hypervisor to be restricted by an MPAM-aware-guest. Change-Id: I47bf3f833fa22baa590f83d49cc0e3f2974e698d Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-28Merge pull request #1839 from loumay-arm/lm/a7x_errataAntonio Niño Díaz
Cortex-A73/75/76 errata workaround
2019-02-28Cortex-A53: Workarounds for 819472, 824069 and 827319Ambroise Vincent
The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28Cortex-A57: Implement workaround for erratum 814670Ambroise Vincent
Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28Cortex-A55: Implement workaround for erratum 798797Ambroise Vincent
Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28Cortex-A55: Implement workaround for erratum 778703Ambroise Vincent
Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-28Cortex-A55: Implement workaround for erratum 768277Ambroise Vincent
Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-27Tegra: Support for scatterfile for the BL31 imageVarun Wadekar
This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-02-27Merge pull request #1829 from antonio-nino-diaz-arm/an/pauthAntonio Niño Díaz
Add Pointer Authentication (ARMv8.3-PAuth) support to the TF
2019-02-27Merge pull request #1840 from grandpaul/rpi3-sdhost-improve1Antonio Niño Díaz
RaspberryPi3 sdhost driver improvement.
2019-02-27TSP: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.4% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +352 | +0 | +16 | +0 | | | 3.1% | | 15.8% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I6cc1fe0b2345c547dcef66f98758c4eb55fe5ee4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL31: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +192 | +1536 | +0 | +0 | | | 0.3% | 3.1% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +1848 | +1536 | +16 | +0 | | | 3.3% | 3.1% | 3.1% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I43db7e509a4f39da6599ec2faa690d197573ec1b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL2_AT_EL3: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +44 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +712 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ The results are valid for the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ BL2_AT_EL3=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I1c0616e7dea30962a92b4fd113428bc30a018320 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL2: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 | | | 0.2% | | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +664 | +0 | +16 | +0 | | | 3.1% | | 0.9% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 The changes for BL2_AT_EL3 aren't done in this commit. Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27BL1: Enable pointer authentication supportAntonio Nino Diaz
The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +108 | +192 | +0 | +0 | | | 0.5% | 0.8% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +748 | +192 | +16 | +0 | | | 3.7% | 0.8% | 7.0% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Add support for pointer authenticationAntonio Nino Diaz
The previous commit added the infrastructure to load and save ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but didn't actually enable pointer authentication in the firmware. This patch adds the functionality needed for platforms to provide authentication keys for the firmware, and a new option (ENABLE_PAUTH) to enable pointer authentication in the firmware itself. This option is disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be enabled. Change-Id: I35127ec271e1198d43209044de39fa712ef202a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Add ARMv8.3-PAuth registers to CPU contextAntonio Nino Diaz
ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Cleanup context handling libraryAntonio Nino Diaz
Minor style cleanup. Change-Id: Ief19dece41a989e2e8157859a265701549f6c585 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-02-27Merge pull request #1831 from antonio-nino-diaz-arm/an/sccdAntonio Niño Díaz
Disable processor Cycle Counting in Secure state
2019-02-27rpi3: sdhost: SDHost driver improvementYing-Chun Liu (PaulLiu)
This commit improves the SDHost driver for RPi3 as following: * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on block reading. * In some low probability that SEND_OP_COND might results CRC7 error. We can consider that the command runs correctly. We don't need to retry this command so removing the code for retry. * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability. * Increase the clock to 50Mhz in data mode to speed up the io. * Change the pull resistors configuration to gain more stability. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2019-02-26Add workaround for errata 1073348 for Cortex-A76Louis Mayencourt
Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26Add workaround for errata 1220197 for Cortex-A76Louis Mayencourt
Streaming store under specific conditions might cause deadlock or data corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write streaming to the L2 to prevent this. Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-02-26Add workaround for errata 764081 of Cortex-A75Louis Mayencourt
Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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