diff options
| author | John Tsichritzis <john.tsichritzis@arm.com> | 2018-10-08 17:09:43 +0100 |
|---|---|---|
| committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-14 11:39:40 +0000 |
| commit | a4546e80f523f9785be6ba8756afd1ec9eec40c7 (patch) | |
| tree | 040c4ad9a98dd912c2f9f940132d36df0eda0b9a /include | |
| parent | 620d9832f96ffcaf86d38b703ca913438d6eea7c (diff) | |
Introduce preliminary support for Neoverse Zeus
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_zeus.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_zeus.h b/include/lib/cpus/aarch64/neoverse_zeus.h new file mode 100644 index 00000000..f0947271 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_zeus.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_ZEUS_H +#define NEOVERSE_ZEUS_H + +#define NEOVERSE_ZEUS_MIDR U(0x410FD400) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* NEOVERSE_ZEUS_H */ |