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authorDimitris Papastamos <dimitris.papastamos@arm.com>2019-03-15 15:28:17 +0000
committerGitHub <noreply@github.com>2019-03-15 15:28:17 +0000
commit1fbb682a73e00883cd4b30253e6ec7701c8e0984 (patch)
tree6ce8b8b6d1169c5d090db28f9fa02919a4d49dde /include
parent136b9fa7c280fad6533f238352170560e7144646 (diff)
parenta4546e80f523f9785be6ba8756afd1ec9eec40c7 (diff)
Merge pull request #1888 from jts-arm/zeus
Introduce preliminary support for Neoverse Zeus
Diffstat (limited to 'include')
-rw-r--r--include/lib/cpus/aarch64/neoverse_zeus.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_zeus.h b/include/lib/cpus/aarch64/neoverse_zeus.h
new file mode 100644
index 00000000..f0947271
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_zeus.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_ZEUS_H
+#define NEOVERSE_ZEUS_H
+
+#define NEOVERSE_ZEUS_MIDR U(0x410FD400)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* NEOVERSE_ZEUS_H */