Age | Commit message (Collapse) | Author |
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Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
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These will be superceded by tianocore release versions from ARM
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
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This patch is prototype and goes with the equivalent patch for pl011
uart. It just just to show the new structure of DSDT if we continue
with this way of doing clocks.
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
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Add DBG2 table compilation support.
Signed-off-by: Naresh Bhat <naresh.bhat@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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These files were taken from the UEFI release for this board. This is the first
draft of the ASL files and will be subject to further revisions.
Signed-off-by: Al Stone <al.stone@linaro.org>
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
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Add these two tables which are supported by ACPICA tools so mab understands
these tables also.
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Added info:
- memory resource ranges
- DSM property, specific for cfi-flash memory
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Since 3.13 kernel birngs a lot of new features and APEI structure refines,
we need to update our tool to make it works with APEI blob.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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We create blob with memory error example as a proof it really works.
This commits only add more detailed info so output message will
looks prettier.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Our test setup assume that GRUB loads APEI blob to the RAM memory.
So all APEI tables must point to the given RAM area.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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The addresses were not updated from the change to the FVP model. Correct
the addresses.
Boot tested with patch series from Hanjun Guo
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Add ASL to support vexpress sysreg rtsm_ve-aemv8a platform.
Signed-off-by: Naresh Bhat <naresh.bhat@linaro.org>
Acked-by: Graeme Gregory <graeme.gregory@linaro.org>
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Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
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Add ASL for AMBA bus and devices on rtsm_ve-aemv8a platform.
Signed-off-by: Naresh Bhat <naresh.bhat@linaro.org>
Acked-by: Graeme Gregory <graeme.gregory@linaro.org>
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Use the official PNPID as LNRO for serial devices.
Signed-off-by: Naresh Bhat <naresh.bhat@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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regarding 1 byte alignment.
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ACPI header is not necessary for blob any more.
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As commit 4a52df24 (ARM64 / ASL: Fix interrupt type and level
flag for device interrupts) did, this patch fix the same problem.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Create GTDT table to convert arch timer for early boot.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Create GTDT table to convert arch timer for early boot.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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This has been discussed with the copyright owner; he is aware of
the change and in agreement with it.
Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Hanjun Guo <hanjun.guo@linaro.org>
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Signed-off-by: Al Stone <al.stone@linaro.org>
Acked-by: Hanjun Guo <hanjun.guo@linaro.org>
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For gic bindings, The 3rd cell of interrupts is the flags,encoded
as follows:
bits[3:0] trigger type and level flags.
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
bits[15:8] PPI interrupt cpu mask.
Please refer to Documentation/devicetree/bindings/arm/gic.txt for
detailed information.
In Foundation model and RTSM model's device tree, the 3rd cell of
interrupts of all devices is 4, so we should use active high
level-sensitive in the DSDT table too when we convert the device
to ACPI.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Add the clk changes for dsdt asl file of foundation-v8 model.
Signed-off-by: Naresh Bhat <naresh.bhat@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Add _HID for pl011-uart devices.
Signed-off-by: Naresh Bhat <naresh.bhat@linaro.org>
Acked-by: Graeme Gregory <graeme.gregory@linaro.org>
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Add ASL for SMB, FPGA, AMBA along with the devices
like CLK, SYSREG, ..etc on the bus.
Signed-off-by: Naresh Bhat <naresh.bhat@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
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Extra table entries in mab will create an incorrect blob.
Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Acked-by: Al Stone <al.stone@linaro.org>
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Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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bfapei now can create blob for EINJ driver as well.
Blob for EINJ driver need to be combined with blob for HEST driver since
EINJ is designed to set status flag for Error Status Block pointed from
HEST table. This way EINJ driver can be tested in easy way. Note that
SCI must be triggered in the next step so GHES driver start to parse error.
This could be done using SCI emulate mechanism.
Logic path:
1. Create Error Status Block (ESB information related to given error,
pointed by HEST)
2. Create pretended registers (blob for EINJ) that instruct kernel to
set status flag in ESB.
3. Trigger error using debugfs
4. Emulate SCI
HOWTO:
Enter to acpi tool repository:
# make PADDR=0x<physical address> APEI=einj <platform>.acpi
Boot target:
Print available error list:
# cat /sys/kernel/debug/apei/einj/available_error_type
0x00000008 Memory Correctable
Set given error type:
# echo 0x00000008 > /sys/kernel/debug/apei/einj/error_type
Confirm error was really set:
# cat /sys/kernel/debug/apei/einj/error_type
0x8
Inject error (here status flag for ESB is set)
# echo 0x00000008 > /sys/kernel/debug/apei/einj/error_inject
Emulate SCI (notification of HED device with 0x80 value)
# echo "HED 128" > /sys/kernel/debug/acpi/sci_notify
ACPI: ACPI device name is <HED>, event code is <128>
ACPI: Notify event is queued
{1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 2
{1}[Hardware Error]: APEI generic hardware error status
{1}[Hardware Error]: severity: 1, fatal
{1}[Hardware Error]: section: 0, severity: 0, recoverable
{1}[Hardware Error]: flags: 0x00
{1}[Hardware Error]: section_type: memory error
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Since every type of test allocate and expand buffer using the same algorithm,
lets move common code to bfapei_expand_buf helper function.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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storage.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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points.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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o set aside pretend physical space to exchange info about error
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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o fix number of Injection Entry in EINJ
o leave one generic hardware error source to get rid of error messages in dmsg,
some of them were x86 specific or not fully supported for ARM now
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
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