juno: add juno platform files

These will be superceded by tianocore release versions from ARM

Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>

7 files changed, 709 insertions, 0 deletions

diff --git a/platforms/juno/apic.asl b/platforms/juno/apic.asl
new file mode 100644
index 0000000..8aaf4f7
--- /dev/null
+++ b/platforms/juno/apic.asl
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2013, Graeme Gregory <graeme.gregory@linaro.org>
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright 
+ * notice, this list of conditions and the following disclaimer.
+ * 
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the 
+ * documentation and/or other materials provided with the distribution.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * 
+ * NB: This License is also known as the "BSD 2-Clause License".
+ * 
+ *
+ * [APIC] Multiple APIC Description Table (MADT)
+ * Format: [ByteLength]  FieldName : HexFieldValue
+ *
+ */
+
+[0004]                          Signature : "APIC"
+[0004]                       Table Length : 0000020C
+[0001]                           Revision : 03
+[0001]                           Checksum : AE
+[0006]                             Oem ID : "LINARO"
+[0008]                       Oem Table ID : "VOLDEMOR"
+[0004]                       Oem Revision : 00000001
+[0004]                    Asl Compiler ID : "INTL"
+[0004]              Asl Compiler Revision : 20110623
+
+[0004]                 Local Apic Address : 00000000
+[0004]              Flags (decoded below) : 00000000
+                      PC-AT Compatibility : 0
+
+[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
+[0001]                             Length : 4C
+[0002]                           Reserved : 0000
+[0004]               CPU Interface Number : 00000000
+[0004]                      Processor UID : 00000000
+[0004]              Flags (decoded below) : 00000001
+                        Processor Enabled : 1
+[0004]           Parking Protocol Version : 00000000
+[0004]              Performance Interrupt : 00000000
+[0008]                     Parked Address : 0000000000000000
+[0008]                       Base Address : 000000002c02f000
+[0008]           Virtual GIC Base Address : 0
+[0008]               Hyp GIC Base Address : 0
+[0004]  Virtual GIC Maintenance Interrupt : 0
+[0008]                  RedistBaseAddress : 0
+[0008]                              MPIDR : 00000100
+
+[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
+[0001]                             Length : 4C
+[0002]                           Reserved : 0000
+[0004]               CPU Interface Number : 00000001
+[0004]                      Processor UID : 00000001
+[0004]              Flags (decoded below) : 00000001
+                          Processor Enabled : 1
+[0004]           Parking Protocol Version : 00000000
+[0004]              Performance Interrupt : 00000000
+[0008]                     Parked Address : 0000000000000000
+[0008]                       Base Address : 000000002c02f000
+[0008]           Virtual GIC Base Address : 0
+[0008]               Hyp GIC Base Address : 0
+[0004]  Virtual GIC Maintenance Interrupt : 0 
+[0008]                  RedistBaseAddress : 0
+[0008]                              MPIDR : 00000101
+
+[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
+[0001]                             Length : 4C
+[0002]                           Reserved : 0000
+[0004]               CPU Interface Number : 00000002
+[0004]                      Processor UID : 00000002
+[0004]              Flags (decoded below) : 00000001
+                          Processor Enabled : 1
+[0004]           Parking Protocol Version : 00000000
+[0004]              Performance Interrupt : 00000000
+[0008]                     Parked Address : 0000000000000000
+[0008]                       Base Address : 000000002c02f000
+[0008]           Virtual GIC Base Address : 0
+[0008]               Hyp GIC Base Address : 0
+[0004]  Virtual GIC Maintenance Interrupt : 0 
+[0008]                  RedistBaseAddress : 0
+[0008]                              MPIDR : 00000102
+
+[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
+[0001]                             Length : 4C
+[0002]                           Reserved : 0000
+[0004]               CPU Interface Number : 00000003
+[0004]                      Processor UID : 00000003
+[0004]              Flags (decoded below) : 00000001
+                          Processor Enabled : 1
+[0004]           Parking Protocol Version : 00000000
+[0004]              Performance Interrupt : 00000000
+[0008]                     Parked Address : 0000000000000000
+[0008]                       Base Address : 000000002c02f000
+[0008]           Virtual GIC Base Address : 0
+[0008]               Hyp GIC Base Address : 0
+[0004]  Virtual GIC Maintenance Interrupt : 0 
+[0008]                  RedistBaseAddress : 0
+[0008]                              MPIDR : 00000103
+
+[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
+[0001]                             Length : 4C
+[0002]                           Reserved : 0000
+[0004]               CPU Interface Number : 00000004
+[0004]                      Processor UID : 00000004
+[0004]              Flags (decoded below) : 00000001
+                          Processor Enabled : 1
+[0004]           Parking Protocol Version : 00000000
+[0004]              Performance Interrupt : 00000000
+[0008]                     Parked Address : 0000000000000000
+[0008]                       Base Address : 000000002c02f000
+[0008]           Virtual GIC Base Address : 0
+[0008]               Hyp GIC Base Address : 0
+[0004]  Virtual GIC Maintenance Interrupt : 0 
+[0008]                  RedistBaseAddress : 0
+[0008]                              MPIDR : 00000000
+
+[0001]                      Subtable Type : 0B [Generic Interrupt Controller]
+[0001]                             Length : 4C
+[0002]                           Reserved : 0000
+[0004]               CPU Interface Number : 00000005
+[0004]                      Processor UID : 00000005
+[0004]              Flags (decoded below) : 00000001
+                          Processor Enabled : 1
+[0004]           Parking Protocol Version : 00000000
+[0004]              Performance Interrupt : 00000000
+[0008]                     Parked Address : 0000000000000000
+[0008]                       Base Address : 000000002c02f000
+[0008]           Virtual GIC Base Address : 0
+[0008]               Hyp GIC Base Address : 0
+[0004]  Virtual GIC Maintenance Interrupt : 0 
+[0008]                  RedistBaseAddress : 0
+[0008]                              MPIDR : 00000001
+
+[0001]                      Subtable Type : 0C [Generic Interrupt Distributor]
+[0001]                             Length : 18
+[0002]                           Reserved : 0000
+[0004]              Local GIC Hardware ID : 00000000
+[0008]                       Base Address : 000000002c010000
+[0004]                     Interrupt Base : 00000000
+[0004]                           Reserved : 00000000
diff --git a/platforms/juno/dsdt.asl b/platforms/juno/dsdt.asl
new file mode 100644
index 0000000..fab03d7
--- /dev/null
+++ b/platforms/juno/dsdt.asl
@@ -0,0 +1,142 @@
+/*
+* Copyright (c) 2014, Graeme Gregory <graeme.gregory@linaro.org>
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* 
+* 1. Redistributions of source code must retain the above copyright 
+* notice, this list of conditions and the following disclaimer.
+* 
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the 
+* documentation and/or other materials provided with the distribution.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* 
+* NB: This License is also known as the "BSD 2-Clause License".
+* 
+*
+* [DSDT] Description of Juno
+*
+*/
+
+DefinitionBlock (
+	"dsdt.aml",		// output filename
+	"DSDT",			// table signature
+	2,			// DSDT compliance revision
+	"LINARO",		// OEM ID
+	"VOLDEMOR",		// table ID
+	0x00000001)		// OEM revision
+{
+	Scope (\_SB)
+	{
+		Method (_OSC, 4, NotSerialized)
+		{
+			/* Platform-Wide OSPM Capabilities */
+			If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+			{
+				/* APEI support unconditionally */
+				Return (Arg3)
+			} Else {
+				CreateDWordField (Arg3, Zero, CDW1)
+				/* Set invalid UUID error bit */
+				Or (CDW1, 0x04, CDW1)
+				Return (Arg3)
+			}
+		}
+
+		// apb_pclk
+		Device (CLK0) {
+			Name (_HID, "LNRO0008")
+			Name (_UID, 0)
+
+			Name (_PRP, Package() {
+				Package(2) {"#clock-cells", 0},
+				Package(2) {"clock-frequency", 100000000}
+			})
+
+		}
+
+		// uartclk
+		Device (CLK1) {
+			Name (_HID, "LNRO0008")
+			Name (_UID, 1)
+
+			Name (_PRP, Package() {
+				Package(2) {"#clock-cells", 0},
+				Package(2) {"clock-frequency", 7273800}
+			})
+		}
+
+		// uartclk
+		Device (CLK2) {
+			Name (_HID, "LNRO0008")
+			Name (_UID, 1)
+
+			Name (_PRP, Package() {
+				Package(2) {"#clock-cells", 0},
+				Package(2) {"clock-frequency", 25000000}
+			})
+		}
+
+		Device (NET0) {
+			Name (_HID, "LNRO001B")
+			Name (_UID, 0)
+			
+			Name (_PRP, Package() {
+				Package(2) {"phy-mode", "mii"},
+				Package(2) {"reg-io-width", 4},
+				Package(2) {"smsc,irq-active-high", 1},
+				Package(2) {"smsc,irq-push-pull", 1},
+			})
+			
+			Method (_CRS, 0x0, Serialized) {
+				Name (RBUF, ResourceTemplate() {
+					Memory32Fixed (ReadWrite,0x18000000 , 0x10000)
+					Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0xC0}
+				})
+				Return (RBUF)
+			}
+		}
+		
+		Device (AMBA) {
+			Name (_HID, "LNRO001A")
+			Name (_UID, 0)
+
+			Name (_PRP, Package() {
+				Package(2) {"clocks", Package () {"\\_SB.CLK0"}}
+			})
+
+			Device (SER0) {
+				Name (_HID, "LNRO000A")
+				Name (_ADR, 0x7ff80000)
+				Name (_UID, 0)
+
+				Method (_CRS, 0x0, Serialized) {
+					Name (RBUF, ResourceTemplate() {
+						Memory32Fixed (ReadWrite, 0x7ff80000, 0x1000)
+						Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x73}
+					})
+					Return (RBUF)
+				}
+
+				Name (_PRP, Package() {
+					Package(2) {"clocks", Package () {"\\_SB.CLK1"}}
+				})
+			} // End of SER0
+		} // End of AMBA
+	} // End of _SB
+}
diff --git a/platforms/juno/facp.asl b/platforms/juno/facp.asl
new file mode 100644
index 0000000..f2bf833
--- /dev/null
+++ b/platforms/juno/facp.asl
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright 
+ * notice, this list of conditions and the following disclaimer.
+ * 
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the 
+ * documentation and/or other materials provided with the distribution.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * 
+ * NB: This License is also known as the "BSD 2-Clause License".
+ * 
+ *
+ * [FACP] ACPI Table
+ *
+ */
+
+[0004]                          Signature : "FACP"
+[0004]                       Table Length : 0000010C
+[0001]                           Revision : 05
+[0001]                           Checksum : 18
+[0006]                             Oem ID : "LINARO"
+[0008]                       Oem Table ID : "VOLDEMOR"
+[0004]                       Oem Revision : 00000000
+[0004]                    Asl Compiler ID : "INTL"
+[0004]              Asl Compiler Revision : 20111123
+
+[0004]                       FACS Address : 00000000
+[0004]                       DSDT Address : 00000010
+[0001]                              Model : 00
+[0001]                         PM Profile : 04          /* Enterprise Server */
+[0002]                      SCI Interrupt : 0000
+[0004]                   SMI Command Port : 00000000
+[0001]                  ACPI Enable Value : 00
+[0001]                 ACPI Disable Value : 00
+[0001]                     S4BIOS Command : 00
+[0001]                    P-State Control : 00
+[0004]           PM1A Event Block Address : 00000001
+[0004]           PM1B Event Block Address : 00000000
+[0004]         PM1A Control Block Address : 00000001
+[0004]         PM1B Control Block Address : 00000000
+[0004]          PM2 Control Block Address : 00000001
+[0004]             PM Timer Block Address : 00000001
+[0004]                 GPE0 Block Address : 00000001
+[0004]                 GPE1 Block Address : 00000000
+[0001]             PM1 Event Block Length : 04
+[0001]           PM1 Control Block Length : 02
+[0001]           PM2 Control Block Length : 01
+[0001]              PM Timer Block Length : 04
+[0001]                  GPE0 Block Length : 08
+[0001]                  GPE1 Block Length : 00
+[0001]                   GPE1 Base Offset : 00
+[0001]                       _CST Support : 00
+[0002]                         C2 Latency : 0000
+[0002]                         C3 Latency : 0000
+[0002]                     CPU Cache Size : 0000
+[0002]                 Cache Flush Stride : 0000
+[0001]                  Duty Cycle Offset : 00
+[0001]                   Duty Cycle Width : 00
+[0001]                RTC Day Alarm Index : 00
+[0001]              RTC Month Alarm Index : 00
+[0001]                  RTC Century Index : 00
+[0002]         Boot Flags (decoded below) : 0000
+            Legacy Devices Supported (V2) : 0
+         8042 Present on ports 60/64 (V2) : 0
+                     VGA Not Present (V4) : 0
+                   MSI Not Supported (V4) : 0
+             PCIe ASPM Not Supported (V4) : 0
+                CMOS RTC Not Present (V5) : 0
+[0001]                           Reserved : 00
+[0004]              Flags (decoded below) : 00000000
+   WBINVD instruction is operational (V1) : 1
+           WBINVD flushes all caches (V1) : 1
+                 All CPUs support C1 (V1) : 0
+               C2 works on MP system (V1) : 0
+         Control Method Power Button (V1) : 1
+         Control Method Sleep Button (V1) : 1
+     RTC wake not in fixed reg space (V1) : 0
+         RTC can wake system from S4 (V1) : 0
+                     32-bit PM Timer (V1) : 0
+                   Docking Supported (V1) : 0
+            Reset Register Supported (V2) : 0
+                         Sealed Case (V3) : 0
+                 Headless - No Video (V3) : 1
+     Use native instr after SLP_TYPx (V3) : 0
+           PCIEXP_WAK Bits Supported (V4) : 0
+                  Use Platform Timer (V4) : 0
+            RTC_STS valid on S4 wake (V4) : 0
+             Remote Power-on capable (V4) : 1
+              Use APIC Cluster Model (V4) : 0
+  Use APIC Physical Destination Mode (V4) : 0
+                    Hardware Reduced (V5) : 1
+                   Low Power S0 Idle (V5) : 1
+
+[0012]                     Reset Register : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 08
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 01 [Byte Access:8]
+[0008]                            Address : 0000000000000001
+
+[0001]               Value to cause reset : 00
+[0002]      ARM_BOOT_ARCH (decoded below) : 0001
+                            Use PSCI 0.2+ : 1
+                             PSCI Use HVC : 0
+[0001]                FADT Minor Revision : 01
+[0008]                       FACS Address : 0000000000000000
+[0008]                       DSDT Address : 0000000000000010
+[0012]                   PM1A Event Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 20
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 02 [Word Access:16]
+[0008]                            Address : 0000000000000001
+
+[0012]                   PM1B Event Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 00
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 00 [Undefined/Legacy]
+[0008]                            Address : 0000000000000000
+
+[0012]                 PM1A Control Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 10
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 02 [Word Access:16]
+[0008]                            Address : 0000000000000001
+
+[0012]                 PM1B Control Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 00
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 00 [Undefined/Legacy]
+[0008]                            Address : 0000000000000000
+
+[0012]                  PM2 Control Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 08
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 00 [Undefined/Legacy]
+[0008]                            Address : 0000000000000001
+
+[0012]                     PM Timer Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 20
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 03 [DWord Access:32]
+[0008]                            Address : 0000000000000001
+
+[0012]                         GPE0 Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 80
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 01 [Byte Access:8]
+[0008]                            Address : 0000000000000001
+
+[0012]                         GPE1 Block : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 00
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 00 [Undefined/Legacy]
+[0008]                            Address : 0000000000000000
+
+
+[0012]             Sleep Control Register : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 08
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 01 [Byte Access:8]
+[0008]                            Address : 0000000000000000
+
+[0012]              Sleep Status Register : [Generic Address Structure]
+[0001]                           Space ID : 01 [SystemIO]
+[0001]                          Bit Width : 08
+[0001]                         Bit Offset : 00
+[0001]               Encoded Access Width : 01 [Byte Access:8]
+[0008]                            Address : 0000000000000000
+
diff --git a/platforms/juno/gtdt.aml b/platforms/juno/gtdt.aml
new file mode 100644
index 0000000..e953878
--- /dev/null
+++ b/platforms/juno/gtdt.aml
diff --git a/platforms/juno/gtdt.asl b/platforms/juno/gtdt.asl
new file mode 100644
index 0000000..16b4cd9
--- /dev/null
+++ b/platforms/juno/gtdt.asl
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+ *                     Hanjun Guo <hanjun.guo@linaro.org>
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright 
+ * notice, this list of conditions and the following disclaimer.
+ * 
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the 
+ * documentation and/or other materials provided with the distribution.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * 
+ * NB: This License is also known as the "BSD 2-Clause License".
+ * 
+ *
+ * [GTDT] Generic Timer Description Table
+ * Format: [ByteLength]  FieldName : HexFieldValue
+ *
+ */
+
+[0004]                          Signature : "GTDT"
+[0004]                       Table Length : 00000050
+[0001]                           Revision : 02
+[0001]                           Checksum : F1
+[0006]                             Oem ID : "LINARO"
+[0008]                       Oem Table ID : "VOLDEMOR"
+[0004]                       Oem Revision : 00000001
+[0004]                    Asl Compiler ID : "INTL"
+[0004]              Asl Compiler Revision : 20110623
+
+/* The 64-bit physical address at which the Counter Control block is located. */
+[0008]    CntControlBase Physical Address : 0000000000000000
+[0004]				 Reserved : 00000000
+
+/* In Juno board's dts file, the last cell of interrupts
+ * is 0xff01, it means its cpu mask is FF, and trigger type
+ * and flag is 1 = low-to-high edge triggered.
+ * 
+ * so in ACPI the Trigger Mode is 1 - Edge triggered, and 
+ * Polarity is 0 - Active high as ACPI spec describled.
+ *
+ * using direct mapping for hwirqs, it means that we using
+ * ID [16, 31] for PPI, not [0, 15] used in FDT.
+ */
+[0004]               Secure EL1 Interrupt : 0000001d
+[0004]         SEL1 Flags (decoded below) : 00000001
+                             Trigger Mode : 1
+                                 Polarity : 0
+				Always-on : 0
+
+[0004]           Non-Secure EL1 Interrupt : 0000001e
+[0004]        NSEL1 Flags (decoded below) : 00000001
+                             Trigger Mode : 1
+                                 Polarity : 0
+				Always-on : 0
+
+[0004]            Virtual Timer Interrupt : 0000001b
+[0004]           VT Flags (decoded below) : 00000001
+                             Trigger Mode : 1
+                                 Polarity : 0
+				Always-on : 0
+
+[0004]           Non-Secure EL2 Interrupt : 0000001a
+[0004]        NSEL2 Flags (decoded below) : 00000001
+                             Trigger Mode : 1
+                                 Polarity : 0
+				Always-on : 0
+
+/* The 64-bit physical address at which the Counter Read block is located */
+[0008]	     CntReadBase Physical address : 0000000000000000
+
+[0004]		     Platform Timer Count : 00000001
+[0004]              Platform Timer Offset : 0000005C
+
+/* Memory-mapped GT (Generic Timer) structures */
+[0001]				     Type : 00
+[0002]				   Length : 003C
+[0001]				 Reserved : 0
+[0008]			       CntCtlBase : 000000002a810000
+[0004]		     GT Block Timer Count : 00000001
+[0004]		    GT Block Timer Offset : 00000010
+
+/* One frame is available */
+[0001]			     GT Frame Num : 00
+[0003]				 Reserved : 000000
+[0008]		     GTx Physical Address : 000000002a830000
+[0008]		 GTx Physical EL0 Address : FFFFFFFFFFFFFFFF
+[0004]	     GTx Physical Timer Interrupt : 0000004C /* 60+16 */
+[0004]           GTx Physical Timer Flags : 00000000 /* Active high level-sensitive */
+                             Trigger Mode : 0
+                                 Polarity : 0
+				   Secure : 0
+				Always On : 0
+/* No virtual timer */
+[0004]        GTx Virtual Timer Interrupt : 00000000
+[0004]            GTx Virtual Timer Flags : 00000000
+[0004]                   GTx Common Flags : 00000000
+                             Secure Timer : 0
+                                Always-on : 0
+
diff --git a/platforms/juno/gtdt.dsl b/platforms/juno/gtdt.dsl
new file mode 100644
index 0000000..aafb588
--- /dev/null
+++ b/platforms/juno/gtdt.dsl
@@ -0,0 +1,88 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140424-64 [Jul 24 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ * 
+ * Disassembly of ArmPlatformPkg/ArmJunoPkg/AcpiTables/juno/gtdt.aml, Thu Jul 24 12:49:51 2014
+ *
+ * ACPI Data Table [GTDT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
+ */
+
+[000h 0000   4]                    Signature : "GTDT"    [Generic Timer Description Table]
+[004h 0004   4]                 Table Length : 0000009C
+[008h 0008   1]                     Revision : 02
+[009h 0009   1]                     Checksum : B4
+[00Ah 0010   6]                       Oem ID : "LINARO"
+[010h 0016   8]                 Oem Table ID : "VOLDEMOR"
+[018h 0024   4]                 Oem Revision : 00000001
+[01Ch 0028   4]              Asl Compiler ID : "INTL"
+[020h 0032   4]        Asl Compiler Revision : 20140424
+
+[024h 0036   8]        Counter Block Address : 0000000000000000
+[02Ch 0044   4]                     Reserved : 00000000
+
+[030h 0048   4]         Secure EL1 Interrupt : 0000001D
+[034h 0052   4]    EL1 Flags (decoded below) : 00000001
+                                Trigger Mode : 1
+                                    Polarity : 0
+                                   Always On : 0
+
+[038h 0056   4]     Non-Secure EL1 Interrupt : 0000001E
+[03Ch 0060   4]   NEL1 Flags (decoded below) : 00000001
+                                Trigger Mode : 1
+                                    Polarity : 0
+                                   Always On : 0
+
+[040h 0064   4]      Virtual Timer Interrupt : 0000001B
+[044h 0068   4]     VT Flags (decoded below) : 00000001
+                                Trigger Mode : 1
+                                    Polarity : 0
+                                   Always On : 0
+
+[048h 0072   4]     Non-Secure EL2 Interrupt : 0000001A
+[04Ch 0076   4]   NEL2 Flags (decoded below) : 00000001
+                                Trigger Mode : 1
+                                    Polarity : 0
+                                   Always On : 0
+[050h 0080   8]   Counter Read Block Address : 0000000000000000
+
+[058h 0088   4]         Platform Timer Count : 00000001
+[05Ch 0092   4]        Platform Timer Offset : 0000005C
+
+[060h 0096   1]                Subtable Type : 00 [GT Block]
+[061h 0097   2]                       Length : 003C
+[063h 0099   1]                     Reserved : 00
+[064h 0100   8]             GT Block Address : 000000002A810000
+[06Ch 0108   4]               GT Block Count : 00000001
+[070h 0112   4]              GT Block Offset : 00000010
+
+[074h 0116   1]              GT Frame Number : 00
+[075h 0117   3]                     Reserved : 000000
+[078h 0120   8]                  GTx Address : 000000002A830000
+[080h 0128   8]              GTx EL0 Address : FFFFFFFFFFFFFFFF
+[088h 0136   4]          GTx Timer Interrupt : 0000004C
+[08Ch 0140   4] GTx Timer Flags (decoded below) : 00000000
+                                Trigger Mode : 0
+                                    Polarity : 0
+[090h 0144   4]  GTx Virtual Timer Interrupt : 00000000
+[094h 0148   4] GTx Virtual Timer Flags (decoded below) : 00000000
+                                Trigger Mode : 0
+                                    Polarity : 0
+[098h 0152   4] GTx Common Flags (decoded below) : 00000000
+                                      Secure : 0
+                                   Always On : 0
+
+Raw Table Data: Length 156 (0x9C)
+
+  0000: 47 54 44 54 9C 00 00 00 02 B4 4C 49 4E 41 52 4F  GTDT......LINARO
+  0010: 56 4F 4C 44 45 4D 4F 52 01 00 00 00 49 4E 54 4C  VOLDEMOR....INTL
+  0020: 24 04 14 20 00 00 00 00 00 00 00 00 00 00 00 00  $.. ............
+  0030: 1D 00 00 00 01 00 00 00 1E 00 00 00 01 00 00 00  ................
+  0040: 1B 00 00 00 01 00 00 00 1A 00 00 00 01 00 00 00  ................
+  0050: 00 00 00 00 00 00 00 00 01 00 00 00 5C 00 00 00  ............\...
+  0060: 00 3C 00 00 00 00 81 2A 00 00 00 00 01 00 00 00  .<.....*........
+  0070: 10 00 00 00 00 00 00 00 00 00 83 2A 00 00 00 00  ...........*....
+  0080: FF FF FF FF FF FF FF FF 4C 00 00 00 00 00 00 00  ........L.......
+  0090: 00 00 00 00 00 00 00 00 00 00 00 00              ............
diff --git a/platforms/juno/juno.manifest b/platforms/juno/juno.manifest
new file mode 100644
index 0000000..b21dbbd
--- /dev/null
+++ b/platforms/juno/juno.manifest
@@ -0,0 +1,6 @@
+
+apic: apic.asl
+dsdt: dsdt.asl
+facp: facp.asl
+gtdt: gtdt.asl
+