aboutsummaryrefslogtreecommitdiff
path: root/core/arch/arm/plat-rockchip
diff options
context:
space:
mode:
Diffstat (limited to 'core/arch/arm/plat-rockchip')
-rw-r--r--core/arch/arm/plat-rockchip/core_pos_a32.S2
-rw-r--r--core/arch/arm/plat-rockchip/plat_init.S3
2 files changed, 0 insertions, 5 deletions
diff --git a/core/arch/arm/plat-rockchip/core_pos_a32.S b/core/arch/arm/plat-rockchip/core_pos_a32.S
index e5317214..5994c469 100644
--- a/core/arch/arm/plat-rockchip/core_pos_a32.S
+++ b/core/arch/arm/plat-rockchip/core_pos_a32.S
@@ -8,13 +8,11 @@
#include <arm32_macros.S>
FUNC get_core_pos_mpidr , :
-UNWIND( .fnstart)
/*
* Because mpidr is designed mistake in hardware, ie. core0 is 0xf00,
* core1 is 0xf01..., so we need implement the function to correct this.
*/
and r0, r0, #MPIDR_CPU_MASK
bx lr
-UNWIND( .fnend)
END_FUNC get_core_pos_mpidr
diff --git a/core/arch/arm/plat-rockchip/plat_init.S b/core/arch/arm/plat-rockchip/plat_init.S
index 6855ee09..fb084afd 100644
--- a/core/arch/arm/plat-rockchip/plat_init.S
+++ b/core/arch/arm/plat-rockchip/plat_init.S
@@ -8,14 +8,11 @@
#include <arm32_macros.S>
FUNC plat_cpu_reset_early , :
-UNWIND( .fnstart)
/* Enable SMP bit */
read_actlr r0
orr r0, r0, #ACTLR_SMP
write_actlr r0
bx lr
-
-UNWIND( .fnend)
END_FUNC plat_cpu_reset_early