4 files changed, 0 insertions, 17 deletions
diff --git a/core/arch/arm/plat-imx/a7_plat_init.S b/core/arch/arm/plat-imx/a7_plat_init.S
index 50c72fee..f96a18ac 100644
--- a/core/arch/arm/plat-imx/a7_plat_init.S
+++ b/core/arch/arm/plat-imx/a7_plat_init.S
@@ -31,8 +31,6 @@
  * Trap CPU in case of error.
  */
 FUNC plat_cpu_reset_early , :
-UNWIND(	.fnstart)
-
 	/*
 	 * DDI: Disable dual issue [bit28=0]
 	 * DDVM: Disable Distributed Virtual Memory transactions [bit15=0]
@@ -49,13 +47,10 @@ UNWIND(	.fnstart)
 	write_nsacr r0
 
 	bx	lr
-UNWIND(	.fnend)
 END_FUNC plat_cpu_reset_early
 
 FUNC get_core_pos_mpidr , :
-UNWIND(	.fnstart)
 	/* Drop ClusterId. There is no SoCs with more than 4 A7 Cores. */
 	and	r0, r0, #MPIDR_CPU_MASK
 	bx	lr
-UNWIND(	.fnend)
 END_FUNC get_core_pos_mpidr
diff --git a/core/arch/arm/plat-imx/a9_plat_init.S b/core/arch/arm/plat-imx/a9_plat_init.S
index 137fb270..4050684c 100644
--- a/core/arch/arm/plat-imx/a9_plat_init.S
+++ b/core/arch/arm/plat-imx/a9_plat_init.S
@@ -55,8 +55,6 @@
  * Trap CPU in case of error.
  */
 FUNC plat_cpu_reset_early , :
-UNWIND(	.fnstart)
-
 	/*
 	 * Under very rare timing circumstances, transition into streaming
 	 * mode might create a data corruption
@@ -137,5 +135,4 @@ UNWIND(	.fnstart)
 	write_pcr r0
 
 	mov pc, lr
-UNWIND(	.fnend)
 END_FUNC plat_cpu_reset_early
diff --git a/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S b/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S
index 1f750030..6894be37 100644
--- a/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S
+++ b/core/arch/arm/plat-imx/pm/psci-cpuidle-imx7.S
@@ -552,7 +552,6 @@
 .extern iram_tlb_phys_addr
 
 FUNC imx7d_low_power_idle, :
-UNWIND( .fnstart)
 	push	{r0 - r12}
 
 	/* get necessary info from pm_info */
@@ -727,8 +726,6 @@ wakeup_skip_lpi_flow:
 
 	/* Restore registers */
 	bx	lr
-
-UNWIND( .fnend)
 END_FUNC imx7d_low_power_idle
 
 /*
@@ -736,7 +733,6 @@ END_FUNC imx7d_low_power_idle
  * This maybe changed in future.
  */
 FUNC v7_cpu_resume, :
-UNWIND( .fnstart)
 	mov     r0, #0	@ ; write the cache size selection register to be
 	write_csselr r0	@ ; sure we address the data cache
 	isb		@ ; isb to sync the change to the cachesizeid reg
@@ -766,5 +762,4 @@ _inv_nextline:
 	blx plat_cpu_reset_early
 
 	b	sm_pm_cpu_resume
-UNWIND( .fnend)
 END_FUNC v7_cpu_resume
diff --git a/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S b/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S
index 200241fb..06910127 100644
--- a/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S
+++ b/core/arch/arm/plat-imx/pm/psci-suspend-imx7.S
@@ -455,7 +455,6 @@
 	.endm
 
 FUNC imx7_suspend, :
-UNWIND(	.fnstart)
 UNWIND(	.cantunwind)
 	push	{r4-r12}
 
@@ -656,11 +655,9 @@ dsm_ddr_self_refresh_out:
 dsm_ddr_retention_out:
 
 	bx	lr
-UNWIND(	.fnend)
 END_FUNC imx7_suspend
 
 FUNC ca7_cpu_resume, :
-UNWIND(	.fnstart)
 UNWIND(	.cantunwind)
 	mov     r0, #0	@ ; write the cache size selection register to be
 	write_csselr r0	@ ; sure we address the data cache
@@ -692,5 +689,4 @@ _inv_nextline:
 	blx	plat_cpu_reset_early
 
 	b	sm_pm_cpu_resume
-UNWIND(	.fnend)
 END_FUNC ca7_cpu_resume