RZN1: reg_auth: refactor system register access authorization

Refactor the code by moving the list of register auth
to an external header file in RZN1 platform directory.
Use the list as a blacklist to allow everything by default
and only explicitly block critical registers.

Signed-off-by: Mourad Goumrhar <Mourad.Goumrhar@se.com>
Change-Id: Ib0a7ffe10c3516a72d6cdcb9abef37484f2dd6ae

1 files changed, 14 insertions, 264 deletions

diff --git a/core/arch/arm/sm/sm.c b/core/arch/arm/sm/sm.c
index 9fd5430e..6b08d767 100644
--- a/core/arch/arm/sm/sm.c
+++ b/core/arch/arm/sm/sm.c
@@ -16,256 +16,11 @@
 #include "sm_private.h"
 #include <console.h>
 #include <mm/core_memprot.h>
+#include <rzn1_regauth.h>
 
 #define OEM_SVC_PUTC        0x83000001
 #define OEM_SVC_SYSREG      0x83000010
 
-typedef const struct {
-	unsigned long paddr;
-	unsigned long rmask;
-	unsigned long wmask;
-} regauth_t;
-
-static regauth_t regauth[] = {
-	// This list must be sorted by paddr
-	{ .paddr=0x4000c000, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_USB
-	{ .paddr=0x4000c008, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_SDIO0
-	{ .paddr=0x4000c00c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO0
-	{ .paddr=0x4000c010, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_SDIO0
-	{ .paddr=0x4000c01c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_USB
-	{ .paddr=0x4000c020, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_USB
-	{ .paddr=0x4000c024, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_CRYPTO
-	{ .paddr=0x4000c02c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_MSEBI
-	{ .paddr=0x4000c034, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_0
-	{ .paddr=0x4000c03c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_1
-	{ .paddr=0x4000c040, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_FW1
-	{ .paddr=0x4000c044, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_FW2
-	{ .paddr=0x4000c048, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PGEXT2_PR6DIV
-	{ .paddr=0x4000c04c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_DMA
-	{ .paddr=0x4000c050, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_NFLASH
-	{ .paddr=0x4000c054, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_QSPI0
-	{ .paddr=0x4000c05c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_NFLASH
-	{ .paddr=0x4000c060, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_QSPI0
-	{ .paddr=0x4000c064, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRCTRL_DDRC
-	{ .paddr=0x4000c068, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_EETH
-	{ .paddr=0x4000c06c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_MAC0
-	{ .paddr=0x4000c070, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_MAC1
-	{ .paddr=0x4000c074, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_DDRC
-	{ .paddr=0x4000c07c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_MAC1
-	{ .paddr=0x4000c080, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_ECAT
-	{ .paddr=0x4000c084, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SERCOS
-	{ .paddr=0x4000c090, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_HSR
-	{ .paddr=0x4000c094, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SWITCHDIV
-	{ .paddr=0x4000c0a0, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_DMAMUX
-	{ .paddr=0x4000c0c0, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_USBSTAT
-	{ .paddr=0x4000c0c4, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_SDIO1
-	{ .paddr=0x4000c0c8, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO1
-	{ .paddr=0x4000c0e0, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_OPPDIV
-	{ .paddr=0x4000c0e4, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_CA7DIV
-	{ .paddr=0x4000c0e8, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG2_25MHZ
-	{ .paddr=0x4000c0ec, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR2
-	{ .paddr=0x4000c0f0, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG3_48MHZ
-	{ .paddr=0x4000c0f4, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG4_FW
-	{ .paddr=0x4000c0f8, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR2DIV
-	{ .paddr=0x4000c0fc, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR3
-	{ .paddr=0x4000c100, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR3DIV
-	{ .paddr=0x4000c104, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR4
-	{ .paddr=0x4000c108, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR4DIV
-	{ .paddr=0x4000c10c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG4_PR1
-	{ .paddr=0x4000c110, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG4_PR1DIV
-	{ .paddr=0x4000c114, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PGEXT2_PR6
-	{ .paddr=0x4000c118, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG5_PR5
-	{ .paddr=0x4000c11c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG5_PR5DIV
-	{ .paddr=0x4000c120, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_RSTEN
-	{ .paddr=0x4000c124, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_QSPI0DIV
-	{ .paddr=0x4000c128, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO0DIV
-	{ .paddr=0x4000c12c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO1DIV
-	{ .paddr=0x4000c130, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SWITCH
-	{ .paddr=0x4000c134, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_ADCDIV
-	{ .paddr=0x4000c138, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_I2CDIV
-	{ .paddr=0x4000c13c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_UARTDIV
-	{ .paddr=0x4000c140, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_RTC
-	{ .paddr=0x4000c148, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_NFLASHDIV
-	{ .paddr=0x4000c150, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_MOTORDIV
-	{ .paddr=0x4000c154, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_ROM
-	{ .paddr=0x4000c15c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_PG2_25MHZ
-	{ .paddr=0x4000c160, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_PG3_48MHZ
-	{ .paddr=0x4000c174, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_CM3
-	{ .paddr=0x4000c184, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_RINCTRL
-	{ .paddr=0x4000c188, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SWITCHCTRL
-	{ .paddr=0x4000c18c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_HWRTOS
-	{ .paddr=0x4000c190, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_HWRTOS_MDCDIV
-	{ .paddr=0x4000c19c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_VERSION
-	{ .paddr=0x40060000, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40060004, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40060008, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x4006000c, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40060010, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40064000, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064004, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064010, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064014, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064018, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006401c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064020, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006402c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064030, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064034, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064038, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006403c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064040, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064054, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064060, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006406c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064070, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064074, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064078, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006407c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064080, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006409c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x400640f4, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x400640f8, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x400640fc, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40067000, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067004, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006700c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067028, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067034, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067038, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006703c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067040, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067044, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067048, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006704c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067050, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067058, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006705c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067060, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067064, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067068, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006706c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067070, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067074, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067078, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006708c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067090, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067094, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067098, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006709c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670a0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670a4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670a8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670ac, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670b0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670b4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670b8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670bc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670c0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670c4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670c8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670cc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670d0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670d4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670d8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670dc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670e0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670e4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670e8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670ec, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670f0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670f8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670fc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067100, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067104, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067108, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006710c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067110, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067114, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067118, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006711c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067120, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067124, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067128, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006712c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067130, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067134, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067138, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006713c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067140, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067144, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067148, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006714c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067150, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067154, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067158, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006715c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067160, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067164, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067168, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006716c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067170, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067174, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067178, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006717c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067180, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067184, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067188, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006718c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067190, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067194, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067198, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006719c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671a0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671b4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671b8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671bc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671c0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671c4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671c8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671cc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671d0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671dc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671e0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671e4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671e8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671fc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067200, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067204, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067208, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006720c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067210, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067214, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067218, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006721c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067220, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067224, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067228, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006722c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067230, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067234, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067238, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006723c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067240, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067244, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006724c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067250, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067254, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067258, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006725c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067260, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067264, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067268, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006726c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067270, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067274, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067278, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006727c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067280, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067284, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067288, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067400, .rmask=~0UL, .wmask=~0UL },	// PINMUX lock
-};
-
 static regauth_t *get_regauth(unsigned long paddr)
 {
 	unsigned int min = 0;
@@ -285,36 +40,31 @@ static uint32_t oem_sysreg (unsigned long addr, unsigned long mask, uint32_t *pv
 	regauth_t *auth;
 	volatile unsigned long *reg;
 
-	// Handle unknown registers
+	// Allow registers not in the list
 	if ( !(auth = get_regauth(addr)) ) {
-		if ( 1 ) { // Troubleshoot code
-			static regauth_t pass = {.rmask = ~0UL,.wmask = ~0UL};
-			auth = &pass;
-			DMSG("Allow %s access to unknown register at 0x%lx", mask ? "write" : "read ", addr);
-		} else {
-			return 1;
-		}
+		static regauth_t pass = {.rmask = ~0UL,.wmask = ~0UL};
+		auth = &pass;
 	}
 
 	// Sanity check
 	reg = (unsigned long*)core_mmu_get_va(addr, MEM_AREA_IO_SEC);
-	if ( mask & ~auth->wmask ) {
-		DMSG("Blocking write of 0x%lx to register 0x%lx (0x%lx)", *pvalue, addr, *reg);
-	}
 
 	// Perform allowed operations
 	if (mask) { // Write
 		mask &= auth->wmask;
-		//if (mask) { DMSG("Write @%lx value 0x%lx",addr,*pvalue); }
-		if ( mask == ~0UL ) { // Full write
+		if ( mask == 0UL ) { // Bits to write are protected
+			DMSG("Blocking write of 0x%x to register 0x%lx (0x%lx)", *pvalue, addr, *reg);
+		} else if ( mask == ~0UL ) { // Full write
 			*reg = *pvalue;
-		} else
-		if (mask) { // Partial write with read ahead
-			*reg = *pvalue = ( *reg & ~mask ) | ( *pvalue & mask );
+		} else { // Partial write with read ahead
+			*reg = ( *reg & ~mask ) | ( *pvalue & mask );
 		}
 	} else { // Read
-		*pvalue = *reg & auth->rmask;
-		//DMSG("Read  @%lx value 0x%lx",addr,*pvalue);
+		if ( auth->rmask == 0UL ) {
+			DMSG("Blocking read of register 0x%lx (0x%lx)", addr, *reg);
+		} else {
+			*pvalue = *reg & auth->rmask;
+		}
 	}
 	return 0;
 }