RZN1: reg_auth: refactor system register access authorization

Refactor the code by moving the list of register auth
to an external header file in RZN1 platform directory.
Use the list as a blacklist to allow everything by default
and only explicitly block critical registers.

Signed-off-by: Mourad Goumrhar <Mourad.Goumrhar@se.com>
Change-Id: Ib0a7ffe10c3516a72d6cdcb9abef37484f2dd6ae

2 files changed, 294 insertions, 264 deletions

diff --git a/core/arch/arm/plat-rzn1/rzn1_regauth.h b/core/arch/arm/plat-rzn1/rzn1_regauth.h
new file mode 100644
index 00000000..3c308c45
--- /dev/null
+++ b/core/arch/arm/plat-rzn1/rzn1_regauth.h
@@ -0,0 +1,280 @@
+#ifndef _RZN1_REGAUTH_H
+#define _RZN1_REGAUTH_H
+
+
+typedef const struct {
+	unsigned long paddr;
+	unsigned long rmask;
+	unsigned long wmask;
+} regauth_t;
+
+static regauth_t regauth[] = {
+	// This list must be sorted by paddr
+	/* OTP */
+	{ .paddr=0x40007000,	.rmask=0UL,	.wmask=0UL	}, /* OTPWCTRL */
+	/* System Controller */
+	{ .paddr=0x4000C064,	.rmask=0xFFFFFFFF,	.wmask=0xFFFFFFE0	}, /* PWRCTRL_DDRC */
+	{ .paddr=0x4000C204,	.rmask=0x0UL,	.wmask=0x0UL	}, /* BOOTADDR */
+	/* DDR CTRL */
+	{ .paddr=0x4000D16C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_91 */
+	{ .paddr=0x4000D170,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_92 */
+	{ .paddr=0x4000D174,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_93 */
+	{ .paddr=0x4000D178,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_94 */
+	{ .paddr=0x4000D17C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_95 */
+	{ .paddr=0x4000D180,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_96 */
+	{ .paddr=0x4000D184,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_97 */
+	{ .paddr=0x4000D188,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_98 */
+	{ .paddr=0x4000D18C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_99 */
+	{ .paddr=0x4000D190,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_100 */
+	{ .paddr=0x4000D194,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_101 */
+	{ .paddr=0x4000D198,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_102 */
+	{ .paddr=0x4000D19C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_103 */
+	{ .paddr=0x4000D1A0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_104 */
+	{ .paddr=0x4000D1A4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_105 */
+	{ .paddr=0x4000D1A8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_106 */
+	{ .paddr=0x4000D1AC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_107 */
+	{ .paddr=0x4000D1B0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_108 */
+	{ .paddr=0x4000D1B4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_109 */
+	{ .paddr=0x4000D1B8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_110 */
+	{ .paddr=0x4000D1BC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_111 */
+	{ .paddr=0x4000D1C0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_112 */
+	{ .paddr=0x4000D1C4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_113 */
+	{ .paddr=0x4000D1C8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_114 */
+	{ .paddr=0x4000D1CC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_115 */
+	{ .paddr=0x4000D1D0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_116 */
+	{ .paddr=0x4000D1D4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_117 */
+	{ .paddr=0x4000D1D8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_118 */
+	{ .paddr=0x4000D1DC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_119 */
+	{ .paddr=0x4000D1E0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_120 */
+	{ .paddr=0x4000D1E4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_121 */
+	{ .paddr=0x4000D1E8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_122 */
+	{ .paddr=0x4000D1EC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_123 */
+	{ .paddr=0x4000D1F0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_124 */
+	{ .paddr=0x4000D1F4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_125 */
+	{ .paddr=0x4000D1F8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_126 */
+	{ .paddr=0x4000D1FC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_127 */
+	{ .paddr=0x4000D200,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_128 */
+	{ .paddr=0x4000D204,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_129 */
+	{ .paddr=0x4000D208,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_130 */
+	{ .paddr=0x4000D20C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_131 */
+	{ .paddr=0x4000D210,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_132 */
+	{ .paddr=0x4000D214,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_133 */
+	{ .paddr=0x4000D218,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_134 */
+	{ .paddr=0x4000D21C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_135 */
+	{ .paddr=0x4000D220,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_136 */
+	{ .paddr=0x4000D224,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_137 */
+	{ .paddr=0x4000D228,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_138 */
+	{ .paddr=0x4000D22C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_139 */
+	{ .paddr=0x4000D230,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_140 */
+	{ .paddr=0x4000D234,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_141 */
+	{ .paddr=0x4000D238,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_142 */
+	{ .paddr=0x4000D23C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_143 */
+	{ .paddr=0x4000D240,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_144 */
+	{ .paddr=0x4000D244,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_145 */
+	{ .paddr=0x4000D248,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_146 */
+	{ .paddr=0x4000D24C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_147 */
+	{ .paddr=0x4000D250,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_148 */
+	{ .paddr=0x4000D254,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_149 */
+	{ .paddr=0x4000D258,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_150 */
+	{ .paddr=0x4000D25C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_151 */
+	{ .paddr=0x4000D260,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_152 */
+	{ .paddr=0x4000D264,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_153 */
+	{ .paddr=0x4000D268,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_154 */
+	{ .paddr=0x4000D26C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_155 */
+	{ .paddr=0x4000D270,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_156 */
+	{ .paddr=0x4000D274,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_157 */
+	{ .paddr=0x4000D278,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_158 */
+	{ .paddr=0x4000D27C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_159 */
+	{ .paddr=0x4000D280,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_160 */
+	{ .paddr=0x4000D284,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_161 */
+	{ .paddr=0x4000D288,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_162 */
+	{ .paddr=0x4000D28C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_163 */
+	{ .paddr=0x4000D290,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_164 */
+	{ .paddr=0x4000D294,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_165 */
+	{ .paddr=0x4000D298,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_166 */
+	{ .paddr=0x4000D29C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_167 */
+	{ .paddr=0x4000D2A0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_168 */
+	{ .paddr=0x4000D2A4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_169 */
+	{ .paddr=0x4000D2A8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_170 */
+	{ .paddr=0x4000D2AC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_171 */
+	{ .paddr=0x4000D2B0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_172 */
+	{ .paddr=0x4000D2B4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_173 */
+	{ .paddr=0x4000D2B8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_174 */
+	{ .paddr=0x4000D2BC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_175 */
+	{ .paddr=0x4000D2C0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_176 */
+	{ .paddr=0x4000D2C4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_177 */
+	{ .paddr=0x4000D2C8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_178 */
+	{ .paddr=0x4000D2CC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_179 */
+	{ .paddr=0x4000D2D0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_180 */
+	{ .paddr=0x4000D2D4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_181 */
+	{ .paddr=0x4000D2D8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_182 */
+	{ .paddr=0x4000D2DC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_183 */
+	{ .paddr=0x4000D2E0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_184 */
+	{ .paddr=0x4000D2E4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_185 */
+	{ .paddr=0x4000D2E8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_186 */
+	{ .paddr=0x4000D2EC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_187 */
+	{ .paddr=0x4000D2F0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_188 */
+	{ .paddr=0x4000D2F4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_189 */
+	{ .paddr=0x4000D2F8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_190 */
+	{ .paddr=0x4000D2FC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_191 */
+	{ .paddr=0x4000D300,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_192 */
+	{ .paddr=0x4000D304,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_193 */
+	{ .paddr=0x4000D308,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_194 */
+	{ .paddr=0x4000D30C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_195 */
+	{ .paddr=0x4000D310,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_196 */
+	{ .paddr=0x4000D314,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_197 */
+	{ .paddr=0x4000D318,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_198 */
+	{ .paddr=0x4000D31C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_199 */
+	{ .paddr=0x4000D320,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_200 */
+	{ .paddr=0x4000D324,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_201 */
+	{ .paddr=0x4000D328,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_202 */
+	{ .paddr=0x4000D32C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_203 */
+	{ .paddr=0x4000D330,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_204 */
+	{ .paddr=0x4000D334,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_205 */
+	{ .paddr=0x4000D338,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_206 */
+	{ .paddr=0x4000D33C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_207 */
+	{ .paddr=0x4000D340,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_208 */
+	{ .paddr=0x4000D344,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_209 */
+	{ .paddr=0x4000D348,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_210 */
+	{ .paddr=0x4000D34C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_211 */
+	{ .paddr=0x4000D350,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_212 */
+	{ .paddr=0x4000D354,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_213 */
+	{ .paddr=0x4000D358,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_214 */
+	{ .paddr=0x4000D35C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_215 */
+	{ .paddr=0x4000D360,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_216 */
+	{ .paddr=0x4000D364,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_217 */
+	{ .paddr=0x4000D368,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_218 */
+	{ .paddr=0x4000D36C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_219 */
+	{ .paddr=0x4000D370,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_220 */
+	{ .paddr=0x4000D374,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_221 */
+	{ .paddr=0x4000D378,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_222 */
+	{ .paddr=0x4000D37C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_223 */
+	{ .paddr=0x4000D380,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_224 */
+	{ .paddr=0x4000D384,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_225 */
+	{ .paddr=0x4000D388,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_226 */
+	{ .paddr=0x4000D38C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_227 */
+	{ .paddr=0x4000D390,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_228 */
+	{ .paddr=0x4000D394,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_229 */
+	{ .paddr=0x4000D398,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_230 */
+	{ .paddr=0x4000D39C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_231 */
+	{ .paddr=0x4000D3A0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_232 */
+	{ .paddr=0x4000D3A4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_233 */
+	{ .paddr=0x4000D3A8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_234 */
+	{ .paddr=0x4000D3AC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_235 */
+	{ .paddr=0x4000D3B0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_236 */
+	{ .paddr=0x4000D3B4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_237 */
+	{ .paddr=0x4000D3B8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_238 */
+	{ .paddr=0x4000D3BC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_239 */
+	{ .paddr=0x4000D3C0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_240 */
+	{ .paddr=0x4000D3C4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_241 */
+	{ .paddr=0x4000D3C8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_242 */
+	{ .paddr=0x4000D3CC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_243 */
+	{ .paddr=0x4000D3D0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_244 */
+	{ .paddr=0x4000D3D4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_245 */
+	{ .paddr=0x4000D3D8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_246 */
+	{ .paddr=0x4000D3DC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_247 */
+	{ .paddr=0x4000D3E0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_248 */
+	{ .paddr=0x4000D3E4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_249 */
+	{ .paddr=0x4000D3E8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_250 */
+	{ .paddr=0x4000D3EC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_251 */
+	{ .paddr=0x4000D3F0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_252 */
+	{ .paddr=0x4000D3F4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_253 */
+	{ .paddr=0x4000D3F8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_254 */
+	{ .paddr=0x4000D3FC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_255 */
+	{ .paddr=0x4000D400,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_256 */
+	{ .paddr=0x4000D404,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_257 */
+	{ .paddr=0x4000D408,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_258 */
+	{ .paddr=0x4000D40C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_259 */
+	{ .paddr=0x4000D410,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_260 */
+	{ .paddr=0x4000D414,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_261 */
+	{ .paddr=0x4000D418,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_262 */
+	{ .paddr=0x4000D41C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_263 */
+	{ .paddr=0x4000D420,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_264 */
+	{ .paddr=0x4000D424,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_265 */
+	{ .paddr=0x4000D428,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_266 */
+	{ .paddr=0x4000D42C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_267 */
+	{ .paddr=0x4000D430,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_268 */
+	{ .paddr=0x4000D434,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_269 */
+	{ .paddr=0x4000D438,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_270 */
+	{ .paddr=0x4000D43C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_271 */
+	{ .paddr=0x4000D440,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_272 */
+	{ .paddr=0x4000D444,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_273 */
+	{ .paddr=0x4000D448,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_274 */
+	{ .paddr=0x4000D44C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_275 */
+	{ .paddr=0x4000D450,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_276 */
+	{ .paddr=0x4000D454,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_277 */
+	{ .paddr=0x4000D458,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_278 */
+	{ .paddr=0x4000D45C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_279 */
+	{ .paddr=0x4000D460,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_280 */
+	{ .paddr=0x4000D464,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_281 */
+	{ .paddr=0x4000D468,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_282 */
+	{ .paddr=0x4000D46C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_283 */
+	{ .paddr=0x4000D470,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_284 */
+	{ .paddr=0x4000D474,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_285 */
+	{ .paddr=0x4000D478,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_286 */
+	{ .paddr=0x4000D47C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_287 */
+	{ .paddr=0x4000D480,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_288 */
+	{ .paddr=0x4000D484,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_289 */
+	{ .paddr=0x4000D488,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_290 */
+	{ .paddr=0x4000D48C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_291 */
+	{ .paddr=0x4000D490,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_292 */
+	{ .paddr=0x4000D494,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_293 */
+	{ .paddr=0x4000D498,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_294 */
+	{ .paddr=0x4000D49C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_295 */
+	{ .paddr=0x4000D4A0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_296 */
+	{ .paddr=0x4000D4A4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_297 */
+	{ .paddr=0x4000D4A8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_298 */
+	{ .paddr=0x4000D4AC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_299 */
+	{ .paddr=0x4000D4B0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_300 */
+	{ .paddr=0x4000D4B4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_301 */
+	{ .paddr=0x4000D4B8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_302 */
+	{ .paddr=0x4000D4BC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_303 */
+	{ .paddr=0x4000D4C0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_304 */
+	{ .paddr=0x4000D4C4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_305 */
+	{ .paddr=0x4000D4C8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_306 */
+	{ .paddr=0x4000D4CC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_307 */
+	{ .paddr=0x4000D4D0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_308 */
+	{ .paddr=0x4000D4D4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_309 */
+	{ .paddr=0x4000D4D8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_310 */
+	{ .paddr=0x4000D4DC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_311 */
+	{ .paddr=0x4000D4E0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_312 */
+	{ .paddr=0x4000D4E4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_313 */
+	{ .paddr=0x4000D4E8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_314 */
+	{ .paddr=0x4000D4EC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_315 */
+	{ .paddr=0x4000D4F0,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_316 */
+	{ .paddr=0x4000D4F4,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_317 */
+	{ .paddr=0x4000D4F8,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_318 */
+	{ .paddr=0x4000D4FC,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_319 */
+	{ .paddr=0x4000D500,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_320 */
+	{ .paddr=0x4000D504,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_321 */
+	{ .paddr=0x4000D508,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_322 */
+	{ .paddr=0x4000D50C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_323 */
+	{ .paddr=0x4000D510,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_324 */
+	{ .paddr=0x4000D514,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_325 */
+	{ .paddr=0x4000D518,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_326 */
+	{ .paddr=0x4000D51C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_327 */
+	{ .paddr=0x4000D520,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_328 */
+	{ .paddr=0x4000D524,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_329 */
+	{ .paddr=0x4000D528,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_330 */
+	{ .paddr=0x4000D52C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_331 */
+	{ .paddr=0x4000D530,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_332 */
+	{ .paddr=0x4000D534,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_333 */
+	{ .paddr=0x4000D538,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_334 */
+	{ .paddr=0x4000D53C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_335 */
+	{ .paddr=0x4000D540,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_336 */
+	{ .paddr=0x4000D544,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_337 */
+	{ .paddr=0x4000D548,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_338 */
+	{ .paddr=0x4000D54C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_339 */
+	{ .paddr=0x4000D550,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_340 */
+	{ .paddr=0x4000D554,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_341 */
+	{ .paddr=0x4000D558,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_342 */
+	{ .paddr=0x4000D55C,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_343 */
+	{ .paddr=0x4000D560,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_344 */
+	{ .paddr=0x4000D564,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_345 */
+	{ .paddr=0x4000D568,	.rmask=0x0UL,	.wmask=0x0UL	}, /* DDR_CTL_346 */
+	{ .paddr=0x4000E000,	.rmask=~0UL,	.wmask=0xFFFFFFFE	}, /* UNCCTRL */
+	{ .paddr=0x4000E004,	.rmask=~0UL,	.wmask=0xFFFFFFFE	}, /* DLLCTRL */
+};
+
+
+#endif /* _RZN1_REGAUTH_H */
diff --git a/core/arch/arm/sm/sm.c b/core/arch/arm/sm/sm.c
index 9fd5430e..6b08d767 100644
--- a/core/arch/arm/sm/sm.c
+++ b/core/arch/arm/sm/sm.c
@@ -16,256 +16,11 @@
 #include "sm_private.h"
 #include <console.h>
 #include <mm/core_memprot.h>
+#include <rzn1_regauth.h>
 
 #define OEM_SVC_PUTC        0x83000001
 #define OEM_SVC_SYSREG      0x83000010
 
-typedef const struct {
-	unsigned long paddr;
-	unsigned long rmask;
-	unsigned long wmask;
-} regauth_t;
-
-static regauth_t regauth[] = {
-	// This list must be sorted by paddr
-	{ .paddr=0x4000c000, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_USB
-	{ .paddr=0x4000c008, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_SDIO0
-	{ .paddr=0x4000c00c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO0
-	{ .paddr=0x4000c010, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_SDIO0
-	{ .paddr=0x4000c01c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_USB
-	{ .paddr=0x4000c020, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_USB
-	{ .paddr=0x4000c024, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_CRYPTO
-	{ .paddr=0x4000c02c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_MSEBI
-	{ .paddr=0x4000c034, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_0
-	{ .paddr=0x4000c03c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_1
-	{ .paddr=0x4000c040, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_FW1
-	{ .paddr=0x4000c044, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_FW2
-	{ .paddr=0x4000c048, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PGEXT2_PR6DIV
-	{ .paddr=0x4000c04c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_DMA
-	{ .paddr=0x4000c050, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_NFLASH
-	{ .paddr=0x4000c054, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_QSPI0
-	{ .paddr=0x4000c05c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_NFLASH
-	{ .paddr=0x4000c060, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_QSPI0
-	{ .paddr=0x4000c064, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRCTRL_DDRC
-	{ .paddr=0x4000c068, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_EETH
-	{ .paddr=0x4000c06c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_MAC0
-	{ .paddr=0x4000c070, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_MAC1
-	{ .paddr=0x4000c074, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_DDRC
-	{ .paddr=0x4000c07c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_MAC1
-	{ .paddr=0x4000c080, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_ECAT
-	{ .paddr=0x4000c084, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SERCOS
-	{ .paddr=0x4000c090, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_HSR
-	{ .paddr=0x4000c094, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SWITCHDIV
-	{ .paddr=0x4000c0a0, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_DMAMUX
-	{ .paddr=0x4000c0c0, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_USBSTAT
-	{ .paddr=0x4000c0c4, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_CFG_SDIO1
-	{ .paddr=0x4000c0c8, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO1
-	{ .paddr=0x4000c0e0, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_OPPDIV
-	{ .paddr=0x4000c0e4, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_CA7DIV
-	{ .paddr=0x4000c0e8, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG2_25MHZ
-	{ .paddr=0x4000c0ec, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR2
-	{ .paddr=0x4000c0f0, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG3_48MHZ
-	{ .paddr=0x4000c0f4, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG4_FW
-	{ .paddr=0x4000c0f8, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR2DIV
-	{ .paddr=0x4000c0fc, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR3
-	{ .paddr=0x4000c100, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR3DIV
-	{ .paddr=0x4000c104, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR4
-	{ .paddr=0x4000c108, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR4DIV
-	{ .paddr=0x4000c10c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG4_PR1
-	{ .paddr=0x4000c110, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG4_PR1DIV
-	{ .paddr=0x4000c114, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PGEXT2_PR6
-	{ .paddr=0x4000c118, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG5_PR5
-	{ .paddr=0x4000c11c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG5_PR5DIV
-	{ .paddr=0x4000c120, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_RSTEN
-	{ .paddr=0x4000c124, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_QSPI0DIV
-	{ .paddr=0x4000c128, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO0DIV
-	{ .paddr=0x4000c12c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SDIO1DIV
-	{ .paddr=0x4000c130, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SWITCH
-	{ .paddr=0x4000c134, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_ADCDIV
-	{ .paddr=0x4000c138, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_I2CDIV
-	{ .paddr=0x4000c13c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_UARTDIV
-	{ .paddr=0x4000c140, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_RTC
-	{ .paddr=0x4000c148, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_NFLASHDIV
-	{ .paddr=0x4000c150, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_PG0_MOTORDIV
-	{ .paddr=0x4000c154, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_ROM
-	{ .paddr=0x4000c15c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_PG2_25MHZ
-	{ .paddr=0x4000c160, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_PWRSTAT_PG3_48MHZ
-	{ .paddr=0x4000c174, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_CM3
-	{ .paddr=0x4000c184, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_RINCTRL
-	{ .paddr=0x4000c188, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_SWITCHCTRL
-	{ .paddr=0x4000c18c, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_HWRTOS
-	{ .paddr=0x4000c190, .rmask=~0UL, .wmask=~0UL },	// RZN1_SYSCTRL_REG_PWRCTRL_HWRTOS_MDCDIV
-	{ .paddr=0x4000c19c, .rmask=~0UL, .wmask=0    },	// RZN1_SYSCTRL_REG_VERSION
-	{ .paddr=0x40060000, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40060004, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40060008, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x4006000c, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40060010, .rmask=~0UL, .wmask=~0UL },	// UART0
-	{ .paddr=0x40064000, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064004, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064010, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064014, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064018, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006401c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064020, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006402c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064030, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064034, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064038, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006403c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064040, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064054, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064060, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006406c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064070, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064074, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064078, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006407c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40064080, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x4006409c, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x400640f4, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x400640f8, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x400640fc, .rmask=~0UL, .wmask=~0UL },	// I2C1
-	{ .paddr=0x40067000, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067004, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006700c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067028, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067034, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067038, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006703c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067040, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067044, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067048, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006704c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067050, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067058, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006705c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067060, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067064, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067068, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006706c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067070, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067074, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067078, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006708c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067090, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067094, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067098, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006709c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670a0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670a4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670a8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670ac, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670b0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670b4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670b8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670bc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670c0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670c4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670c8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670cc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670d0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670d4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670d8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670dc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670e0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670e4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670e8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670ec, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670f0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670f8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400670fc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067100, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067104, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067108, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006710c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067110, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067114, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067118, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006711c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067120, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067124, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067128, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006712c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067130, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067134, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067138, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006713c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067140, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067144, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067148, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006714c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067150, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067154, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067158, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006715c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067160, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067164, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067168, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006716c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067170, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067174, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067178, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006717c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067180, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067184, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067188, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006718c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067190, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067194, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067198, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006719c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671a0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671b4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671b8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671bc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671c0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671c4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671c8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671cc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671d0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671dc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671e0, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671e4, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671e8, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x400671fc, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067200, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067204, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067208, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006720c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067210, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067214, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067218, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006721c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067220, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067224, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067228, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006722c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067230, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067234, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067238, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006723c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067240, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067244, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006724c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067250, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067254, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067258, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006725c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067260, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067264, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067268, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006726c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067270, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067274, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067278, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x4006727c, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067280, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067284, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067288, .rmask=~0UL, .wmask=~0UL },	// PINMUX
-	{ .paddr=0x40067400, .rmask=~0UL, .wmask=~0UL },	// PINMUX lock
-};
-
 static regauth_t *get_regauth(unsigned long paddr)
 {
 	unsigned int min = 0;
@@ -285,36 +40,31 @@ static uint32_t oem_sysreg (unsigned long addr, unsigned long mask, uint32_t *pv
 	regauth_t *auth;
 	volatile unsigned long *reg;
 
-	// Handle unknown registers
+	// Allow registers not in the list
 	if ( !(auth = get_regauth(addr)) ) {
-		if ( 1 ) { // Troubleshoot code
-			static regauth_t pass = {.rmask = ~0UL,.wmask = ~0UL};
-			auth = &pass;
-			DMSG("Allow %s access to unknown register at 0x%lx", mask ? "write" : "read ", addr);
-		} else {
-			return 1;
-		}
+		static regauth_t pass = {.rmask = ~0UL,.wmask = ~0UL};
+		auth = &pass;
 	}
 
 	// Sanity check
 	reg = (unsigned long*)core_mmu_get_va(addr, MEM_AREA_IO_SEC);
-	if ( mask & ~auth->wmask ) {
-		DMSG("Blocking write of 0x%lx to register 0x%lx (0x%lx)", *pvalue, addr, *reg);
-	}
 
 	// Perform allowed operations
 	if (mask) { // Write
 		mask &= auth->wmask;
-		//if (mask) { DMSG("Write @%lx value 0x%lx",addr,*pvalue); }
-		if ( mask == ~0UL ) { // Full write
+		if ( mask == 0UL ) { // Bits to write are protected
+			DMSG("Blocking write of 0x%x to register 0x%lx (0x%lx)", *pvalue, addr, *reg);
+		} else if ( mask == ~0UL ) { // Full write
 			*reg = *pvalue;
-		} else
-		if (mask) { // Partial write with read ahead
-			*reg = *pvalue = ( *reg & ~mask ) | ( *pvalue & mask );
+		} else { // Partial write with read ahead
+			*reg = ( *reg & ~mask ) | ( *pvalue & mask );
 		}
 	} else { // Read
-		*pvalue = *reg & auth->rmask;
-		//DMSG("Read  @%lx value 0x%lx",addr,*pvalue);
+		if ( auth->rmask == 0UL ) {
+			DMSG("Blocking read of register 0x%lx (0x%lx)", addr, *reg);
+		} else {
+			*pvalue = *reg & auth->rmask;
+		}
 	}
 	return 0;
 }