diff options
| author | Ralph Siemsen <ralph.siemsen@linaro.org> | 2021-11-05 13:36:42 -0400 |
|---|---|---|
| committer | Jérôme Forissier <jerome@forissier.org> | 2021-11-24 17:43:37 +0100 |
| commit | a7b6b979b5ea10f92ff5b1063306492747a4f9ad (patch) | |
| tree | 6d7a0a2bb4dde3da93b64040572755edda13fcb6 | |
| parent | 5ab6717dfa872443e948944f0e4fb5a9017c5427 (diff) | |
The RZ/N1 platform contains a Cortex-M3 in addition to dual A7 cores.
Add CFG_BOOT_CM3 flat (default=y) to start the Cortex-M3 unit.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
| -rw-r--r-- | core/arch/arm/plat-rzn1/conf.mk | 2 | ||||
| -rw-r--r-- | core/arch/arm/plat-rzn1/main.c | 47 |
2 files changed, 49 insertions, 0 deletions
diff --git a/core/arch/arm/plat-rzn1/conf.mk b/core/arch/arm/plat-rzn1/conf.mk index 453378d1..5dd7534b 100644 --- a/core/arch/arm/plat-rzn1/conf.mk +++ b/core/arch/arm/plat-rzn1/conf.mk @@ -24,3 +24,5 @@ CFG_TEE_RAM_VA_SIZE ?= 0x00200000 CFG_NUM_THREADS ?= 4 CFG_NS_ENTRY_ADDR ?= 0x87A00000 + +CFG_BOOT_CM3 ?= y diff --git a/core/arch/arm/plat-rzn1/main.c b/core/arch/arm/plat-rzn1/main.c index 192a380b..645c5c3e 100644 --- a/core/arch/arm/plat-rzn1/main.c +++ b/core/arch/arm/plat-rzn1/main.c @@ -9,6 +9,7 @@ #include <drivers/gic.h> #include <drivers/ns16550.h> #include <kernel/boot.h> +#include <kernel/delay.h> #include <kernel/interrupt.h> #include <kernel/panic.h> #include <mm/core_memprot.h> @@ -16,6 +17,18 @@ #include <platform_config.h> #include <rzn1_tz.h> +#define SYSCTRL_PWRCTRL_CM3 (SYSCTRL_BASE + 0x174) +#define SYSCTRL_PWRSTAT_CM3 (SYSCTRL_BASE + 0x178) + +#define SYSCTRL_PWRCTRL_CM3_CLKEN_A BIT(0) +#define SYSCTRL_PWRCTRL_CM3_RSTN_A BIT(1) +#define SYSCTRL_PWRCTRL_CM3_MIREQ_A BIT(2) + +#define SYSCTRL_PWRSTAT_CM3_MIRACK_A BIT(0) + +/* Timeout waiting for Master Idle Request Acknowledge */ +#define IDLE_ACK_TIMEOUT_US 1000 + static struct gic_data gic_data; static struct ns16550_data console_data; @@ -72,3 +85,37 @@ static TEE_Result rzn1_tz_init(void) } service_init(rzn1_tz_init); + +#ifdef CFG_BOOT_CM3 +static TEE_Result rzn1_cm3_start(void) +{ + vaddr_t cm3_pwrctrl_reg = 0; + vaddr_t cm3_pwrstat_reg = 0; + uint64_t timeout_ack = timeout_init_us(IDLE_ACK_TIMEOUT_US); + + cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, + sizeof(uint32_t)); + cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, + sizeof(uint32_t)); + + /* Master Idle Request to the interconnect for CM3 */ + io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); + + /* Wait for Master Idle Request Acknowledge for CM3 */ + while (!timeout_elapsed(timeout_ack)) + if (!(io_read32(cm3_pwrstat_reg) & + SYSCTRL_PWRSTAT_CM3_MIRACK_A)) + break; + + if (io_read32(cm3_pwrstat_reg) & SYSCTRL_PWRSTAT_CM3_MIRACK_A) + panic(); + + /* Clock Enable for CM3_HCLK & Active low Reset to CM3 */ + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); + + return TEE_SUCCESS; +} + +service_init(rzn1_cm3_start); +#endif |