n1sdp: add config files for n1sdp mcp ramfw

Change-Id: I57f379008ba03abb5433d0b0231a9f20223ef697
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

9 files changed, 378 insertions, 0 deletions

diff --git a/product/n1sdp/mcp_ramfw/RTX_Config.h b/product/n1sdp/mcp_ramfw/RTX_Config.h
new file mode 100644
index 00000000..7fa9f64e
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/RTX_Config.h
@@ -0,0 +1,56 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *      RTX2 v5 configuration file.
+ *      The file must be called RTX_Config.h as it is included by an RTX
+ *      file in order to create an object file containing the configuration.
+ */
+
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+
+/* System */
+#define OS_DYNAMIC_MEM_SIZE        0
+#define OS_TICK_FREQ               1000 /* Hz */
+#define OS_ROBIN_ENABLE            0
+#define OS_ROBIN_TIMEOUT           0
+#define OS_ISR_FIFO_QUEUE          16
+
+/* Thread */
+#define OS_THREAD_OBJ_MEM          0
+#define OS_THREAD_NUM              1
+#define OS_THREAD_DEF_STACK_NUM    0
+#define OS_THREAD_USER_STACK_SIZE  0
+#define OS_STACK_SIZE              200
+#define OS_IDLE_THREAD_STACK_SIZE  200
+#define OS_STACK_CHECK             1
+#define OS_STACK_WATERMARK         0
+#define OS_PRIVILEGE_MODE          1
+
+/* Timer */
+#define OS_TIMER_OBJ_MEM           0
+#define OS_TIMER_NUM               1
+#define OS_TIMER_THREAD_PRIO       40
+#define OS_TIMER_THREAD_STACK_SIZE 200
+#define OS_TIMER_CB_QUEUE          4
+
+/* Event flags */
+#define OS_EVFLAGS_OBJ_MEM         0
+#define OS_EVFLAGS_NUM             1
+
+#define OS_MUTEX_OBJ_MEM           0
+#define OS_MUTEX_NUM               1
+#define OS_SEMAPHORE_OBJ_MEM       0
+#define OS_SEMAPHORE_NUM           1
+#define OS_MEMPOOL_OBJ_MEM         0
+#define OS_MEMPOOL_NUM             1
+#define OS_MEMPOOL_DATA_SIZE       0
+#define OS_MSGQUEUE_OBJ_MEM        0
+#define OS_MSGQUEUE_NUM            1
+#define OS_MSGQUEUE_DATA_SIZE      0
+
+#endif /* RTX_CONFIG_H_ */
diff --git a/product/n1sdp/mcp_ramfw/config_armv7m_mpu.c b/product/n1sdp/mcp_ramfw/config_armv7m_mpu.c
new file mode 100644
index 00000000..c6bff184
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/config_armv7m_mpu.c
@@ -0,0 +1,47 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <mod_armv7m_mpu.h>
+#include <n1sdp_mcp_mmap.h>
+#include <n1sdp_mcp_system_mmap.h>
+
+static const ARM_MPU_Region_t regions[] = {
+    { /* 0x0000_0000 - 0xFFFF_FFFF */
+        .RBAR = ARM_MPU_RBAR(0, 0x00000000),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 1, 0, 1, 0, ARM_MPU_REGION_SIZE_4GB),
+    },
+    { /* 0x0080_0000 - 0x0087_FFFF */
+        .RBAR = ARM_MPU_RBAR(1, MCP_RAM0_BASE),
+        .RASR = ARM_MPU_RASR(
+            0, ARM_MPU_AP_PRO, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB),
+    },
+    { /* 0x2000_0000 - 0x2003_FFFF */
+        .RBAR = ARM_MPU_RBAR(2, MCP_RAM1_BASE),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB),
+    },
+    { /* 0x4562_0000 - 0x4562_00FF */
+        .RBAR = ARM_MPU_RBAR(3, MCP_SCP_SHARED_SECURE_RAM),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B),
+    },
+    { /* 0x4561_0000 - 0x4561_00FF */
+        .RBAR = ARM_MPU_RBAR(4, MCP_SCP_SHARED_NONSECURE_RAM),
+        .RASR = ARM_MPU_RASR(
+            1, ARM_MPU_AP_PRIV, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_256B),
+    },
+};
+
+const struct fwk_module_config config_armv7m_mpu = {
+    .data = &((struct mod_armv7m_mpu_config){
+        .region_count = FWK_ARRAY_SIZE(regions),
+        .regions = regions,
+    }),
+};
diff --git a/product/n1sdp/mcp_ramfw/config_clock.c b/product/n1sdp/mcp_ramfw/config_clock.c
new file mode 100644
index 00000000..f1b03e64
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/config_clock.c
@@ -0,0 +1,14 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_module.h>
+
+/*
+ * Empty placeholder for compatibility as all clocks are
+ * managed by SCP.
+ */
+const struct fwk_module_config config_clock = { 0 };
diff --git a/product/n1sdp/mcp_ramfw/config_clock.h b/product/n1sdp/mcp_ramfw/config_clock.h
new file mode 100644
index 00000000..bb02958a
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/config_clock.h
@@ -0,0 +1,28 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONFIG_CLOCK_H
+#define CONFIG_CLOCK_H
+
+#include <fwk_macros.h>
+
+/*
+ * PIK clock rates.
+ */
+#define PIK_CLK_RATE_MCP_CORECLK  (300 * FWK_MHZ)
+#define PIK_CLK_RATE_MCP_AXICLK   (300 * FWK_MHZ)
+
+/*
+ * PIK clock indexes.
+ */
+enum clock_pik_idx {
+    CLOCK_PIK_IDX_MCP_CORECLK,
+    CLOCK_PIK_IDX_MCP_AXICLK,
+    CLOCK_PIK_IDX_COUNT
+};
+
+#endif /* CONFIG_CLOCK_H */
diff --git a/product/n1sdp/mcp_ramfw/config_log.c b/product/n1sdp/mcp_ramfw/config_log.c
new file mode 100644
index 00000000..072f67a3
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/config_log.c
@@ -0,0 +1,59 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <fwk_banner.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+#include <fwk_module_idx.h>
+#include <mod_log.h>
+#include <mod_pl011.h>
+#include <n1sdp_mcp_mmap.h>
+#include <n1sdp_system_clock.h>
+
+/*
+ * PL011 module
+ */
+static const struct fwk_element pl011_element_desc_table[] = {
+    [0] = {
+        .name = "MCP-UART",
+        .data = &((struct mod_pl011_device_config) {
+            .reg_base = MCP_UART0_BASE,
+            .baud_rate_bps = 38400,
+            .clock_rate_hz = CLOCK_RATE_REFCLK,
+            .clock_id = FWK_ID_NONE_INIT,
+            }),
+    },
+    [1] = { 0 },
+};
+
+static const struct fwk_element *get_pl011_table(fwk_id_t module_id)
+{
+    return pl011_element_desc_table;
+}
+
+struct fwk_module_config config_pl011 = {
+    .get_element_table = get_pl011_table,
+};
+
+/*
+ * Log module
+ */
+static const struct mod_log_config log_data = {
+    .device_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PL011, 0),
+    .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PL011, 0),
+    .log_groups = MOD_LOG_GROUP_ERROR |
+                  MOD_LOG_GROUP_INFO |
+                  MOD_LOG_GROUP_WARNING |
+                  MOD_LOG_GROUP_DEBUG,
+    .banner = FWK_BANNER_MCP
+              FWK_BANNER_RAM_FIRMWARE
+              BUILD_VERSION_DESCRIBE_STRING "\n",
+};
+
+struct fwk_module_config config_log = {
+    .data = &log_data,
+};
diff --git a/product/n1sdp/mcp_ramfw/config_pik_clock.c b/product/n1sdp/mcp_ramfw/config_pik_clock.c
new file mode 100644
index 00000000..35018aae
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/config_pik_clock.c
@@ -0,0 +1,78 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_module.h>
+#include <mod_pik_clock.h>
+#include <n1sdp_mcp_pik.h>
+#include <n1sdp_pik_mcp.h>
+#include <n1sdp_system_clock.h>
+#include <config_clock.h>
+
+/*
+ * Rate lookup tables
+ */
+
+static const struct mod_pik_clock_rate rate_table_mcp_coreclk[] = {
+    {
+        .rate = PIK_CLK_RATE_MCP_CORECLK,
+        .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS,
+        .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_CORECLK,
+    },
+};
+
+static const struct mod_pik_clock_rate rate_table_mcp_axiclk[] = {
+    {
+        .rate = PIK_CLK_RATE_MCP_AXICLK,
+        .source = MOD_PIK_CLOCK_MSCLOCK_SOURCE_SYSPLLCLK,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_SYS,
+        .divider = CLOCK_RATE_SYSPLLCLK / PIK_CLK_RATE_MCP_AXICLK,
+    },
+};
+
+static const struct fwk_element pik_clock_element_table[] = {
+    [CLOCK_PIK_IDX_MCP_CORECLK] = {
+        .name = "MCP CORECLK",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_MCP->CORECLK_CTRL,
+            .divsys_reg = &PIK_MCP->CORECLK_DIV1,
+            .rate_table = rate_table_mcp_coreclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_coreclk),
+            .initial_rate = PIK_CLK_RATE_MCP_CORECLK,
+            .defer_initialization = true,
+        }),
+    },
+    [CLOCK_PIK_IDX_MCP_AXICLK] = {
+        .name = "MCP AXICLK",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_MULTI_SOURCE,
+            .is_group_member = false,
+            .control_reg = &PIK_MCP->CORECLK_CTRL,
+            .divsys_reg = &PIK_MCP->CORECLK_DIV1,
+            .rate_table = rate_table_mcp_axiclk,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_mcp_axiclk),
+            .initial_rate = PIK_CLK_RATE_MCP_AXICLK,
+            .defer_initialization = true,
+        }),
+    },
+    [CLOCK_PIK_IDX_COUNT] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *pik_clock_get_element_table
+    (fwk_id_t module_id)
+{
+    return pik_clock_element_table;
+}
+
+const struct fwk_module_config config_pik_clock = {
+    .get_element_table = pik_clock_get_element_table,
+};
diff --git a/product/n1sdp/mcp_ramfw/firmware.mk b/product/n1sdp/mcp_ramfw/firmware.mk
new file mode 100644
index 00000000..74d827de
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/firmware.mk
@@ -0,0 +1,29 @@
+#
+# Arm SCP/MCP Software
+# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BS_FIRMWARE_CPU := cortex-m7
+BS_FIRMWARE_HAS_MULTITHREADING := yes
+BS_FIRMWARE_HAS_NOTIFICATION := yes
+BS_FIRMWARE_MODULE_HEADERS_ONLY := \
+    power_domain \
+    css_clock
+
+BS_FIRMWARE_MODULES := \
+    armv7m_mpu \
+    pl011 \
+    log \
+    pik_clock \
+    clock
+
+BS_FIRMWARE_SOURCES := \
+    rtx_config.c \
+    config_armv7m_mpu.c \
+    config_log.c \
+    config_pik_clock.c \
+    config_clock.c
+
+include $(BS_DIR)/firmware.mk
diff --git a/product/n1sdp/mcp_ramfw/fmw_memory.ld.S b/product/n1sdp/mcp_ramfw/fmw_memory.ld.S
new file mode 100644
index 00000000..7099e370
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/fmw_memory.ld.S
@@ -0,0 +1,32 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Description:
+ *     RAM firmware memory layout for the linker script.
+ */
+
+#ifndef FMW_MEMORY_LD_S
+#define FMW_MEMORY_LD_S
+
+#include <n1sdp_mcp_system_mmap.h>
+
+#define FIRMWARE_MEM_MODE FWK_MEM_MODE_DUAL_REGION_RELOCATION
+
+/*
+ * RAM instruction memory
+ */
+#define FIRMWARE_MEM0_SIZE  MCP_RAM0_SIZE
+#define FIRMWARE_MEM0_BASE  MCP_RAM0_BASE
+
+/*
+ * RAM data memory
+ */
+#define FIRMWARE_MEM1_SIZE  MCP_RAM1_SIZE
+#define FIRMWARE_MEM1_BASE  MCP_RAM1_BASE
+
+#define FIRMWARE_STACK_SIZE (1 * 1024)
+
+#endif /* FMW_MEMORY_LD_S */
diff --git a/product/n1sdp/mcp_ramfw/rtx_config.c b/product/n1sdp/mcp_ramfw/rtx_config.c
new file mode 100644
index 00000000..3d54e676
--- /dev/null
+++ b/product/n1sdp/mcp_ramfw/rtx_config.c
@@ -0,0 +1,35 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <cmsis_compiler.h>
+#include <rtx_os.h>
+#include <n1sdp_system_clock.h>
+#include <rtx_lib.c>
+
+/*
+ * Required by RTX to configure the SysTick timer.
+ */
+uint32_t SystemCoreClock = CLOCK_RATE_REFCLK;
+
+/*
+ * Idle thread
+ */
+__NO_RETURN void osRtxIdleThread(void *argument)
+{
+    while (true)
+        __WFI();
+}
+
+/*
+ * OS error handler
+ */
+uint32_t osRtxErrorNotify(uint32_t code, void *object_id)
+{
+    osRtxIdleThread(object_id);
+}