diff options
| author | Manoj Kumar <manoj.kumar3@arm.com> | 2018-10-26 12:02:17 +0530 |
|---|---|---|
| committer | ronald-cron-arm <39518861+ronald-cron-arm@users.noreply.github.com> | 2018-11-15 11:04:19 +0100 |
| commit | 8bd282f914064fc753cee16439b30140b3a488f3 (patch) | |
| tree | 7a1cffd0ef6896d98afd029062785a58066bceda /product/n1sdp | |
| parent | 30590d8a334c0934fa371df917d11c07331a39d2 (diff) | |
n1sdp: add pik header files for n1sdp MCP
Change-Id: I4dd4208c02aa549c7809eca90f2366a9ec0a2374
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Diffstat (limited to 'product/n1sdp')
| -rw-r--r-- | product/n1sdp/include/n1sdp_mcp_pik.h | 16 | ||||
| -rw-r--r-- | product/n1sdp/include/n1sdp_pik_mcp.h | 60 |
2 files changed, 76 insertions, 0 deletions
diff --git a/product/n1sdp/include/n1sdp_mcp_pik.h b/product/n1sdp/include/n1sdp_mcp_pik.h new file mode 100644 index 00000000..f76f3b15 --- /dev/null +++ b/product/n1sdp/include/n1sdp_mcp_pik.h @@ -0,0 +1,16 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef N1SDP_MCP_PIK_H +#define N1SDP_MCP_PIK_H + +#include <n1sdp_mcp_mmap.h> +#include <n1sdp_pik_mcp.h> + +#define PIK_MCP ((struct pik_mcp_reg *) MCP_PIK_BASE) + +#endif /* N1SDP_MCP_PIK_H */ diff --git a/product/n1sdp/include/n1sdp_pik_mcp.h b/product/n1sdp/include/n1sdp_pik_mcp.h new file mode 100644 index 00000000..7be5086a --- /dev/null +++ b/product/n1sdp/include/n1sdp_pik_mcp.h @@ -0,0 +1,60 @@ +/* + * Arm SCP/MCP Software + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Description: + * MCP PIK registers + */ + +#ifndef N1SDP_PIK_MCP_H +#define N1SDP_PIK_MCP_H + +#include <stdint.h> +#include <fwk_macros.h> + +/*! + * \brief MCP PIK register definitions + */ +struct pik_mcp_reg { + uint8_t RESERVED0[0x10 - 0x0]; + FWK_RW uint32_t RESET_SYNDROME; + uint8_t RESERVED1[0x20 - 0x14]; + FWK_RW uint32_t SURVIVAL_RESET_STATUS; + uint8_t RESERVED2[0x34 - 0x24]; + FWK_RW uint32_t ADDR_TRANS; + FWK_RW uint32_t DBG_ADDR_TRANS; + uint8_t RESERVED3[0x40 - 0x3C]; + FWK_RW uint32_t WS1_TIMER_MATCH; + FWK_RW uint32_t WS1_TIMER_EN; + uint8_t RESERVED4[0x200 - 0x48]; + FWK_R uint32_t SS_RESET_STATUS; + FWK_W uint32_t SS_RESET_SET; + FWK_W uint32_t SS_RESET_CLR; + uint8_t RESERVED5[0x810 - 0x20C]; + FWK_RW uint32_t CORECLK_CTRL; + FWK_RW uint32_t CORECLK_DIV1; + uint8_t RESERVED6[0x820 - 0x818]; + FWK_RW uint32_t ACLK_CTRL; + FWK_RW uint32_t ACLK_DIV1; + uint8_t RESERVED7[0xA10 - 0x828]; + FWK_R uint32_t PLL_STATUS0; + uint8_t RESERVED8[0xFC0 - 0xA14]; + FWK_R uint32_t PWR_CTRL_CONFIG; + uint8_t RESERVED18[0xFD0 - 0xFC4]; + FWK_R uint32_t PID4; + FWK_R uint32_t PID5; + FWK_R uint32_t PID6; + FWK_R uint32_t PID7; + FWK_R uint32_t PID0; + FWK_R uint32_t PID1; + FWK_R uint32_t PID2; + FWK_R uint32_t PID3; + FWK_R uint32_t ID0; + FWK_R uint32_t ID1; + FWK_R uint32_t ID2; + FWK_R uint32_t ID3; +}; + +#endif /* N1SDP_PIK_MCP_H */ |