arm: Move Cortex-M memory map to be absolute addressed

Support Cortex-M0, M3/M4, M7 is easier when the memory map is defined in
terms of absolute addresses.

Based work from: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>

Change-Id: I860860c369e8bed6c6c23661a15ce464d87ff221
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

1 files changed, 34 insertions, 34 deletions

diff --git a/include/arch/arm/cortex_m/memory_map.h b/include/arch/arm/cortex_m/memory_map.h
index eb0edadf4..24104a9a5 100644
--- a/include/arch/arm/cortex_m/memory_map.h
+++ b/include/arch/arm/cortex_m/memory_map.h
@@ -28,32 +28,32 @@
 #include <misc/util.h>
 
 /* 0x00000000 -> 0x1fffffff: Code in ROM [0.5 GB] */
-#define _CODE_BASE_ADDR 0
-#define _CODE_END_ADDR (_CODE_BASE_ADDR + MB(512) - 1)
+#define _CODE_BASE_ADDR           0x00000000
+#define _CODE_END_ADDR            0x1FFFFFFF
 
 /* 0x20000000 -> 0x3fffffff: SRAM [0.5GB] */
-#define _SRAM_BASE_ADDR (_CODE_END_ADDR + 1)
-#define _SRAM_BIT_BAND_REGION (_SRAM_BASE_ADDR)
-#define _SRAM_BIT_BAND_REGION_END (_SRAM_BIT_BAND_REGION + MB(1) - 1)
-#define _SRAM_BIT_BAND_ALIAS (_SRAM_BIT_BAND_REGION + MB(32))
-#define _SRAM_BIT_BAND_ALIAS_END (_SRAM_BIT_BAND_ALIAS + MB(32) - 1)
-#define _SRAM_END_ADDR (_SRAM_BASE_ADDR + MB(512) - 1)
+#define _SRAM_BASE_ADDR           0x20000000
+#define _SRAM_BIT_BAND_REGION     0x20000000
+#define _SRAM_BIT_BAND_REGION_END 0x200FFFFF
+#define _SRAM_BIT_BAND_ALIAS      0x22000000
+#define _SRAM_BIT_BAND_ALIAS_END  0x23FFFFFF
+#define _SRAM_END_ADDR            0x3FFFFFFF
 
 /* 0x40000000 -> 0x5fffffff: Peripherals [0.5GB] */
-#define _PERI_BASE_ADDR (_SRAM_END_ADDR + 1)
-#define _PERI_BIT_BAND_REGION (_PERI_BASE_ADDR)
-#define _PERI_BIT_BAND_REGION_END (_PERI_BIT_BAND_REGION + MB(1) - 1)
-#define _PERI_BIT_BAND_ALIAS (_PERI_BIT_BAND_REGION + MB(32))
-#define _PERI_BIT_BAND_ALIAS_END (_PERI_BIT_BAND_ALIAS + MB(32) - 1)
-#define _PERI_END_ADDR (_PERI_BASE_ADDR + MB(512) - 1)
+#define _PERI_BASE_ADDR           0x40000000
+#define _PERI_BIT_BAND_REGION     0x40000000
+#define _PERI_BIT_BAND_REGION_END 0x400FFFFF
+#define _PERI_BIT_BAND_ALIAS      0x42000000
+#define _PERI_BIT_BAND_ALIAS_END  0x43FFFFFF
+#define _PERI_END_ADDR            0x5FFFFFFF
 
 /* 0x60000000 -> 0x9fffffff: external RAM [1GB] */
-#define _ERAM_BASE_ADDR (_PERI_END_ADDR + 1)
-#define _ERAM_END_ADDR (_ERAM_BASE_ADDR + GB(1) - 1)
+#define _ERAM_BASE_ADDR           0x60000000
+#define _ERAM_END_ADDR            0x9FFFFFFF
 
 /* 0xa0000000 -> 0xdfffffff: external devices [1GB] */
-#define _EDEV_BASE_ADDR (_ERAM_END_ADDR + 1)
-#define _EDEV_END_ADDR (_EDEV_BASE_ADDR + GB(1) - 1)
+#define _EDEV_BASE_ADDR           0xA0000000
+#define _EDEV_END_ADDR            0xDFFFFFFF
 
 /* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
 
@@ -61,26 +61,26 @@
 /* 0xe0000000 -> 0xe00fffff: private peripheral bus */
 
 /* 0xe0000000 -> 0xe003ffff: internal [256KB] */
-#define _PPB_INT_BASE_ADDR (_EDEV_END_ADDR + 1)
-#define _PPB_INT_ITM _PPB_INT_BASE_ADDR
-#define _PPB_INT_DWT (_PPB_INT_ITM + KB(4))
-#define _PPB_INT_FPB (_PPB_INT_DWT + KB(4))
-#define _PPB_INT_RSVD_1 (_PPB_INT_FPB + KB(4))
-#define _PPB_INT_SCS (_PPB_INT_RSVD_1 + KB(44))
-#define _PPB_INT_RSVD_2 (_PPB_INT_SCS + KB(4))
-#define _PPB_INT_END_ADDR (_PPB_INT_RSVD_2 + KB(196) - 1)
+#define _PPB_INT_BASE_ADDR        0xE0000000
+#define _PPB_INT_ITM              0xE0000000
+#define _PPB_INT_DWT              0xE0001000
+#define _PPB_INT_FPB              0xE0002000
+#define _PPB_INT_RSVD_1           0xE0003000
+#define _PPB_INT_SCS              0xE000E000
+#define _PPB_INT_RSVD_2           0xE000F000
+#define _PPB_INT_END_ADDR         0xE003FFFF
 
 /* 0xe0040000 -> 0xe00fffff: external [768K] */
-#define _PPB_EXT_BASE_ADDR (_PPB_INT_END_ADDR + 1)
-#define _PPB_EXT_TPIU _PPB_EXT_BASE_ADDR
-#define _PPB_EXT_ETM (_PPB_EXT_TPIU + KB(4))
-#define _PPB_EXT_PPB (_PPB_EXT_ETM + KB(4))
-#define _PPB_EXT_ROM_TABLE (_PPB_EXT_PPB + KB(756))
-#define _PPB_EXT_END_ADDR (_PPB_EXT_ROM_TABLE + KB(4) - 1)
+#define _PPB_EXT_BASE_ADDR        0xE0040000
+#define _PPB_EXT_TPIU             0xE0040000
+#define _PPB_EXT_ETM              0xE0041000
+#define _PPB_EXT_PPB              0xE0042000
+#define _PPB_EXT_ROM_TABLE        0xE00FF000
+#define _PPB_EXT_END_ADDR         0xE00FFFFF
 
 /* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB]  */
-#define _VENDOR_BASE_ADDR (_PPB_EXT_END_ADDR + 1)
-#define _VENDOR_END_ADDR 0xffffffff
+#define _VENDOR_BASE_ADDR         0xE0100000
+#define _VENDOR_END_ADDR          0xFFFFFFFF
 #else
 #error Unknown CPU
 #endif