diff options
| author | Iván Briano <ivan.briano@intel.com> | 2016-07-14 11:46:31 -0300 |
|---|---|---|
| committer | Andrew Boie <andrew.p.boie@intel.com> | 2016-07-20 16:24:22 +0000 |
| commit | 4b6a87e48ebc14e4f961bc3ea4b1d338aeb34791 (patch) | |
| tree | 3b7dbc1c0a604913e5661a64a0c63fb55cc41e96 /ext | |
| parent | 211ae314e8de20482d15ee53f50c709b9cee613d (diff) | |
ext qmsi: Fix registers definition for LPSS
This is fixed in QMSI 1.1 already and this patch can be reverted when
the next released is merged into Zephyr.
Original commit message:
While performing power measurements in LPSS, it appeared that the value
for LPSS registers was incorrect. Fix this value to enable proper entry
in LPSS mode.
Change-Id: Ie6a4aa5c9aa01ebaad0cd2db722bb9b5c87df5e7
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Diffstat (limited to 'ext')
| -rw-r--r-- | ext/hal/qmsi/soc/quark_se/include/qm_soc_regs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ext/hal/qmsi/soc/quark_se/include/qm_soc_regs.h b/ext/hal/qmsi/soc/quark_se/include/qm_soc_regs.h index e0d37577a..9542c600e 100644 --- a/ext/hal/qmsi/soc/quark_se/include/qm_soc_regs.h +++ b/ext/hal/qmsi/soc/quark_se/include/qm_soc_regs.h @@ -124,8 +124,8 @@ qm_scss_ccu_reg_t test_scss_ccu; /* System clock control */ #define QM_CCU_SYS_CLK_SEL BIT(0) #define QM_SCSS_CCU_SYS_CLK_SEL BIT(0) -#define QM_SCSS_CCU_C2_LP_EN (1) -#define QM_SCSS_CCU_SS_LPS_EN (0) +#define QM_SCSS_CCU_C2_LP_EN BIT(1) +#define QM_SCSS_CCU_SS_LPS_EN BIT(0) #define QM_CCU_RTC_CLK_EN BIT(1) #define QM_CCU_RTC_CLK_DIV_EN BIT(2) #define QM_CCU_SYS_CLK_DIV_EN BIT(7) |