soc: arm: mps2: Add configuration for CMSDK Driver

This patch adds the configuration parametes required to enable CMSDK
(Cortex-M System Design Kit) Drivers at MPS2 soc level.

It provides as well the definitions for the MPS2 System Control
registers.

Change-Id: I06181dcfeb4fb887425b85ec9a99c268c857a34e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>

3 files changed, 96 insertions, 6 deletions

diff --git a/arch/arm/soc/arm/mps2/soc_devices.h b/arch/arm/soc/arm/mps2/soc_devices.h
index f8fdd824c..41e9091f3 100644
--- a/arch/arm/soc/arm/mps2/soc_devices.h
+++ b/arch/arm/soc/arm/mps2/soc_devices.h
@@ -10,7 +10,20 @@
 #include <soc_memory_map.h>
 #include <soc_irq.h>
 
+#if defined(CONFIG_GPIO)
+/* CMSDK AHB General Purpose Input/Output (GPIO) */
+#define CMSDK_AHB_GPIO0	GPIO_0_BASE_ADDR
+#define IRQ_PORT0_ALL	IRQ_GPIO_0_COMBINED
+#define CMSDK_AHB_GPIO1	GPIO_1_BASE_ADDR
+#define IRQ_PORT1_ALL	IRQ_GPIO_1_COMBINED
+#define CMSDK_AHB_GPIO2	GPIO_2_BASE_ADDR
+#define IRQ_PORT2_ALL	IRQ_GPIO_2_COMBINED
+#define CMSDK_AHB_GPIO3	GPIO_3_BASE_ADDR
+#define IRQ_PORT3_ALL	IRQ_GPIO_3_COMBINED
+#endif /* CONFIG_GPIO */
+
 #if defined(CONFIG_UART_CMSDK_APB)
+/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
 #define CMSDK_APB_UART0		UART_0_BASE_ADDR
 #define CMSDK_APB_UART_0_IRQ_TX	IRQ_UART_0_TX
 #define CMSDK_APB_UART_0_IRQ_RX	IRQ_UART_0_RX
@@ -26,6 +39,32 @@
 #define CMSDK_APB_UART4		UART_4_BASE_ADDR
 #define CMSDK_APB_UART_4_IRQ_TX	IRQ_UART_4_TX
 #define CMSDK_APB_UART_4_IRQ_RX	IRQ_UART_4_RX
-#endif
+#endif /* CONFIG_UART_CMSDK_APB */
+
+#if defined(CONFIG_WATCHDOG)
+/* CMSDK APB Watchdog */
+#define CMSDK_APB_WDOG	WDOG_BASE_ADDR
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_COUNTER)
+/* CMSDK APB Timers */
+#define CMSDK_APB_TIMER0	TIMER_0_BASE_ADDR
+#define CMSDK_APB_TIMER_0_IRQ	IRQ_TIMER_0
+#define CMSDK_APB_TIMER1	TIMER_1_BASE_ADDR
+#define CMSDK_APB_TIMER_1_IRQ	IRQ_TIMER_1
+
+/* CMSDK APB Dual Timer */
+#define CMSDK_APB_DTIMER	DTIMER_BASE_ADDR
+#define CMSDK_APB_DUALTIMER_IRQ	IRQ_DUAL_TIMER
+#endif /* CONFIG_COUNTER */
+
+#ifndef _ASMLANGUAGE
+
+#include "soc_registers.h"
+
+/* System Control Register (SYSCON) */
+#define __MPS2_SYSCON ((volatile struct mps2_syscon *)SYSCON_BASE_ADDR)
+
+#endif /* !_ASMLANGUAGE */
 
 #endif /* _SOC_DEVICES_H_ */
diff --git a/arch/arm/soc/arm/mps2/soc_memory_map.h b/arch/arm/soc/arm/mps2/soc_memory_map.h
index 1674ec120..6a1fba833 100644
--- a/arch/arm/soc/arm/mps2/soc_memory_map.h
+++ b/arch/arm/soc/arm/mps2/soc_memory_map.h
@@ -7,10 +7,30 @@
 #ifndef _SOC_MEMORY_MAP_H_
 #define _SOC_MEMORY_MAP_H_
 
-#define UART_0_BASE_ADDR		0x40004000
-#define UART_1_BASE_ADDR		0x40005000
-#define UART_2_BASE_ADDR		0x40006000
-#define UART_3_BASE_ADDR		0x40007000
-#define UART_4_BASE_ADDR		0x40009000
+/*
+ * Address space definitions
+ */
+
+/* MPS2 Address space definition */
+#define MPS2_APB_BASE_ADDR    0x40000000
+#define MPS2_AHB_BASE_ADDR    0x40010000
+
+/* MPS2 AHB peripherals */
+#define GPIO_0_BASE_ADDR	(MPS2_AHB_BASE_ADDR + 0x0000)
+#define GPIO_1_BASE_ADDR	(MPS2_AHB_BASE_ADDR + 0x1000)
+#define GPIO_2_BASE_ADDR	(MPS2_AHB_BASE_ADDR + 0x2000)
+#define GPIO_3_BASE_ADDR	(MPS2_AHB_BASE_ADDR + 0x3000)
+#define SYSCON_BASE_ADDR	(MPS2_AHB_BASE_ADDR + 0xF000)
+
+/* MPS2 APB peripherals */
+#define TIMER_0_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x0000)
+#define TIMER_1_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x1000)
+#define DTIMER_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x2000)
+#define UART_0_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x4000)
+#define UART_1_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x5000)
+#define UART_2_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x6000)
+#define UART_3_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x7000)
+#define WDOG_BASE_ADDR		(MPS2_APB_BASE_ADDR + 0x8000)
+#define UART_4_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0xB000)
 
 #endif /* _SOC_MEMORY_MAP_H_ */
diff --git a/arch/arm/soc/arm/mps2/soc_registers.h b/arch/arm/soc/arm/mps2/soc_registers.h
new file mode 100644
index 000000000..44f51c8d3
--- /dev/null
+++ b/arch/arm/soc/arm/mps2/soc_registers.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the ARM Ltd MPS2.
+ *
+ */
+
+#ifndef _ARM_MPS2_REGS_H_
+#define _ARM_MPS2_REGS_H_
+
+#include <stdint.h>
+
+/* System Control Register (SYSCON) */
+struct mps2_syscon {
+	/* Offset: 0x000 (r/w) remap control register */
+	volatile uint32_t remap;
+	/* Offset: 0x004 (r/w) pmu control register */
+	volatile uint32_t pmuctrl;
+	/* Offset: 0x008 (r/w) reset option register */
+	volatile uint32_t resetop;
+	/* Offset: 0x00c (r/w) emi control register */
+	volatile uint32_t emictrl;
+	/* Offset: 0x010 (r/w) reset information register */
+	volatile uint32_t rstinfo;
+};
+
+#endif /* _ARM_MPS2_REGS_H_ */