1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8)
declare i16 @llvm.ssub.sat.i16(i16, i16)
declare i32 @llvm.ssub.sat.i32(i32, i32)
declare i64 @llvm.ssub.sat.i64(i64, i64)
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-T1-LABEL: func:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, lr}
; CHECK-T1-NEXT: push {r4, lr}
; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: movs r3, #1
; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: mov r4, r3
; CHECK-T1-NEXT: bmi .LBB0_2
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r4, #0
; CHECK-T1-NEXT: .LBB0_2:
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: bne .LBB0_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: lsls r3, r3, #31
; CHECK-T1-NEXT: cmp r2, r1
; CHECK-T1-NEXT: bvs .LBB0_5
; CHECK-T1-NEXT: b .LBB0_6
; CHECK-T1-NEXT: .LBB0_4:
; CHECK-T1-NEXT: ldr r3, .LCPI0_0
; CHECK-T1-NEXT: cmp r2, r1
; CHECK-T1-NEXT: bvc .LBB0_6
; CHECK-T1-NEXT: .LBB0_5:
; CHECK-T1-NEXT: mov r0, r3
; CHECK-T1-NEXT: .LBB0_6:
; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: .LCPI0_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
;
; CHECK-T2-LABEL: func:
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: subs.w r12, r0, r1
; CHECK-T2-NEXT: mov.w r3, #0
; CHECK-T2-NEXT: mov.w r2, #-2147483648
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r3, #1
; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: mvnne r2, #-2147483648
; CHECK-T2-NEXT: cmp r0, r1
; CHECK-T2-NEXT: it vc
; CHECK-T2-NEXT: movvc r2, r12
; CHECK-T2-NEXT: mov r0, r2
; CHECK-T2-NEXT: bx lr
;
; CHECK-ARM-LABEL: func:
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: subs r12, r0, r1
; CHECK-ARM-NEXT: mov r3, #0
; CHECK-ARM-NEXT: movmi r3, #1
; CHECK-ARM-NEXT: mov r2, #-2147483648
; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: mvnne r2, #-2147483648
; CHECK-ARM-NEXT: cmp r0, r1
; CHECK-ARM-NEXT: movvc r2, r12
; CHECK-ARM-NEXT: mov r0, r2
; CHECK-ARM-NEXT: bx lr
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y)
ret i32 %tmp
}
define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T1-LABEL: func2:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-T1-NEXT: .pad #4
; CHECK-T1-NEXT: sub sp, #4
; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: movs r4, #1
; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: mov r5, r4
; CHECK-T1-NEXT: bge .LBB1_2
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r5, r0
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r7, r4
; CHECK-T1-NEXT: bge .LBB1_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r7, r0
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: subs r5, r7, r5
; CHECK-T1-NEXT: subs r6, r5, #1
; CHECK-T1-NEXT: sbcs r5, r6
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
; CHECK-T1-NEXT: subs r6, r2, r6
; CHECK-T1-NEXT: sbcs r1, r3
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r2, r4
; CHECK-T1-NEXT: bge .LBB1_6
; CHECK-T1-NEXT: @ %bb.5:
; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: subs r0, r7, r2
; CHECK-T1-NEXT: subs r2, r0, #1
; CHECK-T1-NEXT: sbcs r0, r2
; CHECK-T1-NEXT: ands r5, r0
; CHECK-T1-NEXT: beq .LBB1_8
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: asrs r6, r1, #31
; CHECK-T1-NEXT: .LBB1_8:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bmi .LBB1_10
; CHECK-T1-NEXT: @ %bb.9:
; CHECK-T1-NEXT: lsls r2, r4, #31
; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: beq .LBB1_11
; CHECK-T1-NEXT: b .LBB1_12
; CHECK-T1-NEXT: .LBB1_10:
; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: cmp r5, #0
; CHECK-T1-NEXT: bne .LBB1_12
; CHECK-T1-NEXT: .LBB1_11:
; CHECK-T1-NEXT: mov r2, r1
; CHECK-T1-NEXT: .LBB1_12:
; CHECK-T1-NEXT: mov r0, r6
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: add sp, #4
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.13:
; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
;
; CHECK-T2-LABEL: func2:
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r4, lr}
; CHECK-T2-NEXT: push {r4, lr}
; CHECK-T2-NEXT: cmp.w r3, #-1
; CHECK-T2-NEXT: mov.w lr, #0
; CHECK-T2-NEXT: it gt
; CHECK-T2-NEXT: movgt.w lr, #1
; CHECK-T2-NEXT: cmp.w r1, #-1
; CHECK-T2-NEXT: mov.w r4, #0
; CHECK-T2-NEXT: mov.w r12, #0
; CHECK-T2-NEXT: it gt
; CHECK-T2-NEXT: movgt r4, #1
; CHECK-T2-NEXT: subs.w lr, r4, lr
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne.w lr, #1
; CHECK-T2-NEXT: subs r0, r0, r2
; CHECK-T2-NEXT: sbc.w r2, r1, r3
; CHECK-T2-NEXT: cmp.w r2, #-1
; CHECK-T2-NEXT: it gt
; CHECK-T2-NEXT: movgt.w r12, #1
; CHECK-T2-NEXT: subs.w r1, r4, r12
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: movne r1, #1
; CHECK-T2-NEXT: ands.w r3, lr, r1
; CHECK-T2-NEXT: mov.w r1, #-2147483648
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: asrne r0, r2, #31
; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it eq
; CHECK-T2-NEXT: moveq r1, r2
; CHECK-T2-NEXT: pop {r4, pc}
;
; CHECK-ARM-LABEL: func2:
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r4, lr}
; CHECK-ARM-NEXT: push {r4, lr}
; CHECK-ARM-NEXT: cmn r3, #1
; CHECK-ARM-NEXT: mov lr, #0
; CHECK-ARM-NEXT: movgt lr, #1
; CHECK-ARM-NEXT: cmn r1, #1
; CHECK-ARM-NEXT: mov r4, #0
; CHECK-ARM-NEXT: mov r12, #0
; CHECK-ARM-NEXT: movgt r4, #1
; CHECK-ARM-NEXT: subs lr, r4, lr
; CHECK-ARM-NEXT: movne lr, #1
; CHECK-ARM-NEXT: subs r0, r0, r2
; CHECK-ARM-NEXT: sbc r2, r1, r3
; CHECK-ARM-NEXT: cmn r2, #1
; CHECK-ARM-NEXT: movgt r12, #1
; CHECK-ARM-NEXT: subs r1, r4, r12
; CHECK-ARM-NEXT: movne r1, #1
; CHECK-ARM-NEXT: ands r3, lr, r1
; CHECK-ARM-NEXT: asrne r0, r2, #31
; CHECK-ARM-NEXT: mov r1, #-2147483648
; CHECK-ARM-NEXT: cmp r2, #0
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: moveq r1, r2
; CHECK-ARM-NEXT: pop {r4, pc}
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y)
ret i64 %tmp
}
define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: ldr r1, .LCPI2_0
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: blt .LBB2_2
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: .LBB2_2:
; CHECK-T1-NEXT: ldr r1, .LCPI2_1
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: bgt .LBB2_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: .LBB2_4:
; CHECK-T1-NEXT: bx lr
; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.5:
; CHECK-T1-NEXT: .LCPI2_0:
; CHECK-T1-NEXT: .long 32767 @ 0x7fff
; CHECK-T1-NEXT: .LCPI2_1:
; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
;
; CHECK-T2-LABEL: func16:
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: movw r1, #32767
; CHECK-T2-NEXT: cmp r0, r1
; CHECK-T2-NEXT: it lt
; CHECK-T2-NEXT: movlt r1, r0
; CHECK-T2-NEXT: movw r0, #32768
; CHECK-T2-NEXT: cmn.w r1, #32768
; CHECK-T2-NEXT: movt r0, #65535
; CHECK-T2-NEXT: it gt
; CHECK-T2-NEXT: movgt r0, r1
; CHECK-T2-NEXT: bx lr
;
; CHECK-ARM-LABEL: func16:
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: sub r0, r0, r1
; CHECK-ARM-NEXT: mov r1, #255
; CHECK-ARM-NEXT: orr r1, r1, #32512
; CHECK-ARM-NEXT: cmp r0, r1
; CHECK-ARM-NEXT: movlt r1, r0
; CHECK-ARM-NEXT: ldr r0, .LCPI2_0
; CHECK-ARM-NEXT: cmn r1, #32768
; CHECK-ARM-NEXT: movgt r0, r1
; CHECK-ARM-NEXT: bx lr
; CHECK-ARM-NEXT: .p2align 2
; CHECK-ARM-NEXT: @ %bb.1:
; CHECK-ARM-NEXT: .LCPI2_0:
; CHECK-ARM-NEXT: .long 4294934528 @ 0xffff8000
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
ret i16 %tmp
}
define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: movs r1, #127
; CHECK-T1-NEXT: cmp r0, #127
; CHECK-T1-NEXT: blt .LBB3_2
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: .LBB3_2:
; CHECK-T1-NEXT: mvns r1, r1
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: bgt .LBB3_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: .LBB3_4:
; CHECK-T1-NEXT: bx lr
;
; CHECK-T2-LABEL: func8:
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: cmp r0, #127
; CHECK-T2-NEXT: it ge
; CHECK-T2-NEXT: movge r0, #127
; CHECK-T2-NEXT: cmn.w r0, #128
; CHECK-T2-NEXT: it le
; CHECK-T2-NEXT: mvnle r0, #127
; CHECK-T2-NEXT: bx lr
;
; CHECK-ARM-LABEL: func8:
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: sub r0, r0, r1
; CHECK-ARM-NEXT: cmp r0, #127
; CHECK-ARM-NEXT: movge r0, #127
; CHECK-ARM-NEXT: cmn r0, #128
; CHECK-ARM-NEXT: mvnle r0, #127
; CHECK-ARM-NEXT: bx lr
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y)
ret i8 %tmp
}
define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; CHECK-T1-LABEL: func3:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: subs r0, r0, r1
; CHECK-T1-NEXT: movs r1, #7
; CHECK-T1-NEXT: cmp r0, #7
; CHECK-T1-NEXT: blt .LBB4_2
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: .LBB4_2:
; CHECK-T1-NEXT: mvns r1, r1
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: bgt .LBB4_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: .LBB4_4:
; CHECK-T1-NEXT: bx lr
;
; CHECK-T2-LABEL: func3:
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: subs r0, r0, r1
; CHECK-T2-NEXT: cmp r0, #7
; CHECK-T2-NEXT: it ge
; CHECK-T2-NEXT: movge r0, #7
; CHECK-T2-NEXT: cmn.w r0, #8
; CHECK-T2-NEXT: it le
; CHECK-T2-NEXT: mvnle r0, #7
; CHECK-T2-NEXT: bx lr
;
; CHECK-ARM-LABEL: func3:
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: sub r0, r0, r1
; CHECK-ARM-NEXT: cmp r0, #7
; CHECK-ARM-NEXT: movge r0, #7
; CHECK-ARM-NEXT: cmn r0, #8
; CHECK-ARM-NEXT: mvnle r0, #7
; CHECK-ARM-NEXT: bx lr
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y)
ret i4 %tmp
}
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-T1-LABEL: vec:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-T1-NEXT: .pad #12
; CHECK-T1-NEXT: sub sp, #12
; CHECK-T1-NEXT: str r3, [sp] @ 4-byte Spill
; CHECK-T1-NEXT: mov r4, r1
; CHECK-T1-NEXT: mov r1, r0
; CHECK-T1-NEXT: ldr r5, [sp, #32]
; CHECK-T1-NEXT: movs r7, #1
; CHECK-T1-NEXT: movs r0, #0
; CHECK-T1-NEXT: str r0, [sp, #8] @ 4-byte Spill
; CHECK-T1-NEXT: subs r0, r1, r5
; CHECK-T1-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-T1-NEXT: mov r6, r7
; CHECK-T1-NEXT: bmi .LBB5_2
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; CHECK-T1-NEXT: .LBB5_2:
; CHECK-T1-NEXT: lsls r3, r7, #31
; CHECK-T1-NEXT: ldr r0, .LCPI5_0
; CHECK-T1-NEXT: cmp r6, #0
; CHECK-T1-NEXT: mov r6, r0
; CHECK-T1-NEXT: bne .LBB5_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r6, r3
; CHECK-T1-NEXT: .LBB5_4:
; CHECK-T1-NEXT: cmp r1, r5
; CHECK-T1-NEXT: bvc .LBB5_6
; CHECK-T1-NEXT: @ %bb.5:
; CHECK-T1-NEXT: str r6, [sp, #4] @ 4-byte Spill
; CHECK-T1-NEXT: .LBB5_6:
; CHECK-T1-NEXT: ldr r5, [sp, #36]
; CHECK-T1-NEXT: subs r1, r4, r5
; CHECK-T1-NEXT: mov r6, r7
; CHECK-T1-NEXT: bmi .LBB5_8
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; CHECK-T1-NEXT: .LBB5_8:
; CHECK-T1-NEXT: cmp r6, #0
; CHECK-T1-NEXT: mov r6, r0
; CHECK-T1-NEXT: bne .LBB5_10
; CHECK-T1-NEXT: @ %bb.9:
; CHECK-T1-NEXT: mov r6, r3
; CHECK-T1-NEXT: .LBB5_10:
; CHECK-T1-NEXT: cmp r4, r5
; CHECK-T1-NEXT: bvc .LBB5_12
; CHECK-T1-NEXT: @ %bb.11:
; CHECK-T1-NEXT: mov r1, r6
; CHECK-T1-NEXT: .LBB5_12:
; CHECK-T1-NEXT: ldr r5, [sp, #40]
; CHECK-T1-NEXT: subs r4, r2, r5
; CHECK-T1-NEXT: mov r6, r7
; CHECK-T1-NEXT: bmi .LBB5_14
; CHECK-T1-NEXT: @ %bb.13:
; CHECK-T1-NEXT: ldr r6, [sp, #8] @ 4-byte Reload
; CHECK-T1-NEXT: .LBB5_14:
; CHECK-T1-NEXT: cmp r6, #0
; CHECK-T1-NEXT: mov r6, r0
; CHECK-T1-NEXT: bne .LBB5_16
; CHECK-T1-NEXT: @ %bb.15:
; CHECK-T1-NEXT: mov r6, r3
; CHECK-T1-NEXT: .LBB5_16:
; CHECK-T1-NEXT: cmp r2, r5
; CHECK-T1-NEXT: bvc .LBB5_18
; CHECK-T1-NEXT: @ %bb.17:
; CHECK-T1-NEXT: mov r4, r6
; CHECK-T1-NEXT: .LBB5_18:
; CHECK-T1-NEXT: ldr r2, [sp, #44]
; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
; CHECK-T1-NEXT: subs r5, r6, r2
; CHECK-T1-NEXT: bpl .LBB5_23
; CHECK-T1-NEXT: @ %bb.19:
; CHECK-T1-NEXT: cmp r7, #0
; CHECK-T1-NEXT: beq .LBB5_24
; CHECK-T1-NEXT: .LBB5_20:
; CHECK-T1-NEXT: cmp r6, r2
; CHECK-T1-NEXT: bvc .LBB5_22
; CHECK-T1-NEXT: .LBB5_21:
; CHECK-T1-NEXT: mov r5, r0
; CHECK-T1-NEXT: .LBB5_22:
; CHECK-T1-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-T1-NEXT: mov r2, r4
; CHECK-T1-NEXT: mov r3, r5
; CHECK-T1-NEXT: add sp, #12
; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-T1-NEXT: .LBB5_23:
; CHECK-T1-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
; CHECK-T1-NEXT: cmp r7, #0
; CHECK-T1-NEXT: bne .LBB5_20
; CHECK-T1-NEXT: .LBB5_24:
; CHECK-T1-NEXT: mov r0, r3
; CHECK-T1-NEXT: cmp r6, r2
; CHECK-T1-NEXT: bvs .LBB5_21
; CHECK-T1-NEXT: b .LBB5_22
; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.25:
; CHECK-T1-NEXT: .LCPI5_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
;
; CHECK-T2-LABEL: vec:
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-T2-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-T2-NEXT: .pad #4
; CHECK-T2-NEXT: sub sp, #4
; CHECK-T2-NEXT: ldr r4, [sp, #24]
; CHECK-T2-NEXT: mov lr, r0
; CHECK-T2-NEXT: ldr r7, [sp, #28]
; CHECK-T2-NEXT: movs r5, #0
; CHECK-T2-NEXT: subs r6, r0, r4
; CHECK-T2-NEXT: mov.w r0, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r0, #1
; CHECK-T2-NEXT: cmp r0, #0
; CHECK-T2-NEXT: mov.w r0, #-2147483648
; CHECK-T2-NEXT: mov.w r12, #-2147483648
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: mvnne r0, #-2147483648
; CHECK-T2-NEXT: cmp lr, r4
; CHECK-T2-NEXT: it vc
; CHECK-T2-NEXT: movvc r0, r6
; CHECK-T2-NEXT: subs r6, r1, r7
; CHECK-T2-NEXT: mov.w r4, #0
; CHECK-T2-NEXT: mov.w lr, #-2147483648
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r4, #1
; CHECK-T2-NEXT: cmp r4, #0
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: mvnne lr, #-2147483648
; CHECK-T2-NEXT: cmp r1, r7
; CHECK-T2-NEXT: ldr r1, [sp, #32]
; CHECK-T2-NEXT: mov.w r4, #0
; CHECK-T2-NEXT: it vc
; CHECK-T2-NEXT: movvc lr, r6
; CHECK-T2-NEXT: subs r6, r2, r1
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r4, #1
; CHECK-T2-NEXT: cmp r4, #0
; CHECK-T2-NEXT: mov.w r4, #-2147483648
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: mvnne r4, #-2147483648
; CHECK-T2-NEXT: cmp r2, r1
; CHECK-T2-NEXT: ldr r1, [sp, #36]
; CHECK-T2-NEXT: it vc
; CHECK-T2-NEXT: movvc r4, r6
; CHECK-T2-NEXT: subs r2, r3, r1
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: movmi r5, #1
; CHECK-T2-NEXT: cmp r5, #0
; CHECK-T2-NEXT: it ne
; CHECK-T2-NEXT: mvnne r12, #-2147483648
; CHECK-T2-NEXT: cmp r3, r1
; CHECK-T2-NEXT: it vc
; CHECK-T2-NEXT: movvc r12, r2
; CHECK-T2-NEXT: mov r1, lr
; CHECK-T2-NEXT: mov r2, r4
; CHECK-T2-NEXT: mov r3, r12
; CHECK-T2-NEXT: add sp, #4
; CHECK-T2-NEXT: pop {r4, r5, r6, r7, pc}
;
; CHECK-ARM-LABEL: vec:
; CHECK-ARM: @ %bb.0:
; CHECK-ARM-NEXT: .save {r4, r5, r6, r7, r11, lr}
; CHECK-ARM-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-ARM-NEXT: ldr r4, [sp, #24]
; CHECK-ARM-NEXT: mov lr, r0
; CHECK-ARM-NEXT: ldr r7, [sp, #28]
; CHECK-ARM-NEXT: mov r5, #0
; CHECK-ARM-NEXT: subs r6, r0, r4
; CHECK-ARM-NEXT: mov r0, #0
; CHECK-ARM-NEXT: movmi r0, #1
; CHECK-ARM-NEXT: cmp r0, #0
; CHECK-ARM-NEXT: mov r0, #-2147483648
; CHECK-ARM-NEXT: mov r12, #-2147483648
; CHECK-ARM-NEXT: mvnne r0, #-2147483648
; CHECK-ARM-NEXT: cmp lr, r4
; CHECK-ARM-NEXT: movvc r0, r6
; CHECK-ARM-NEXT: subs r6, r1, r7
; CHECK-ARM-NEXT: mov r4, #0
; CHECK-ARM-NEXT: mov lr, #-2147483648
; CHECK-ARM-NEXT: movmi r4, #1
; CHECK-ARM-NEXT: cmp r4, #0
; CHECK-ARM-NEXT: mvnne lr, #-2147483648
; CHECK-ARM-NEXT: cmp r1, r7
; CHECK-ARM-NEXT: ldr r1, [sp, #32]
; CHECK-ARM-NEXT: movvc lr, r6
; CHECK-ARM-NEXT: mov r4, #0
; CHECK-ARM-NEXT: subs r6, r2, r1
; CHECK-ARM-NEXT: movmi r4, #1
; CHECK-ARM-NEXT: cmp r4, #0
; CHECK-ARM-NEXT: mov r4, #-2147483648
; CHECK-ARM-NEXT: mvnne r4, #-2147483648
; CHECK-ARM-NEXT: cmp r2, r1
; CHECK-ARM-NEXT: ldr r1, [sp, #36]
; CHECK-ARM-NEXT: movvc r4, r6
; CHECK-ARM-NEXT: subs r2, r3, r1
; CHECK-ARM-NEXT: movmi r5, #1
; CHECK-ARM-NEXT: cmp r5, #0
; CHECK-ARM-NEXT: mvnne r12, #-2147483648
; CHECK-ARM-NEXT: cmp r3, r1
; CHECK-ARM-NEXT: movvc r12, r2
; CHECK-ARM-NEXT: mov r1, lr
; CHECK-ARM-NEXT: mov r2, r4
; CHECK-ARM-NEXT: mov r3, r12
; CHECK-ARM-NEXT: pop {r4, r5, r6, r7, r11, pc}
%tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %tmp
}
|
