diff options
Diffstat (limited to 'test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir')
| -rw-r--r-- | test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir new file mode 100644 index 00000000000..6903f01ae5a --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir @@ -0,0 +1,130 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600 +--- | + + define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void } + define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void } + define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void } + define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void } + +... +--- +name: add_v16i8 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; P5600-LABEL: name: add_v16i8 + ; P5600: liveins: $a0, $a1, $a2 + ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 + ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a) + ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b) + ; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]] + ; P5600: ST_B [[ADDV_B]], [[COPY2]], 0 :: (store 16 into %ir.c) + ; P5600: RetRA + %0:gprb(p0) = COPY $a0 + %1:gprb(p0) = COPY $a1 + %2:gprb(p0) = COPY $a2 + %3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a) + %4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b) + %5:fprb(<16 x s8>) = G_ADD %4, %3 + G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c) + RetRA + +... +--- +name: add_v8i16 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; P5600-LABEL: name: add_v8i16 + ; P5600: liveins: $a0, $a1, $a2 + ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 + ; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a) + ; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b) + ; P5600: [[ADDV_H:%[0-9]+]]:msa128h = ADDV_H [[LD_H1]], [[LD_H]] + ; P5600: ST_H [[ADDV_H]], [[COPY2]], 0 :: (store 16 into %ir.c) + ; P5600: RetRA + %0:gprb(p0) = COPY $a0 + %1:gprb(p0) = COPY $a1 + %2:gprb(p0) = COPY $a2 + %3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a) + %4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b) + %5:fprb(<8 x s16>) = G_ADD %4, %3 + G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c) + RetRA + +... +--- +name: add_v4i32 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; P5600-LABEL: name: add_v4i32 + ; P5600: liveins: $a0, $a1, $a2 + ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 + ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a) + ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b) + ; P5600: [[ADDV_W:%[0-9]+]]:msa128w = ADDV_W [[LD_W1]], [[LD_W]] + ; P5600: ST_W [[ADDV_W]], [[COPY2]], 0 :: (store 16 into %ir.c) + ; P5600: RetRA + %0:gprb(p0) = COPY $a0 + %1:gprb(p0) = COPY $a1 + %2:gprb(p0) = COPY $a2 + %3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a) + %4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b) + %5:fprb(<4 x s32>) = G_ADD %4, %3 + G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c) + RetRA + +... +--- +name: add_v2i64 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; P5600-LABEL: name: add_v2i64 + ; P5600: liveins: $a0, $a1, $a2 + ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 + ; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a) + ; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b) + ; P5600: [[ADDV_D:%[0-9]+]]:msa128d = ADDV_D [[LD_D1]], [[LD_D]] + ; P5600: ST_D [[ADDV_D]], [[COPY2]], 0 :: (store 16 into %ir.c) + ; P5600: RetRA + %0:gprb(p0) = COPY $a0 + %1:gprb(p0) = COPY $a1 + %2:gprb(p0) = COPY $a2 + %3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a) + %4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b) + %5:fprb(<2 x s64>) = G_ADD %4, %3 + G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c) + RetRA + +... |