diff options
author | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-10-22 14:25:37 +0000 |
---|---|---|
committer | Petar Avramovic <Petar.Avramovic@rt-rk.com> | 2019-10-22 14:25:37 +0000 |
commit | e6fb6db5680e297e0b99739dcfbdb4d72ddd752b (patch) | |
tree | 21969fd96012bfba3cfbd70379a9f615d38185ca /test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir | |
parent | ee57dd49214a7ca74f0b01111bf0ce16d42cecb5 (diff) |
[MIParser] Set RegClassOrRegBank during instruction parsing
MachineRegisterInfo::createGenericVirtualRegister sets
RegClassOrRegBank to static_cast<RegisterBank *>(nullptr).
MIParser on the other hand doesn't. When we attempt to constrain
Register Class on such VReg, additional COPY is generated.
This way we avoid COPY instructions showing in test that have MIR
input while they are not present with llvm-ir input that was used
to create given MIR for a -run-pass test.
Differential Revision: https://reviews.llvm.org/D68946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375502 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir')
-rw-r--r-- | test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir | 32 |
1 files changed, 12 insertions, 20 deletions
diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir b/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir index 2e71669bc9d..e43a38e2c65 100644 --- a/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir +++ b/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir @@ -151,11 +151,9 @@ body: | ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128b = COPY [[LOAD]](<16 x s8>) - ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b = ADDVI_B [[COPY2]], 3 - ; P5600: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ADDVI_B]] - ; P5600: G_STORE [[COPY3]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b(<16 x s8>) = ADDVI_B [[LOAD]](<16 x s8>), 3 + ; P5600: G_STORE [[ADDVI_B]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 @@ -177,11 +175,9 @@ body: | ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128h = COPY [[LOAD]](<8 x s16>) - ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h = ADDVI_H [[COPY2]], 18 - ; P5600: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ADDVI_H]] - ; P5600: G_STORE [[COPY3]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h(<8 x s16>) = ADDVI_H [[LOAD]](<8 x s16>), 18 + ; P5600: G_STORE [[ADDVI_H]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 @@ -203,11 +199,9 @@ body: | ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128w = COPY [[LOAD]](<4 x s32>) - ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w = ADDVI_W [[COPY2]], 25 - ; P5600: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ADDVI_W]] - ; P5600: G_STORE [[COPY3]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25 + ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 @@ -229,11 +223,9 @@ body: | ; P5600: liveins: $a0, $a1 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 - ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) - ; P5600: [[COPY2:%[0-9]+]]:msa128d = COPY [[LOAD]](<2 x s64>) - ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d = ADDVI_D [[COPY2]], 31 - ; P5600: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ADDVI_D]] - ; P5600: G_STORE [[COPY3]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c) + ; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a) + ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d(<2 x s64>) = ADDVI_D [[LOAD]](<2 x s64>), 31 + ; P5600: G_STORE [[ADDVI_D]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c) ; P5600: RetRA %0:_(p0) = COPY $a0 %1:_(p0) = COPY $a1 |