diff options
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 38 |
1 files changed, 29 insertions, 9 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 08c66833a22..2914f10326f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -494,7 +494,8 @@ Objective-C and Objective-C++ Dialects}. -mcaller-super-interworking -mcallee-super-interworking @gol -mtp=@var{name} -mtls-dialect=@var{dialect} @gol -mword-relocations @gol --mfix-cortex-m3-ldrd} +-mfix-cortex-m3-ldrd @gol +-munaligned-access} @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol @@ -883,8 +884,8 @@ See RS/6000 and PowerPC Options. -m5-compact -m5-compact-nofpu @gol -mb -ml -mdalign -mrelax @gol -mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol --mieee -mbitops -misize -minline-ic_invalidate -mpadstruct -mspace @gol --mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol +-mieee -mno-ieee -mbitops -misize -minline-ic_invalidate -mpadstruct @gol +-mspace -mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol -mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol -madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol -maccumulate-outgoing-args -minvalid-symbols -msoft-atomic @gol @@ -10935,6 +10936,23 @@ with overlapping destination and base registers are used. This option avoids generating these instructions. This option is enabled by default when @option{-mcpu=cortex-m3} is specified. +@item -munaligned-access +@itemx -mno-unaligned-access +@opindex munaligned-access +@opindex mno-unaligned-access +Enables (or disables) reading and writing of 16- and 32- bit values +from addresses that are not 16- or 32- bit aligned. By default +unaligned access is disabled for all pre-ARMv6 and all ARMv6-M +architectures, and enabled for all other architectures. If unaligned +access is not enabled then words in packed data structures will be +accessed a byte at a time. + +The ARM attribute @code{Tag_CPU_unaligned_access} will be set in the +generated object file to either true or false, depending upon the +setting of this option. If unaligned access is enabled then the +preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be +defined. + @end table @node AVR Options @@ -17958,13 +17976,15 @@ Mark the @code{MAC} register as call-clobbered, even if @option{-mhitachi} is given. @item -mieee +@item -mno-ieee @opindex mieee -Increase IEEE compliance of floating-point code. -At the moment, this is equivalent to @option{-fno-finite-math-only}. -When generating 16-bit SH opcodes, getting IEEE-conforming results for -comparisons of NANs / infinities incurs extra overhead in every -floating-point comparison, therefore the default is set to -@option{-ffinite-math-only}. +@opindex mnoieee +Control the IEEE compliance of floating-point comparisons, which affects the +handling of cases where the result of a comparison is unordered. By default +@option{-mieee} is implicitly enabled. If @option{-ffinite-math-only} is +enabled @option{-mno-ieee} is implicitly set, which results in faster +floating-point greater-equal and less-equal comparisons. The implcit settings +can be overridden by specifying either @option{-mieee} or @option{-mno-ieee}. @item -minline-ic_invalidate @opindex minline-ic_invalidate |