diff options
| author | Michael Hope <michael.hope@linaro.org> | 2012-03-23 15:48:51 +1300 |
|---|---|---|
| committer | Michael Hope <michael.hope@linaro.org> | 2012-03-23 15:48:51 +1300 |
| commit | 81b66833911c76d16b36d9ab64aab2461f68af64 (patch) | |
| tree | c776fab6e9b6be3cfbbd0b520e4c76304665bcf8 /gcc | |
| parent | a350686ad674f067c9f0eb013d987277e3fbb0c3 (diff) | |
Don't allow arbitrary constants into Neon vector compare.
Backport from mainline r185603:
gcc/
2012-03-20 Richard Earnshaw <rearnsha@arm.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/neon.md | 10 | ||||
| -rw-r--r-- | gcc/config/arm/predicates.md | 9 |
2 files changed, 14 insertions, 5 deletions
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 9a523751843..c0a46d06b85 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2114,7 +2114,7 @@ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w,w") - (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") + (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz") (match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_VCEQ))] "TARGET_NEON" @@ -2133,7 +2133,7 @@ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w,w") - (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") + (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz") (match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_VCGE))] "TARGET_NEON" @@ -2164,7 +2164,7 @@ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w,w") - (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") + (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz") (match_operand:SI 3 "immediate_operand" "i,i")] UNSPEC_VCGT))] "TARGET_NEON" @@ -2198,7 +2198,7 @@ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w") - (match_operand:VDQW 2 "nonmemory_operand" "Dz") + (match_operand:VDQW 2 "zero_operand" "Dz") (match_operand:SI 3 "immediate_operand" "i")] UNSPEC_VCLE))] "TARGET_NEON" @@ -2215,7 +2215,7 @@ [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w") - (match_operand:VDQW 2 "nonmemory_operand" "Dz") + (match_operand:VDQW 2 "zero_operand" "Dz") (match_operand:SI 3 "immediate_operand" "i")] UNSPEC_VCLT))] "TARGET_NEON" diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index dea3a96368e..9171d7377fe 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -89,6 +89,15 @@ && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS))); }) +(define_predicate "zero_operand" + (and (match_code "const_int,const_double,const_vector") + (match_test "op == CONST0_RTX (mode)"))) + +;; Match a register, or zero in the appropriate mode. +(define_predicate "reg_or_zero_operand" + (ior (match_operand 0 "s_register_operand") + (match_operand 0 "zero_operand"))) + (define_special_predicate "subreg_lowpart_operator" (and (match_code "subreg") (match_test "subreg_lowpart_p (op)"))) |