diff options
| author | Christophe Lyon <christophe.lyon@linaro.org> | 2016-02-17 14:18:23 +0100 |
|---|---|---|
| committer | Linaro Code Review <review@review.linaro.org> | 2016-03-14 13:42:10 +0000 |
| commit | 4d05e02e2e1eeaa238c06639949f588a9a2b4417 (patch) | |
| tree | dd6714c32e91336f59f19189a75dc6110bece663 /gcc | |
| parent | 621fee3132cdbec4e81f827d40fa7b1bf11ecb97 (diff) | |
gcc/
Backport from trunk r233460.
2016-02-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
constraints for operand 3.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.
Change-Id: I06d45c5302a927088a5e68bbbf317f73fb69f785
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9ca4617f77b..4cc60889f48 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3096,7 +3096,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCOND> 3 "register_operand" "w") + (match_operand:<VCOND> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3114,7 +3114,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCOND> 3 "register_operand" "w") + (match_operand:<VCOND> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3134,7 +3134,7 @@ [(match_operand:VDQHS 1 "register_operand" "0") (match_operand:VDQHS 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCONQ> 3 "register_operand" "w") + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" @@ -3152,7 +3152,7 @@ [(match_operand:SD_HSI 1 "register_operand" "0") (match_operand:SD_HSI 2 "register_operand" "w") (vec_select:<VEL> - (match_operand:<VCONQ> 3 "register_operand" "w") + (match_operand:<VCONQ> 3 "register_operand" "<vwx>") (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] SQRDMLH_AS))] "TARGET_SIMD_RDMA" |