From 4d05e02e2e1eeaa238c06639949f588a9a2b4417 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Wed, 17 Feb 2016 14:18:23 +0100
Subject: 	gcc/ 	Backport from trunk r233460. 	2016-02-16  James
 Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md
	(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
	constraints for	operand 3.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.

Change-Id: I06d45c5302a927088a5e68bbbf317f73fb69f785
---
 gcc/config/aarch64/aarch64-simd.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'gcc')

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 9ca4617f77b..4cc60889f48 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3096,7 +3096,7 @@
 	  [(match_operand:VDQHS 1 "register_operand" "0")
 	   (match_operand:VDQHS 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCOND> 3 "register_operand" "w")
+	     (match_operand:<VCOND> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3114,7 +3114,7 @@
 	  [(match_operand:SD_HSI 1 "register_operand" "0")
 	   (match_operand:SD_HSI 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCOND> 3 "register_operand" "w")
+	     (match_operand:<VCOND> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3134,7 +3134,7 @@
 	  [(match_operand:VDQHS 1 "register_operand" "0")
 	   (match_operand:VDQHS 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCONQ> 3 "register_operand" "w")
+	     (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
@@ -3152,7 +3152,7 @@
 	  [(match_operand:SD_HSI 1 "register_operand" "0")
 	   (match_operand:SD_HSI 2 "register_operand" "w")
 	   (vec_select:<VEL>
-	     (match_operand:<VCONQ> 3 "register_operand" "w")
+	     (match_operand:<VCONQ> 3 "register_operand" "<vwx>")
 	     (parallel [(match_operand:SI 4 "immediate_operand" "i")]))]
 	  SQRDMLH_AS))]
    "TARGET_SIMD_RDMA"
-- 
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