diff options
| author | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1997-03-20 16:00:49 +0000 |
|---|---|---|
| committer | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1997-03-20 16:00:49 +0000 |
| commit | 7eac600ce904b8f16237d3211b683d2b14c21230 (patch) | |
| tree | 6ca402aa2668332c80822d26f4daf9c18633e5aa /gcc/config/pa | |
| parent | 2dd45a00a5c19036b5e6f1c008456954e57522ee (diff) | |
* pa/pa.c (emit_move_sequence): Don't lose for a secondary reload
to the SAR register if the input is a MEM with an offset that won't
fit in 14bits.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@13753 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa')
| -rw-r--r-- | gcc/config/pa/pa.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 221166fb664..5f9416057df 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -1170,7 +1170,21 @@ emit_move_sequence (operands, mode, scratch_reg) && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))) && scratch_reg) { - emit_move_insn (scratch_reg, operand1); + /* D might not fit in 14 bits either; for such cases load D into + scratch reg. */ + if (GET_CODE (operand1) == MEM + && !memory_address_p (SImode, XEXP (operand1, 0))) + { + emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); + emit_move_insn (scratch_reg, gen_rtx (GET_CODE (XEXP (operand1, 0)), + SImode, + XEXP (XEXP (operand1, 0), 0), + scratch_reg)); + emit_move_insn (scratch_reg, gen_rtx (MEM, GET_MODE (operand1), + scratch_reg)); + } + else + emit_move_insn (scratch_reg, operand1); emit_move_insn (operand0, scratch_reg); return 1; } |