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authorGCC Administrator <gccadmin@gcc.gnu.org>2023-04-17 00:17:00 +0000
committerGCC Administrator <gccadmin@gcc.gnu.org>2023-04-17 00:17:00 +0000
commita167416a239a4afcc7e89d2ccdea3ffa318defac (patch)
treebee7349e3e37cebab2400b00341491b4dca7f1ca
parenta647198fcf7463a42c8e035a429200e7998735dc (diff)
Daily bump.
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/DATESTAMP2
-rw-r--r--gcc/testsuite/ChangeLog10
3 files changed, 17 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c6cdcc3a1db..33e4b506765 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2023-04-16 Jeff Law <jlaw@ventanamicro>
+
+ PR target/109508
+ * config/riscv/riscv.cc (riscv_expand_conditional_move): For
+ TARGET_SFB_ALU, force the true arm into a register.
+
2023-04-15 John David Anglin <danglin@gcc.gnu.org>
PR target/104989
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ba4f30bf048..27b1d3f07db 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230416
+20230417
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 443ba5f48f4..2cda0bfd4e4 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2023-04-16 Jeff Law <jlaw@ventanamicro>
+
+ PR target/109508
+ * gcc.target/riscv/pr109508.c: New test.
+
+2023-04-16 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/54816
+ * gcc.target/avr/pr54816.c: New test case.
+
2023-04-15 Jason Merrill <jason@redhat.com>
PR c++/109357