RISC-V: Allow later passes to recog() (set mem const_double -0.0)

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

4 files changed, 27 insertions, 4 deletions

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 6e301c59106..c8ea56cc9e8 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -98,6 +98,11 @@
   (and (match_code "const_double")
        (match_test "op == CONST0_RTX (mode)")))
 
+(define_constraint "G0n"
+  "@internal"
+  (and (match_code "const_double")
+       (match_test "riscv_const_double_m0_rtx(op)")))
+
 (define_memory_constraint "A"
   "An address that is held in a general-purpose register."
   (and (match_code "mem")
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index de61c468b3a..42f33cb6497 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -57,6 +57,7 @@ extern void riscv_split_doubleword_move (rtx, rtx);
 extern const char *riscv_output_move (rtx, rtx);
 extern const char *riscv_output_return ();
 extern bool riscv_const_double_p0_or_m0_rtx (rtx x);
+extern bool riscv_const_double_m0_rtx (rtx x);
 
 #ifdef RTX_CODE
 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9e22612604a..ffddab6e52c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2143,6 +2143,22 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue)
   REG_NOTES (insn) = dwarf;
 }
 
+/* Return TRUE if rtx X is a FP constant -0.0.  */
+bool
+riscv_const_double_m0_rtx (rtx x)
+{
+  const REAL_VALUE_TYPE *r;
+
+  if (GET_CODE (x) != CONST_DOUBLE)
+    return false;
+
+  r = CONST_DOUBLE_REAL_VALUE (x);
+  if (REAL_VALUE_MINUS_ZERO (*r))
+    return true;
+
+  return false;
+}
+
 /* Return TRUE if rtx X is a FP constant 0.0 or -0.0.  */
 bool
 riscv_const_double_p0_or_m0_rtx (rtx x)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f4312b63d99..d2d63e048d6 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2109,13 +2109,14 @@
    (set_attr "mode" "DF")])
 
 (define_insn "*movdf_hardfloat_rv64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,  f,f,m,  m,*f,*r,    *r,*r,*m")
-	(match_operand:DF 1 "move_operand"         " f,G0p,m,f,G0p,*r,*f,*r*G0p,*m,*r"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,  f,f,m,  m,*f,*r,    *r,*r,*m,  m")
+	(match_operand:DF 1 "move_operand"         " f,G0p,m,f,G0p,*r,*f,*r*G0p,*m,*r,G0n"))]
   "TARGET_64BIT && TARGET_DOUBLE_FLOAT
    && (register_operand (operands[0], DFmode)
-       || reg_or_0_operand (operands[1], DFmode))"
+       || reg_or_0_operand (operands[1], DFmode)
+       || riscv_const_double_p0_or_m0_rtx (operands[1]))"
   { return riscv_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+  [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store,store")
    (set_attr "mode" "DF")])
 
 (define_insn "*movdf_softfloat"