diff options
| author | YunQiang Su <syq@gcc.gnu.org> | 2024-06-20 01:20:36 +0800 |
|---|---|---|
| committer | YunQiang Su <syq@gcc.gnu.org> | 2024-06-25 16:31:00 +0800 |
| commit | 17b368b4b4524ce9d11bf79ce7f58d6825156ce0 (patch) | |
| tree | 66d233cc09256a870a81daf8f7dccf808e92bfd5 | |
| parent | 0b456434fe0f1d64291b7c6b3596c836c9519f85 (diff) | |
MIPS: Implement vcond_mask optabs for MSA
Currently, we have `mips_expand_vec_cond_expr`, which calculate
cmp_res first. We can just add a new extra argument to ask it
to use operands[3] as cmp_res instead of calculating from operands[4]
and operands[5].
gcc
* config/mips/mips.cc(mips_expand_vec_cond_expr): Add extra
argument to info that opernads[3] is cmp_res already.
* config/mips/mips-protos.h(mips_expand_vec_cond_expr): Ditto.
* config/mips/mips-msa.md(vcond_mask): Define new expand.
(vcondu): Use mips_expand_vec_cond_expr with 4th argument.
(vcond): Ditto.
| -rw-r--r-- | gcc/config/mips/mips-msa.md | 17 | ||||
| -rw-r--r-- | gcc/config/mips/mips-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/mips/mips.cc | 18 |
3 files changed, 28 insertions, 9 deletions
diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 779157f2a0c..0081b688ce9 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -411,6 +411,19 @@ DONE; }) +(define_expand "vcond_mask_<MSA:mode><IMSA:mode>" + [(match_operand:MSA 0 "register_operand") + (match_operand:MSA 1 "reg_or_m1_operand") + (match_operand:MSA 2 "reg_or_0_operand") + (match_operand:IMSA 3 "register_operand")] + "ISA_HAS_MSA + && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<IMSA:MODE>mode))" +{ + mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands, true); + DONE; +}) + + (define_expand "vcondu<MSA:mode><IMSA:mode>" [(match_operand:MSA 0 "register_operand") (match_operand:MSA 1 "reg_or_m1_operand") @@ -421,7 +434,7 @@ "ISA_HAS_MSA && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<IMSA:MODE>mode))" { - mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands); + mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands, false); DONE; }) @@ -435,7 +448,7 @@ "ISA_HAS_MSA && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<MSA_2:MODE>mode))" { - mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands); + mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands, false); DONE; }) diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index fcc0a0ae663..75f80984c03 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -385,7 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum rtx_code); #endif extern void mips_register_frame_header_opt (void); -extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *); +extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *, bool); extern void mips_expand_vec_cmp_expr (rtx *); extern void mips_emit_speculation_barrier_function (void); diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 24addfa89aa..7d4791157d1 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -22801,14 +22801,20 @@ mips_expand_vec_cmp_expr (rtx *operands) void mips_expand_vec_cond_expr (machine_mode mode, machine_mode vimode, - rtx *operands) + rtx *operands, bool mask) { - rtx cond = operands[3]; - rtx cmp_op0 = operands[4]; - rtx cmp_op1 = operands[5]; - rtx cmp_res = gen_reg_rtx (vimode); + rtx cmp_res; + if (mask) + cmp_res = operands[3]; + else + { + rtx cond = operands[3]; + rtx cmp_op0 = operands[4]; + rtx cmp_op1 = operands[5]; + cmp_res = gen_reg_rtx (vimode); - mips_expand_msa_cmp (cmp_res, GET_CODE (cond), cmp_op0, cmp_op1); + mips_expand_msa_cmp (cmp_res, GET_CODE (cond), cmp_op0, cmp_op1); + } /* We handle the following cases: 1) r = a CMP b ? -1 : 0 |