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authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2022-05-28 10:02:11 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-06-11 11:44:47 +0200
commit65417e548ad4277ee6b08443fd06d4d8446ed05e (patch)
tree86a70cc3facbbd23cfefb1c0d54729394f4968a0
parent5a9715c26f19675c32a4113867a3a073fa1e8595 (diff)
hw/acpi/piix4: remove unused piix4_pm_initfn() function
This function is now unused and so can be completely removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220528091934.15520-13-mark.cave-ayland@ilande.co.uk> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-rw-r--r--hw/acpi/piix4.c19
-rw-r--r--include/hw/southbridge/piix.h4
2 files changed, 0 insertions, 23 deletions
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 32033bc9d7..0a81f1ad93 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -505,25 +505,6 @@ static void piix4_pm_init(Object *obj)
qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1);
}
-PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
- bool smm_enabled)
-{
- PCIDevice *pci_dev;
- DeviceState *dev;
- PIIX4PMState *s;
-
- pci_dev = pci_new(devfn, TYPE_PIIX4_PM);
- dev = DEVICE(pci_dev);
- qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
- qdev_prop_set_bit(dev, "smm-enabled", smm_enabled);
-
- s = PIIX4_PM(dev);
-
- pci_realize_and_unref(pci_dev, bus, &error_fatal);
-
- return s;
-}
-
static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
{
PIIX4PMState *s = opaque;
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b69e0dfb04..976b4da582 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -14,10 +14,6 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
-#include "hw/acpi/piix4.h"
-
-PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
- bool smm_enabled);
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60