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| author | Tri Vo <trong@android.com> | 2018-09-12 23:45:04 +0000 |
|---|---|---|
| committer | Tri Vo <trong@android.com> | 2018-09-12 23:45:04 +0000 |
| commit | 6e8abbc8b94e071b5cf046918fda7d99ca4b151c (patch) | |
| tree | 00d42c606f348d00275a2746d382cbf9e6e85430 /clang/docs | |
| parent | da36f3f4820a3d9aa20cd32b9ca21e54f53bec82 (diff) | |
[AArch64] Support reserving x1-7 registers.
Summary: Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.
Reviewers: javed.absar, efriedma, nickdesaulniers, srhines, phosek
Reviewed By: nickdesaulniers
Subscribers: manojgupta, jfb, cfe-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D48581
llvm-svn: 342100
Diffstat (limited to 'clang/docs')
| -rw-r--r-- | clang/docs/ClangCommandLineReference.rst | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst index b60c4ed42f3c..2ba544b06b4b 100644 --- a/clang/docs/ClangCommandLineReference.rst +++ b/clang/docs/ClangCommandLineReference.rst @@ -2298,6 +2298,34 @@ The thread model to use, e.g. posix, single (posix by default) AARCH64 ------- +.. option:: -ffixed-x1 + +Reserve the x1 register (AArch64 only) + +.. option:: -ffixed-x2 + +Reserve the x2 register (AArch64 only) + +.. option:: -ffixed-x3 + +Reserve the x3 register (AArch64 only) + +.. option:: -ffixed-x4 + +Reserve the x4 register (AArch64 only) + +.. option:: -ffixed-x5 + +Reserve the x5 register (AArch64 only) + +.. option:: -ffixed-x6 + +Reserve the x6 register (AArch64 only) + +.. option:: -ffixed-x7 + +Reserve the x7 register (AArch64 only) + .. option:: -ffixed-x18 Reserve the x18 register (AArch64 only) |