diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:56 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:56 +0000 |
| commit | e14c9cb6c88e3dbcbaef4e0f62f8e07ece17b51b (patch) | |
| tree | aba47ab38cf70e915e3dd89b2b4530f64ab1f147 | |
| parent | 175eafaf378659f6798c5b1b7591e9a3b1abd042 (diff) | |
aarch64: Add id_aa64isar2_el1
Armv8.8-A defines a read-only system register called id_aa64isar2_el1.
The register was previously RES0 and should therefore be accepted
at all architecture levels.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en]
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Add id_aa64isar2_el1.
gas/
* testsuite/gas/aarch64/sysreg-diagnostic.s: Test writes to
id_aa64isar2_el1.
* testsuite/gas/aarch64/sysreg-diagnostic.d: Update accordingly.
* testsuite/gas/aarch64/sysreg-diagnostic.l: Likewise.
* testsuite/gas/aarch64/sysreg.s: Test reads from
id_aa64isar2_el1.
* testsuite/gas/aarch64/sysreg.d: Update accordingly.
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-diagnostic.d | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-diagnostic.l | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-diagnostic.s | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg.s | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 |
6 files changed, 9 insertions, 0 deletions
diff --git a/gas/testsuite/gas/aarch64/sysreg-diagnostic.d b/gas/testsuite/gas/aarch64/sysreg-diagnostic.d index fb39db20d2..7059fbe3c8 100644 --- a/gas/testsuite/gas/aarch64/sysreg-diagnostic.d +++ b/gas/testsuite/gas/aarch64/sysreg-diagnostic.d @@ -12,3 +12,4 @@ Disassembly of section \.text: .*: d5330503 mrs x3, dbgdtrrx_el0 .*: d5330503 mrs x3, dbgdtrrx_el0 .*: d5180003 msr midr_el1, x3 // note: writing to a read-only register +.*: d5180640 msr id_aa64isar2_el1, x0 // note: writing to a read-only register diff --git a/gas/testsuite/gas/aarch64/sysreg-diagnostic.l b/gas/testsuite/gas/aarch64/sysreg-diagnostic.l index 4566652dc6..e9a41a2a3d 100644 --- a/gas/testsuite/gas/aarch64/sysreg-diagnostic.l +++ b/gas/testsuite/gas/aarch64/sysreg-diagnostic.l @@ -2,3 +2,4 @@ .*:3: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3' .*:5: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0' .*:6: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3' +.*:7: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64isar2_el1,x0' diff --git a/gas/testsuite/gas/aarch64/sysreg-diagnostic.s b/gas/testsuite/gas/aarch64/sysreg-diagnostic.s index 5f68fe60bd..a689cdceae 100644 --- a/gas/testsuite/gas/aarch64/sysreg-diagnostic.s +++ b/gas/testsuite/gas/aarch64/sysreg-diagnostic.s @@ -4,3 +4,4 @@ mrs x3, dbgdtrrx_el0 mrs x3, dbgdtrtx_el0 msr midr_el1, x3 + msr id_aa64isar2_el1, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg.d b/gas/testsuite/gas/aarch64/sysreg.d index 5da20c9984..704666d48c 100644 --- a/gas/testsuite/gas/aarch64/sysreg.d +++ b/gas/testsuite/gas/aarch64/sysreg.d @@ -29,3 +29,5 @@ Disassembly of section \.text: 54: d5184b00 msr s3_0_c4_c11_0, x0 58: d5310300 mrs x0, trcstatr 5c: d5110300 msr trcstatr, x0 + 60: d5380640 mrs x0, id_aa64isar2_el1 + 64: d538065e mrs x30, id_aa64isar2_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg.s b/gas/testsuite/gas/aarch64/sysreg.s index fa797284f2..f2e75a863a 100644 --- a/gas/testsuite/gas/aarch64/sysreg.s +++ b/gas/testsuite/gas/aarch64/sysreg.s @@ -30,3 +30,6 @@ mrs x0, s2_1_c0_c3_0 msr s2_1_c0_c3_0, x0 + + mrs x0, id_aa64isar2_el1 + mrs x30, id_aa64isar2_el1 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 289df9e884..9b7d7efd43 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4082,6 +4082,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("id_aa64dfr1_el1", CPENC (3,0,C0,C5,1), F_REG_READ), SR_CORE ("id_aa64isar0_el1", CPENC (3,0,C0,C6,0), F_REG_READ), SR_CORE ("id_aa64isar1_el1", CPENC (3,0,C0,C6,1), F_REG_READ), + SR_CORE ("id_aa64isar2_el1", CPENC (3,0,C0,C6,2), F_REG_READ), SR_CORE ("id_aa64mmfr0_el1", CPENC (3,0,C0,C7,0), F_REG_READ), SR_CORE ("id_aa64mmfr1_el1", CPENC (3,0,C0,C7,1), F_REG_READ), SR_CORE ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ), |