diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2022-03-31 17:51:16 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2022-03-31 17:51:16 +0100 |
| commit | 025f768ffc3aeb5561bb60a9c8f3841faa53bd6f (patch) | |
| tree | 9c98019e7d6d7849a2fe4b627060a6ef1d2b1e1d | |
| parent | fa8a0804b8fd7599367147754b4c82d555860374 (diff) | |
aarch64: Relax check for RNG system registers
FEAT_RNG is an optional Armv8.5-A extension, but it can be backported
to earlier architectures as well. GAS previously made the RNG registers
conditional on having both armv8.5-a and +rng, but only +rng should be
required.
This seems to be the only feature that was handled like this.
opcodes/
* aarch64-opc.c (SR_RNG): Don't require V8_5.
gas/
* testsuite/gas/aarch64/rng-1.s, testsuite/gas/aarch64/rng-1.d: New
test.
| -rw-r--r-- | gas/testsuite/gas/aarch64/rng-1.d | 10 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/rng-1.s | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 2 |
3 files changed, 14 insertions, 1 deletions
diff --git a/gas/testsuite/gas/aarch64/rng-1.d b/gas/testsuite/gas/aarch64/rng-1.d new file mode 100644 index 0000000000..8c65cba1d0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rng-1.d @@ -0,0 +1,10 @@ +#source: rng-1.s +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +.*: d53b2405 mrs x5, rndr +.*: d53b2426 mrs x6, rndrrs diff --git a/gas/testsuite/gas/aarch64/rng-1.s b/gas/testsuite/gas/aarch64/rng-1.s new file mode 100644 index 0000000000..3565897b29 --- /dev/null +++ b/gas/testsuite/gas/aarch64/rng-1.s @@ -0,0 +1,3 @@ + .arch armv8.4-a+rng + mrs x5, rndr + mrs x6, rndrrs diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4774eba2e5..37f6dae07a 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3974,7 +3974,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, SYSREG ((n), (e), (f) | F_ARCHEXT, \ AARCH64_FEATURE_##fe1 | AARCH64_FEATURE_##fe2) -#define SR_RNG(n,e,f) SR_FEAT2(n,e,f,RNG,V8_5) #define SR_V8_1_A(n,e,f) SR_FEAT2(n,e,f,V8_A,V8_1) #define SR_V8_4_A(n,e,f) SR_FEAT2(n,e,f,V8_A,V8_4) @@ -3994,6 +3993,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, #define SR_LOR(n,e,f) SR_FEAT (n,e,f,LOR) #define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN) #define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS) +#define SR_RNG(n,e,f) SR_FEAT (n,e,f,RNG) #define SR_SME(n,e,f) SR_FEAT (n,e,f,SME) #define SR_SSBS(n,e,f) SR_FEAT (n,e,f,SSBS) #define SR_SVE(n,e,f) SR_FEAT (n,e,f,SVE) |